1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/ioport.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/scatterlist.h>
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <linux/stat.h>
31 #include <linux/types.h>
32 #include <linux/platform_data/atmel.h>
33
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/sdio.h>
36
37 #include <mach/atmel-mci.h>
38 #include <linux/atmel-mci.h>
39 #include <linux/atmel_pdc.h>
40
41 #include <asm/cacheflush.h>
42 #include <asm/io.h>
43 #include <asm/unaligned.h>
44
45 #include "atmel-mci-regs.h"
46
47 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
48 #define ATMCI_DMA_THRESHOLD 16
49
50 enum {
51 EVENT_CMD_RDY = 0,
52 EVENT_XFER_COMPLETE,
53 EVENT_NOTBUSY,
54 EVENT_DATA_ERROR,
55 };
56
57 enum atmel_mci_state {
58 STATE_IDLE = 0,
59 STATE_SENDING_CMD,
60 STATE_DATA_XFER,
61 STATE_WAITING_NOTBUSY,
62 STATE_SENDING_STOP,
63 STATE_END_REQUEST,
64 };
65
66 enum atmci_xfer_dir {
67 XFER_RECEIVE = 0,
68 XFER_TRANSMIT,
69 };
70
71 enum atmci_pdc_buf {
72 PDC_FIRST_BUF = 0,
73 PDC_SECOND_BUF,
74 };
75
76 struct atmel_mci_caps {
77 bool has_dma_conf_reg;
78 bool has_pdc;
79 bool has_cfg_reg;
80 bool has_cstor_reg;
81 bool has_highspeed;
82 bool has_rwproof;
83 bool has_odd_clk_div;
84 bool has_bad_data_ordering;
85 bool need_reset_after_xfer;
86 bool need_blksz_mul_4;
87 bool need_notbusy_for_read_ops;
88 };
89
90 struct atmel_mci_dma {
91 struct dma_chan *chan;
92 struct dma_async_tx_descriptor *data_desc;
93 };
94
95 /**
96 * struct atmel_mci - MMC controller state shared between all slots
97 * @lock: Spinlock protecting the queue and associated data.
98 * @regs: Pointer to MMIO registers.
99 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
100 * @pio_offset: Offset into the current scatterlist entry.
101 * @buffer: Buffer used if we don't have the r/w proof capability. We
102 * don't have the time to switch pdc buffers so we have to use only
103 * one buffer for the full transaction.
104 * @buf_size: size of the buffer.
105 * @phys_buf_addr: buffer address needed for pdc.
106 * @cur_slot: The slot which is currently using the controller.
107 * @mrq: The request currently being processed on @cur_slot,
108 * or NULL if the controller is idle.
109 * @cmd: The command currently being sent to the card, or NULL.
110 * @data: The data currently being transferred, or NULL if no data
111 * transfer is in progress.
112 * @data_size: just data->blocks * data->blksz.
113 * @dma: DMA client state.
114 * @data_chan: DMA channel being used for the current data transfer.
115 * @cmd_status: Snapshot of SR taken upon completion of the current
116 * command. Only valid when EVENT_CMD_COMPLETE is pending.
117 * @data_status: Snapshot of SR taken upon completion of the current
118 * data transfer. Only valid when EVENT_DATA_COMPLETE or
119 * EVENT_DATA_ERROR is pending.
120 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
121 * to be sent.
122 * @tasklet: Tasklet running the request state machine.
123 * @pending_events: Bitmask of events flagged by the interrupt handler
124 * to be processed by the tasklet.
125 * @completed_events: Bitmask of events which the state machine has
126 * processed.
127 * @state: Tasklet state.
128 * @queue: List of slots waiting for access to the controller.
129 * @need_clock_update: Update the clock rate before the next request.
130 * @need_reset: Reset controller before next request.
131 * @timer: Timer to balance the data timeout error flag which cannot rise.
132 * @mode_reg: Value of the MR register.
133 * @cfg_reg: Value of the CFG register.
134 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
135 * rate and timeout calculations.
136 * @mapbase: Physical address of the MMIO registers.
137 * @mck: The peripheral bus clock hooked up to the MMC controller.
138 * @pdev: Platform device associated with the MMC controller.
139 * @slot: Slots sharing this MMC controller.
140 * @caps: MCI capabilities depending on MCI version.
141 * @prepare_data: function to setup MCI before data transfer which
142 * depends on MCI capabilities.
143 * @submit_data: function to start data transfer which depends on MCI
144 * capabilities.
145 * @stop_transfer: function to stop data transfer which depends on MCI
146 * capabilities.
147 *
148 * Locking
149 * =======
150 *
151 * @lock is a softirq-safe spinlock protecting @queue as well as
152 * @cur_slot, @mrq and @state. These must always be updated
153 * at the same time while holding @lock.
154 *
155 * @lock also protects mode_reg and need_clock_update since these are
156 * used to synchronize mode register updates with the queue
157 * processing.
158 *
159 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
160 * and must always be written at the same time as the slot is added to
161 * @queue.
162 *
163 * @pending_events and @completed_events are accessed using atomic bit
164 * operations, so they don't need any locking.
165 *
166 * None of the fields touched by the interrupt handler need any
167 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
168 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
169 * interrupts must be disabled and @data_status updated with a
170 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
171 * CMDRDY interrupt must be disabled and @cmd_status updated with a
172 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
173 * bytes_xfered field of @data must be written. This is ensured by
174 * using barriers.
175 */
176 struct atmel_mci {
177 spinlock_t lock;
178 void __iomem *regs;
179
180 struct scatterlist *sg;
181 unsigned int sg_len;
182 unsigned int pio_offset;
183 unsigned int *buffer;
184 unsigned int buf_size;
185 dma_addr_t buf_phys_addr;
186
187 struct atmel_mci_slot *cur_slot;
188 struct mmc_request *mrq;
189 struct mmc_command *cmd;
190 struct mmc_data *data;
191 unsigned int data_size;
192
193 struct atmel_mci_dma dma;
194 struct dma_chan *data_chan;
195 struct dma_slave_config dma_conf;
196
197 u32 cmd_status;
198 u32 data_status;
199 u32 stop_cmdr;
200
201 struct tasklet_struct tasklet;
202 unsigned long pending_events;
203 unsigned long completed_events;
204 enum atmel_mci_state state;
205 struct list_head queue;
206
207 bool need_clock_update;
208 bool need_reset;
209 struct timer_list timer;
210 u32 mode_reg;
211 u32 cfg_reg;
212 unsigned long bus_hz;
213 unsigned long mapbase;
214 struct clk *mck;
215 struct platform_device *pdev;
216
217 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
218
219 struct atmel_mci_caps caps;
220
221 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
222 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
223 void (*stop_transfer)(struct atmel_mci *host);
224 };
225
226 /**
227 * struct atmel_mci_slot - MMC slot state
228 * @mmc: The mmc_host representing this slot.
229 * @host: The MMC controller this slot is using.
230 * @sdc_reg: Value of SDCR to be written before using this slot.
231 * @sdio_irq: SDIO irq mask for this slot.
232 * @mrq: mmc_request currently being processed or waiting to be
233 * processed, or NULL when the slot is idle.
234 * @queue_node: List node for placing this node in the @queue list of
235 * &struct atmel_mci.
236 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
237 * @flags: Random state bits associated with the slot.
238 * @detect_pin: GPIO pin used for card detection, or negative if not
239 * available.
240 * @wp_pin: GPIO pin used for card write protect sending, or negative
241 * if not available.
242 * @detect_is_active_high: The state of the detect pin when it is active.
243 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
244 */
245 struct atmel_mci_slot {
246 struct mmc_host *mmc;
247 struct atmel_mci *host;
248
249 u32 sdc_reg;
250 u32 sdio_irq;
251
252 struct mmc_request *mrq;
253 struct list_head queue_node;
254
255 unsigned int clock;
256 unsigned long flags;
257 #define ATMCI_CARD_PRESENT 0
258 #define ATMCI_CARD_NEED_INIT 1
259 #define ATMCI_SHUTDOWN 2
260
261 int detect_pin;
262 int wp_pin;
263 bool detect_is_active_high;
264
265 struct timer_list detect_timer;
266 };
267
268 #define atmci_test_and_clear_pending(host, event) \
269 test_and_clear_bit(event, &host->pending_events)
270 #define atmci_set_completed(host, event) \
271 set_bit(event, &host->completed_events)
272 #define atmci_set_pending(host, event) \
273 set_bit(event, &host->pending_events)
274
275 /*
276 * The debugfs stuff below is mostly optimized away when
277 * CONFIG_DEBUG_FS is not set.
278 */
atmci_req_show(struct seq_file * s,void * v)279 static int atmci_req_show(struct seq_file *s, void *v)
280 {
281 struct atmel_mci_slot *slot = s->private;
282 struct mmc_request *mrq;
283 struct mmc_command *cmd;
284 struct mmc_command *stop;
285 struct mmc_data *data;
286
287 /* Make sure we get a consistent snapshot */
288 spin_lock_bh(&slot->host->lock);
289 mrq = slot->mrq;
290
291 if (mrq) {
292 cmd = mrq->cmd;
293 data = mrq->data;
294 stop = mrq->stop;
295
296 if (cmd)
297 seq_printf(s,
298 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
299 cmd->opcode, cmd->arg, cmd->flags,
300 cmd->resp[0], cmd->resp[1], cmd->resp[2],
301 cmd->resp[3], cmd->error);
302 if (data)
303 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
304 data->bytes_xfered, data->blocks,
305 data->blksz, data->flags, data->error);
306 if (stop)
307 seq_printf(s,
308 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
309 stop->opcode, stop->arg, stop->flags,
310 stop->resp[0], stop->resp[1], stop->resp[2],
311 stop->resp[3], stop->error);
312 }
313
314 spin_unlock_bh(&slot->host->lock);
315
316 return 0;
317 }
318
atmci_req_open(struct inode * inode,struct file * file)319 static int atmci_req_open(struct inode *inode, struct file *file)
320 {
321 return single_open(file, atmci_req_show, inode->i_private);
322 }
323
324 static const struct file_operations atmci_req_fops = {
325 .owner = THIS_MODULE,
326 .open = atmci_req_open,
327 .read = seq_read,
328 .llseek = seq_lseek,
329 .release = single_release,
330 };
331
atmci_show_status_reg(struct seq_file * s,const char * regname,u32 value)332 static void atmci_show_status_reg(struct seq_file *s,
333 const char *regname, u32 value)
334 {
335 static const char *sr_bit[] = {
336 [0] = "CMDRDY",
337 [1] = "RXRDY",
338 [2] = "TXRDY",
339 [3] = "BLKE",
340 [4] = "DTIP",
341 [5] = "NOTBUSY",
342 [6] = "ENDRX",
343 [7] = "ENDTX",
344 [8] = "SDIOIRQA",
345 [9] = "SDIOIRQB",
346 [12] = "SDIOWAIT",
347 [14] = "RXBUFF",
348 [15] = "TXBUFE",
349 [16] = "RINDE",
350 [17] = "RDIRE",
351 [18] = "RCRCE",
352 [19] = "RENDE",
353 [20] = "RTOE",
354 [21] = "DCRCE",
355 [22] = "DTOE",
356 [23] = "CSTOE",
357 [24] = "BLKOVRE",
358 [25] = "DMADONE",
359 [26] = "FIFOEMPTY",
360 [27] = "XFRDONE",
361 [30] = "OVRE",
362 [31] = "UNRE",
363 };
364 unsigned int i;
365
366 seq_printf(s, "%s:\t0x%08x", regname, value);
367 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
368 if (value & (1 << i)) {
369 if (sr_bit[i])
370 seq_printf(s, " %s", sr_bit[i]);
371 else
372 seq_puts(s, " UNKNOWN");
373 }
374 }
375 seq_putc(s, '\n');
376 }
377
atmci_regs_show(struct seq_file * s,void * v)378 static int atmci_regs_show(struct seq_file *s, void *v)
379 {
380 struct atmel_mci *host = s->private;
381 u32 *buf;
382 int ret = 0;
383
384
385 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
386 if (!buf)
387 return -ENOMEM;
388
389 /*
390 * Grab a more or less consistent snapshot. Note that we're
391 * not disabling interrupts, so IMR and SR may not be
392 * consistent.
393 */
394 ret = clk_prepare_enable(host->mck);
395 if (ret)
396 goto out;
397
398 spin_lock_bh(&host->lock);
399 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
400 spin_unlock_bh(&host->lock);
401
402 clk_disable_unprepare(host->mck);
403
404 seq_printf(s, "MR:\t0x%08x%s%s ",
405 buf[ATMCI_MR / 4],
406 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
407 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
408 if (host->caps.has_odd_clk_div)
409 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
410 ((buf[ATMCI_MR / 4] & 0xff) << 1)
411 | ((buf[ATMCI_MR / 4] >> 16) & 1));
412 else
413 seq_printf(s, "CLKDIV=%u\n",
414 (buf[ATMCI_MR / 4] & 0xff));
415 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
416 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
417 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
418 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
419 buf[ATMCI_BLKR / 4],
420 buf[ATMCI_BLKR / 4] & 0xffff,
421 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
422 if (host->caps.has_cstor_reg)
423 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
424
425 /* Don't read RSPR and RDR; it will consume the data there */
426
427 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
428 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
429
430 if (host->caps.has_dma_conf_reg) {
431 u32 val;
432
433 val = buf[ATMCI_DMA / 4];
434 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
435 val, val & 3,
436 ((val >> 4) & 3) ?
437 1 << (((val >> 4) & 3) + 1) : 1,
438 val & ATMCI_DMAEN ? " DMAEN" : "");
439 }
440 if (host->caps.has_cfg_reg) {
441 u32 val;
442
443 val = buf[ATMCI_CFG / 4];
444 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
445 val,
446 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
447 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
448 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
449 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
450 }
451
452 out:
453 kfree(buf);
454
455 return ret;
456 }
457
atmci_regs_open(struct inode * inode,struct file * file)458 static int atmci_regs_open(struct inode *inode, struct file *file)
459 {
460 return single_open(file, atmci_regs_show, inode->i_private);
461 }
462
463 static const struct file_operations atmci_regs_fops = {
464 .owner = THIS_MODULE,
465 .open = atmci_regs_open,
466 .read = seq_read,
467 .llseek = seq_lseek,
468 .release = single_release,
469 };
470
atmci_init_debugfs(struct atmel_mci_slot * slot)471 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
472 {
473 struct mmc_host *mmc = slot->mmc;
474 struct atmel_mci *host = slot->host;
475 struct dentry *root;
476 struct dentry *node;
477
478 root = mmc->debugfs_root;
479 if (!root)
480 return;
481
482 node = debugfs_create_file("regs", S_IRUSR, root, host,
483 &atmci_regs_fops);
484 if (IS_ERR(node))
485 return;
486 if (!node)
487 goto err;
488
489 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
490 if (!node)
491 goto err;
492
493 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
494 if (!node)
495 goto err;
496
497 node = debugfs_create_x32("pending_events", S_IRUSR, root,
498 (u32 *)&host->pending_events);
499 if (!node)
500 goto err;
501
502 node = debugfs_create_x32("completed_events", S_IRUSR, root,
503 (u32 *)&host->completed_events);
504 if (!node)
505 goto err;
506
507 return;
508
509 err:
510 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
511 }
512
513 #if defined(CONFIG_OF)
514 static const struct of_device_id atmci_dt_ids[] = {
515 { .compatible = "atmel,hsmci" },
516 { /* sentinel */ }
517 };
518
519 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
520
521 static struct mci_platform_data*
atmci_of_init(struct platform_device * pdev)522 atmci_of_init(struct platform_device *pdev)
523 {
524 struct device_node *np = pdev->dev.of_node;
525 struct device_node *cnp;
526 struct mci_platform_data *pdata;
527 u32 slot_id;
528
529 if (!np) {
530 dev_err(&pdev->dev, "device node not found\n");
531 return ERR_PTR(-EINVAL);
532 }
533
534 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
535 if (!pdata) {
536 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
537 return ERR_PTR(-ENOMEM);
538 }
539
540 for_each_child_of_node(np, cnp) {
541 if (of_property_read_u32(cnp, "reg", &slot_id)) {
542 dev_warn(&pdev->dev, "reg property is missing for %s\n",
543 cnp->full_name);
544 continue;
545 }
546
547 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
548 dev_warn(&pdev->dev, "can't have more than %d slots\n",
549 ATMCI_MAX_NR_SLOTS);
550 break;
551 }
552
553 if (of_property_read_u32(cnp, "bus-width",
554 &pdata->slot[slot_id].bus_width))
555 pdata->slot[slot_id].bus_width = 1;
556
557 pdata->slot[slot_id].detect_pin =
558 of_get_named_gpio(cnp, "cd-gpios", 0);
559
560 pdata->slot[slot_id].detect_is_active_high =
561 of_property_read_bool(cnp, "cd-inverted");
562
563 pdata->slot[slot_id].wp_pin =
564 of_get_named_gpio(cnp, "wp-gpios", 0);
565 }
566
567 return pdata;
568 }
569 #else /* CONFIG_OF */
570 static inline struct mci_platform_data*
atmci_of_init(struct platform_device * dev)571 atmci_of_init(struct platform_device *dev)
572 {
573 return ERR_PTR(-EINVAL);
574 }
575 #endif
576
atmci_get_version(struct atmel_mci * host)577 static inline unsigned int atmci_get_version(struct atmel_mci *host)
578 {
579 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
580 }
581
atmci_timeout_timer(unsigned long data)582 static void atmci_timeout_timer(unsigned long data)
583 {
584 struct atmel_mci *host;
585
586 host = (struct atmel_mci *)data;
587
588 dev_dbg(&host->pdev->dev, "software timeout\n");
589
590 if (host->mrq->cmd->data) {
591 host->mrq->cmd->data->error = -ETIMEDOUT;
592 host->data = NULL;
593 /*
594 * With some SDIO modules, sometimes DMA transfer hangs. If
595 * stop_transfer() is not called then the DMA request is not
596 * removed, following ones are queued and never computed.
597 */
598 if (host->state == STATE_DATA_XFER)
599 host->stop_transfer(host);
600 } else {
601 host->mrq->cmd->error = -ETIMEDOUT;
602 host->cmd = NULL;
603 }
604 host->need_reset = 1;
605 host->state = STATE_END_REQUEST;
606 smp_wmb();
607 tasklet_schedule(&host->tasklet);
608 }
609
atmci_ns_to_clocks(struct atmel_mci * host,unsigned int ns)610 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
611 unsigned int ns)
612 {
613 /*
614 * It is easier here to use us instead of ns for the timeout,
615 * it prevents from overflows during calculation.
616 */
617 unsigned int us = DIV_ROUND_UP(ns, 1000);
618
619 /* Maximum clock frequency is host->bus_hz/2 */
620 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
621 }
622
atmci_set_timeout(struct atmel_mci * host,struct atmel_mci_slot * slot,struct mmc_data * data)623 static void atmci_set_timeout(struct atmel_mci *host,
624 struct atmel_mci_slot *slot, struct mmc_data *data)
625 {
626 static unsigned dtomul_to_shift[] = {
627 0, 4, 7, 8, 10, 12, 16, 20
628 };
629 unsigned timeout;
630 unsigned dtocyc;
631 unsigned dtomul;
632
633 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
634 + data->timeout_clks;
635
636 for (dtomul = 0; dtomul < 8; dtomul++) {
637 unsigned shift = dtomul_to_shift[dtomul];
638 dtocyc = (timeout + (1 << shift) - 1) >> shift;
639 if (dtocyc < 15)
640 break;
641 }
642
643 if (dtomul >= 8) {
644 dtomul = 7;
645 dtocyc = 15;
646 }
647
648 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
649 dtocyc << dtomul_to_shift[dtomul]);
650 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
651 }
652
653 /*
654 * Return mask with command flags to be enabled for this command.
655 */
atmci_prepare_command(struct mmc_host * mmc,struct mmc_command * cmd)656 static u32 atmci_prepare_command(struct mmc_host *mmc,
657 struct mmc_command *cmd)
658 {
659 struct mmc_data *data;
660 u32 cmdr;
661
662 cmd->error = -EINPROGRESS;
663
664 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
665
666 if (cmd->flags & MMC_RSP_PRESENT) {
667 if (cmd->flags & MMC_RSP_136)
668 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
669 else
670 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
671 }
672
673 /*
674 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
675 * it's too difficult to determine whether this is an ACMD or
676 * not. Better make it 64.
677 */
678 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
679
680 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
681 cmdr |= ATMCI_CMDR_OPDCMD;
682
683 data = cmd->data;
684 if (data) {
685 cmdr |= ATMCI_CMDR_START_XFER;
686
687 if (cmd->opcode == SD_IO_RW_EXTENDED) {
688 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
689 } else {
690 if (data->flags & MMC_DATA_STREAM)
691 cmdr |= ATMCI_CMDR_STREAM;
692 else if (data->blocks > 1)
693 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
694 else
695 cmdr |= ATMCI_CMDR_BLOCK;
696 }
697
698 if (data->flags & MMC_DATA_READ)
699 cmdr |= ATMCI_CMDR_TRDIR_READ;
700 }
701
702 return cmdr;
703 }
704
atmci_send_command(struct atmel_mci * host,struct mmc_command * cmd,u32 cmd_flags)705 static void atmci_send_command(struct atmel_mci *host,
706 struct mmc_command *cmd, u32 cmd_flags)
707 {
708 WARN_ON(host->cmd);
709 host->cmd = cmd;
710
711 dev_vdbg(&host->pdev->dev,
712 "start command: ARGR=0x%08x CMDR=0x%08x\n",
713 cmd->arg, cmd_flags);
714
715 atmci_writel(host, ATMCI_ARGR, cmd->arg);
716 atmci_writel(host, ATMCI_CMDR, cmd_flags);
717 }
718
atmci_send_stop_cmd(struct atmel_mci * host,struct mmc_data * data)719 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
720 {
721 dev_dbg(&host->pdev->dev, "send stop command\n");
722 atmci_send_command(host, data->stop, host->stop_cmdr);
723 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
724 }
725
726 /*
727 * Configure given PDC buffer taking care of alignement issues.
728 * Update host->data_size and host->sg.
729 */
atmci_pdc_set_single_buf(struct atmel_mci * host,enum atmci_xfer_dir dir,enum atmci_pdc_buf buf_nb)730 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
731 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
732 {
733 u32 pointer_reg, counter_reg;
734 unsigned int buf_size;
735
736 if (dir == XFER_RECEIVE) {
737 pointer_reg = ATMEL_PDC_RPR;
738 counter_reg = ATMEL_PDC_RCR;
739 } else {
740 pointer_reg = ATMEL_PDC_TPR;
741 counter_reg = ATMEL_PDC_TCR;
742 }
743
744 if (buf_nb == PDC_SECOND_BUF) {
745 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
746 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
747 }
748
749 if (!host->caps.has_rwproof) {
750 buf_size = host->buf_size;
751 atmci_writel(host, pointer_reg, host->buf_phys_addr);
752 } else {
753 buf_size = sg_dma_len(host->sg);
754 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
755 }
756
757 if (host->data_size <= buf_size) {
758 if (host->data_size & 0x3) {
759 /* If size is different from modulo 4, transfer bytes */
760 atmci_writel(host, counter_reg, host->data_size);
761 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
762 } else {
763 /* Else transfer 32-bits words */
764 atmci_writel(host, counter_reg, host->data_size / 4);
765 }
766 host->data_size = 0;
767 } else {
768 /* We assume the size of a page is 32-bits aligned */
769 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
770 host->data_size -= sg_dma_len(host->sg);
771 if (host->data_size)
772 host->sg = sg_next(host->sg);
773 }
774 }
775
776 /*
777 * Configure PDC buffer according to the data size ie configuring one or two
778 * buffers. Don't use this function if you want to configure only the second
779 * buffer. In this case, use atmci_pdc_set_single_buf.
780 */
atmci_pdc_set_both_buf(struct atmel_mci * host,int dir)781 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
782 {
783 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
784 if (host->data_size)
785 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
786 }
787
788 /*
789 * Unmap sg lists, called when transfer is finished.
790 */
atmci_pdc_cleanup(struct atmel_mci * host)791 static void atmci_pdc_cleanup(struct atmel_mci *host)
792 {
793 struct mmc_data *data = host->data;
794
795 if (data)
796 dma_unmap_sg(&host->pdev->dev,
797 data->sg, data->sg_len,
798 ((data->flags & MMC_DATA_WRITE)
799 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
800 }
801
802 /*
803 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
804 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
805 * interrupt needed for both transfer directions.
806 */
atmci_pdc_complete(struct atmel_mci * host)807 static void atmci_pdc_complete(struct atmel_mci *host)
808 {
809 int transfer_size = host->data->blocks * host->data->blksz;
810 int i;
811
812 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
813
814 if ((!host->caps.has_rwproof)
815 && (host->data->flags & MMC_DATA_READ)) {
816 if (host->caps.has_bad_data_ordering)
817 for (i = 0; i < transfer_size; i++)
818 host->buffer[i] = swab32(host->buffer[i]);
819 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
820 host->buffer, transfer_size);
821 }
822
823 atmci_pdc_cleanup(host);
824
825 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
826 atmci_set_pending(host, EVENT_XFER_COMPLETE);
827 tasklet_schedule(&host->tasklet);
828 }
829
atmci_dma_cleanup(struct atmel_mci * host)830 static void atmci_dma_cleanup(struct atmel_mci *host)
831 {
832 struct mmc_data *data = host->data;
833
834 if (data)
835 dma_unmap_sg(host->dma.chan->device->dev,
836 data->sg, data->sg_len,
837 ((data->flags & MMC_DATA_WRITE)
838 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
839 }
840
841 /*
842 * This function is called by the DMA driver from tasklet context.
843 */
atmci_dma_complete(void * arg)844 static void atmci_dma_complete(void *arg)
845 {
846 struct atmel_mci *host = arg;
847 struct mmc_data *data = host->data;
848
849 dev_vdbg(&host->pdev->dev, "DMA complete\n");
850
851 if (host->caps.has_dma_conf_reg)
852 /* Disable DMA hardware handshaking on MCI */
853 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
854
855 atmci_dma_cleanup(host);
856
857 /*
858 * If the card was removed, data will be NULL. No point trying
859 * to send the stop command or waiting for NBUSY in this case.
860 */
861 if (data) {
862 dev_dbg(&host->pdev->dev,
863 "(%s) set pending xfer complete\n", __func__);
864 atmci_set_pending(host, EVENT_XFER_COMPLETE);
865 tasklet_schedule(&host->tasklet);
866
867 /*
868 * Regardless of what the documentation says, we have
869 * to wait for NOTBUSY even after block read
870 * operations.
871 *
872 * When the DMA transfer is complete, the controller
873 * may still be reading the CRC from the card, i.e.
874 * the data transfer is still in progress and we
875 * haven't seen all the potential error bits yet.
876 *
877 * The interrupt handler will schedule a different
878 * tasklet to finish things up when the data transfer
879 * is completely done.
880 *
881 * We may not complete the mmc request here anyway
882 * because the mmc layer may call back and cause us to
883 * violate the "don't submit new operations from the
884 * completion callback" rule of the dma engine
885 * framework.
886 */
887 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
888 }
889 }
890
891 /*
892 * Returns a mask of interrupt flags to be enabled after the whole
893 * request has been prepared.
894 */
atmci_prepare_data(struct atmel_mci * host,struct mmc_data * data)895 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
896 {
897 u32 iflags;
898
899 data->error = -EINPROGRESS;
900
901 host->sg = data->sg;
902 host->sg_len = data->sg_len;
903 host->data = data;
904 host->data_chan = NULL;
905
906 iflags = ATMCI_DATA_ERROR_FLAGS;
907
908 /*
909 * Errata: MMC data write operation with less than 12
910 * bytes is impossible.
911 *
912 * Errata: MCI Transmit Data Register (TDR) FIFO
913 * corruption when length is not multiple of 4.
914 */
915 if (data->blocks * data->blksz < 12
916 || (data->blocks * data->blksz) & 3)
917 host->need_reset = true;
918
919 host->pio_offset = 0;
920 if (data->flags & MMC_DATA_READ)
921 iflags |= ATMCI_RXRDY;
922 else
923 iflags |= ATMCI_TXRDY;
924
925 return iflags;
926 }
927
928 /*
929 * Set interrupt flags and set block length into the MCI mode register even
930 * if this value is also accessible in the MCI block register. It seems to be
931 * necessary before the High Speed MCI version. It also map sg and configure
932 * PDC registers.
933 */
934 static u32
atmci_prepare_data_pdc(struct atmel_mci * host,struct mmc_data * data)935 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
936 {
937 u32 iflags, tmp;
938 unsigned int sg_len;
939 enum dma_data_direction dir;
940 int i;
941
942 data->error = -EINPROGRESS;
943
944 host->data = data;
945 host->sg = data->sg;
946 iflags = ATMCI_DATA_ERROR_FLAGS;
947
948 /* Enable pdc mode */
949 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
950
951 if (data->flags & MMC_DATA_READ) {
952 dir = DMA_FROM_DEVICE;
953 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
954 } else {
955 dir = DMA_TO_DEVICE;
956 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
957 }
958
959 /* Set BLKLEN */
960 tmp = atmci_readl(host, ATMCI_MR);
961 tmp &= 0x0000ffff;
962 tmp |= ATMCI_BLKLEN(data->blksz);
963 atmci_writel(host, ATMCI_MR, tmp);
964
965 /* Configure PDC */
966 host->data_size = data->blocks * data->blksz;
967 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
968
969 if ((!host->caps.has_rwproof)
970 && (host->data->flags & MMC_DATA_WRITE)) {
971 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
972 host->buffer, host->data_size);
973 if (host->caps.has_bad_data_ordering)
974 for (i = 0; i < host->data_size; i++)
975 host->buffer[i] = swab32(host->buffer[i]);
976 }
977
978 if (host->data_size)
979 atmci_pdc_set_both_buf(host,
980 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
981
982 return iflags;
983 }
984
985 static u32
atmci_prepare_data_dma(struct atmel_mci * host,struct mmc_data * data)986 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
987 {
988 struct dma_chan *chan;
989 struct dma_async_tx_descriptor *desc;
990 struct scatterlist *sg;
991 unsigned int i;
992 enum dma_data_direction direction;
993 enum dma_transfer_direction slave_dirn;
994 unsigned int sglen;
995 u32 maxburst;
996 u32 iflags;
997
998 data->error = -EINPROGRESS;
999
1000 WARN_ON(host->data);
1001 host->sg = NULL;
1002 host->data = data;
1003
1004 iflags = ATMCI_DATA_ERROR_FLAGS;
1005
1006 /*
1007 * We don't do DMA on "complex" transfers, i.e. with
1008 * non-word-aligned buffers or lengths. Also, we don't bother
1009 * with all the DMA setup overhead for short transfers.
1010 */
1011 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1012 return atmci_prepare_data(host, data);
1013 if (data->blksz & 3)
1014 return atmci_prepare_data(host, data);
1015
1016 for_each_sg(data->sg, sg, data->sg_len, i) {
1017 if (sg->offset & 3 || sg->length & 3)
1018 return atmci_prepare_data(host, data);
1019 }
1020
1021 /* If we don't have a channel, we can't do DMA */
1022 chan = host->dma.chan;
1023 if (chan)
1024 host->data_chan = chan;
1025
1026 if (!chan)
1027 return -ENODEV;
1028
1029 if (data->flags & MMC_DATA_READ) {
1030 direction = DMA_FROM_DEVICE;
1031 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1032 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1033 } else {
1034 direction = DMA_TO_DEVICE;
1035 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1036 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1037 }
1038
1039 if (host->caps.has_dma_conf_reg)
1040 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1041 ATMCI_DMAEN);
1042
1043 sglen = dma_map_sg(chan->device->dev, data->sg,
1044 data->sg_len, direction);
1045
1046 dmaengine_slave_config(chan, &host->dma_conf);
1047 desc = dmaengine_prep_slave_sg(chan,
1048 data->sg, sglen, slave_dirn,
1049 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050 if (!desc)
1051 goto unmap_exit;
1052
1053 host->dma.data_desc = desc;
1054 desc->callback = atmci_dma_complete;
1055 desc->callback_param = host;
1056
1057 return iflags;
1058 unmap_exit:
1059 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1060 return -ENOMEM;
1061 }
1062
1063 static void
atmci_submit_data(struct atmel_mci * host,struct mmc_data * data)1064 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1065 {
1066 return;
1067 }
1068
1069 /*
1070 * Start PDC according to transfer direction.
1071 */
1072 static void
atmci_submit_data_pdc(struct atmel_mci * host,struct mmc_data * data)1073 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1074 {
1075 if (data->flags & MMC_DATA_READ)
1076 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1077 else
1078 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1079 }
1080
1081 static void
atmci_submit_data_dma(struct atmel_mci * host,struct mmc_data * data)1082 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1083 {
1084 struct dma_chan *chan = host->data_chan;
1085 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1086
1087 if (chan) {
1088 dmaengine_submit(desc);
1089 dma_async_issue_pending(chan);
1090 }
1091 }
1092
atmci_stop_transfer(struct atmel_mci * host)1093 static void atmci_stop_transfer(struct atmel_mci *host)
1094 {
1095 dev_dbg(&host->pdev->dev,
1096 "(%s) set pending xfer complete\n", __func__);
1097 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1098 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1099 }
1100
1101 /*
1102 * Stop data transfer because error(s) occurred.
1103 */
atmci_stop_transfer_pdc(struct atmel_mci * host)1104 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1105 {
1106 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1107 }
1108
atmci_stop_transfer_dma(struct atmel_mci * host)1109 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1110 {
1111 struct dma_chan *chan = host->data_chan;
1112
1113 if (chan) {
1114 dmaengine_terminate_all(chan);
1115 atmci_dma_cleanup(host);
1116 } else {
1117 /* Data transfer was stopped by the interrupt handler */
1118 dev_dbg(&host->pdev->dev,
1119 "(%s) set pending xfer complete\n", __func__);
1120 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1121 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1122 }
1123 }
1124
1125 /*
1126 * Start a request: prepare data if needed, prepare the command and activate
1127 * interrupts.
1128 */
atmci_start_request(struct atmel_mci * host,struct atmel_mci_slot * slot)1129 static void atmci_start_request(struct atmel_mci *host,
1130 struct atmel_mci_slot *slot)
1131 {
1132 struct mmc_request *mrq;
1133 struct mmc_command *cmd;
1134 struct mmc_data *data;
1135 u32 iflags;
1136 u32 cmdflags;
1137
1138 mrq = slot->mrq;
1139 host->cur_slot = slot;
1140 host->mrq = mrq;
1141
1142 host->pending_events = 0;
1143 host->completed_events = 0;
1144 host->cmd_status = 0;
1145 host->data_status = 0;
1146
1147 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1148
1149 if (host->need_reset || host->caps.need_reset_after_xfer) {
1150 iflags = atmci_readl(host, ATMCI_IMR);
1151 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1152 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1153 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1154 atmci_writel(host, ATMCI_MR, host->mode_reg);
1155 if (host->caps.has_cfg_reg)
1156 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1157 atmci_writel(host, ATMCI_IER, iflags);
1158 host->need_reset = false;
1159 }
1160 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1161
1162 iflags = atmci_readl(host, ATMCI_IMR);
1163 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1164 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1165 iflags);
1166
1167 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1168 /* Send init sequence (74 clock cycles) */
1169 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1170 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1171 cpu_relax();
1172 }
1173 iflags = 0;
1174 data = mrq->data;
1175 if (data) {
1176 atmci_set_timeout(host, slot, data);
1177
1178 /* Must set block count/size before sending command */
1179 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1180 | ATMCI_BLKLEN(data->blksz));
1181 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1182 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1183
1184 iflags |= host->prepare_data(host, data);
1185 }
1186
1187 iflags |= ATMCI_CMDRDY;
1188 cmd = mrq->cmd;
1189 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1190
1191 /*
1192 * DMA transfer should be started before sending the command to avoid
1193 * unexpected errors especially for read operations in SDIO mode.
1194 * Unfortunately, in PDC mode, command has to be sent before starting
1195 * the transfer.
1196 */
1197 if (host->submit_data != &atmci_submit_data_dma)
1198 atmci_send_command(host, cmd, cmdflags);
1199
1200 if (data)
1201 host->submit_data(host, data);
1202
1203 if (host->submit_data == &atmci_submit_data_dma)
1204 atmci_send_command(host, cmd, cmdflags);
1205
1206 if (mrq->stop) {
1207 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1208 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1209 if (!(data->flags & MMC_DATA_WRITE))
1210 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1211 if (data->flags & MMC_DATA_STREAM)
1212 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1213 else
1214 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1215 }
1216
1217 /*
1218 * We could have enabled interrupts earlier, but I suspect
1219 * that would open up a nice can of interesting race
1220 * conditions (e.g. command and data complete, but stop not
1221 * prepared yet.)
1222 */
1223 atmci_writel(host, ATMCI_IER, iflags);
1224
1225 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1226 }
1227
atmci_queue_request(struct atmel_mci * host,struct atmel_mci_slot * slot,struct mmc_request * mrq)1228 static void atmci_queue_request(struct atmel_mci *host,
1229 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1230 {
1231 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1232 host->state);
1233
1234 spin_lock_bh(&host->lock);
1235 slot->mrq = mrq;
1236 if (host->state == STATE_IDLE) {
1237 host->state = STATE_SENDING_CMD;
1238 atmci_start_request(host, slot);
1239 } else {
1240 dev_dbg(&host->pdev->dev, "queue request\n");
1241 list_add_tail(&slot->queue_node, &host->queue);
1242 }
1243 spin_unlock_bh(&host->lock);
1244 }
1245
atmci_request(struct mmc_host * mmc,struct mmc_request * mrq)1246 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1247 {
1248 struct atmel_mci_slot *slot = mmc_priv(mmc);
1249 struct atmel_mci *host = slot->host;
1250 struct mmc_data *data;
1251
1252 WARN_ON(slot->mrq);
1253 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1254
1255 /*
1256 * We may "know" the card is gone even though there's still an
1257 * electrical connection. If so, we really need to communicate
1258 * this to the MMC core since there won't be any more
1259 * interrupts as the card is completely removed. Otherwise,
1260 * the MMC core might believe the card is still there even
1261 * though the card was just removed very slowly.
1262 */
1263 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1264 mrq->cmd->error = -ENOMEDIUM;
1265 mmc_request_done(mmc, mrq);
1266 return;
1267 }
1268
1269 /* We don't support multiple blocks of weird lengths. */
1270 data = mrq->data;
1271 if (data && data->blocks > 1 && data->blksz & 3) {
1272 mrq->cmd->error = -EINVAL;
1273 mmc_request_done(mmc, mrq);
1274 }
1275
1276 atmci_queue_request(host, slot, mrq);
1277 }
1278
atmci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1279 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1280 {
1281 struct atmel_mci_slot *slot = mmc_priv(mmc);
1282 struct atmel_mci *host = slot->host;
1283 unsigned int i;
1284 bool unprepare_clk;
1285
1286 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1287 switch (ios->bus_width) {
1288 case MMC_BUS_WIDTH_1:
1289 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1290 break;
1291 case MMC_BUS_WIDTH_4:
1292 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1293 break;
1294 }
1295
1296 if (ios->clock) {
1297 unsigned int clock_min = ~0U;
1298 int clkdiv;
1299
1300 clk_prepare(host->mck);
1301 unprepare_clk = true;
1302
1303 spin_lock_bh(&host->lock);
1304 if (!host->mode_reg) {
1305 clk_enable(host->mck);
1306 unprepare_clk = false;
1307 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1308 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1309 if (host->caps.has_cfg_reg)
1310 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1311 }
1312
1313 /*
1314 * Use mirror of ios->clock to prevent race with mmc
1315 * core ios update when finding the minimum.
1316 */
1317 slot->clock = ios->clock;
1318 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1319 if (host->slot[i] && host->slot[i]->clock
1320 && host->slot[i]->clock < clock_min)
1321 clock_min = host->slot[i]->clock;
1322 }
1323
1324 /* Calculate clock divider */
1325 if (host->caps.has_odd_clk_div) {
1326 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1327 if (clkdiv < 0) {
1328 dev_warn(&mmc->class_dev,
1329 "clock %u too fast; using %lu\n",
1330 clock_min, host->bus_hz / 2);
1331 clkdiv = 0;
1332 } else if (clkdiv > 511) {
1333 dev_warn(&mmc->class_dev,
1334 "clock %u too slow; using %lu\n",
1335 clock_min, host->bus_hz / (511 + 2));
1336 clkdiv = 511;
1337 }
1338 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1339 | ATMCI_MR_CLKODD(clkdiv & 1);
1340 } else {
1341 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1342 if (clkdiv > 255) {
1343 dev_warn(&mmc->class_dev,
1344 "clock %u too slow; using %lu\n",
1345 clock_min, host->bus_hz / (2 * 256));
1346 clkdiv = 255;
1347 }
1348 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1349 }
1350
1351 /*
1352 * WRPROOF and RDPROOF prevent overruns/underruns by
1353 * stopping the clock when the FIFO is full/empty.
1354 * This state is not expected to last for long.
1355 */
1356 if (host->caps.has_rwproof)
1357 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1358
1359 if (host->caps.has_cfg_reg) {
1360 /* setup High Speed mode in relation with card capacity */
1361 if (ios->timing == MMC_TIMING_SD_HS)
1362 host->cfg_reg |= ATMCI_CFG_HSMODE;
1363 else
1364 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1365 }
1366
1367 if (list_empty(&host->queue)) {
1368 atmci_writel(host, ATMCI_MR, host->mode_reg);
1369 if (host->caps.has_cfg_reg)
1370 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1371 } else {
1372 host->need_clock_update = true;
1373 }
1374
1375 spin_unlock_bh(&host->lock);
1376 } else {
1377 bool any_slot_active = false;
1378
1379 unprepare_clk = false;
1380
1381 spin_lock_bh(&host->lock);
1382 slot->clock = 0;
1383 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1384 if (host->slot[i] && host->slot[i]->clock) {
1385 any_slot_active = true;
1386 break;
1387 }
1388 }
1389 if (!any_slot_active) {
1390 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1391 if (host->mode_reg) {
1392 atmci_readl(host, ATMCI_MR);
1393 clk_disable(host->mck);
1394 unprepare_clk = true;
1395 }
1396 host->mode_reg = 0;
1397 }
1398 spin_unlock_bh(&host->lock);
1399 }
1400
1401 if (unprepare_clk)
1402 clk_unprepare(host->mck);
1403
1404 switch (ios->power_mode) {
1405 case MMC_POWER_OFF:
1406 if (!IS_ERR(mmc->supply.vmmc))
1407 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1408 break;
1409 case MMC_POWER_UP:
1410 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1411 if (!IS_ERR(mmc->supply.vmmc))
1412 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1413 break;
1414 default:
1415 /*
1416 * TODO: None of the currently available AVR32-based
1417 * boards allow MMC power to be turned off. Implement
1418 * power control when this can be tested properly.
1419 *
1420 * We also need to hook this into the clock management
1421 * somehow so that newly inserted cards aren't
1422 * subjected to a fast clock before we have a chance
1423 * to figure out what the maximum rate is. Currently,
1424 * there's no way to avoid this, and there never will
1425 * be for boards that don't support power control.
1426 */
1427 break;
1428 }
1429 }
1430
atmci_get_ro(struct mmc_host * mmc)1431 static int atmci_get_ro(struct mmc_host *mmc)
1432 {
1433 int read_only = -ENOSYS;
1434 struct atmel_mci_slot *slot = mmc_priv(mmc);
1435
1436 if (gpio_is_valid(slot->wp_pin)) {
1437 read_only = gpio_get_value(slot->wp_pin);
1438 dev_dbg(&mmc->class_dev, "card is %s\n",
1439 read_only ? "read-only" : "read-write");
1440 }
1441
1442 return read_only;
1443 }
1444
atmci_get_cd(struct mmc_host * mmc)1445 static int atmci_get_cd(struct mmc_host *mmc)
1446 {
1447 int present = -ENOSYS;
1448 struct atmel_mci_slot *slot = mmc_priv(mmc);
1449
1450 if (gpio_is_valid(slot->detect_pin)) {
1451 present = !(gpio_get_value(slot->detect_pin) ^
1452 slot->detect_is_active_high);
1453 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1454 present ? "" : "not ");
1455 }
1456
1457 return present;
1458 }
1459
atmci_enable_sdio_irq(struct mmc_host * mmc,int enable)1460 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1461 {
1462 struct atmel_mci_slot *slot = mmc_priv(mmc);
1463 struct atmel_mci *host = slot->host;
1464
1465 if (enable)
1466 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1467 else
1468 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1469 }
1470
1471 static const struct mmc_host_ops atmci_ops = {
1472 .request = atmci_request,
1473 .set_ios = atmci_set_ios,
1474 .get_ro = atmci_get_ro,
1475 .get_cd = atmci_get_cd,
1476 .enable_sdio_irq = atmci_enable_sdio_irq,
1477 };
1478
1479 /* Called with host->lock held */
atmci_request_end(struct atmel_mci * host,struct mmc_request * mrq)1480 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1481 __releases(&host->lock)
1482 __acquires(&host->lock)
1483 {
1484 struct atmel_mci_slot *slot = NULL;
1485 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1486
1487 WARN_ON(host->cmd || host->data);
1488
1489 /*
1490 * Update the MMC clock rate if necessary. This may be
1491 * necessary if set_ios() is called when a different slot is
1492 * busy transferring data.
1493 */
1494 if (host->need_clock_update) {
1495 atmci_writel(host, ATMCI_MR, host->mode_reg);
1496 if (host->caps.has_cfg_reg)
1497 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1498 }
1499
1500 host->cur_slot->mrq = NULL;
1501 host->mrq = NULL;
1502 if (!list_empty(&host->queue)) {
1503 slot = list_entry(host->queue.next,
1504 struct atmel_mci_slot, queue_node);
1505 list_del(&slot->queue_node);
1506 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1507 mmc_hostname(slot->mmc));
1508 host->state = STATE_SENDING_CMD;
1509 atmci_start_request(host, slot);
1510 } else {
1511 dev_vdbg(&host->pdev->dev, "list empty\n");
1512 host->state = STATE_IDLE;
1513 }
1514
1515 del_timer(&host->timer);
1516
1517 spin_unlock(&host->lock);
1518 mmc_request_done(prev_mmc, mrq);
1519 spin_lock(&host->lock);
1520 }
1521
atmci_command_complete(struct atmel_mci * host,struct mmc_command * cmd)1522 static void atmci_command_complete(struct atmel_mci *host,
1523 struct mmc_command *cmd)
1524 {
1525 u32 status = host->cmd_status;
1526
1527 /* Read the response from the card (up to 16 bytes) */
1528 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1529 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1530 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1531 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1532
1533 if (status & ATMCI_RTOE)
1534 cmd->error = -ETIMEDOUT;
1535 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1536 cmd->error = -EILSEQ;
1537 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1538 cmd->error = -EIO;
1539 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1540 if (host->caps.need_blksz_mul_4) {
1541 cmd->error = -EINVAL;
1542 host->need_reset = 1;
1543 }
1544 } else
1545 cmd->error = 0;
1546 }
1547
atmci_detect_change(unsigned long data)1548 static void atmci_detect_change(unsigned long data)
1549 {
1550 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1551 bool present;
1552 bool present_old;
1553
1554 /*
1555 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1556 * freeing the interrupt. We must not re-enable the interrupt
1557 * if it has been freed, and if we're shutting down, it
1558 * doesn't really matter whether the card is present or not.
1559 */
1560 smp_rmb();
1561 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1562 return;
1563
1564 enable_irq(gpio_to_irq(slot->detect_pin));
1565 present = !(gpio_get_value(slot->detect_pin) ^
1566 slot->detect_is_active_high);
1567 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1568
1569 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1570 present, present_old);
1571
1572 if (present != present_old) {
1573 struct atmel_mci *host = slot->host;
1574 struct mmc_request *mrq;
1575
1576 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1577 present ? "inserted" : "removed");
1578
1579 spin_lock(&host->lock);
1580
1581 if (!present)
1582 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1583 else
1584 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1585
1586 /* Clean up queue if present */
1587 mrq = slot->mrq;
1588 if (mrq) {
1589 if (mrq == host->mrq) {
1590 /*
1591 * Reset controller to terminate any ongoing
1592 * commands or data transfers.
1593 */
1594 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1595 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1596 atmci_writel(host, ATMCI_MR, host->mode_reg);
1597 if (host->caps.has_cfg_reg)
1598 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1599
1600 host->data = NULL;
1601 host->cmd = NULL;
1602
1603 switch (host->state) {
1604 case STATE_IDLE:
1605 break;
1606 case STATE_SENDING_CMD:
1607 mrq->cmd->error = -ENOMEDIUM;
1608 if (mrq->data)
1609 host->stop_transfer(host);
1610 break;
1611 case STATE_DATA_XFER:
1612 mrq->data->error = -ENOMEDIUM;
1613 host->stop_transfer(host);
1614 break;
1615 case STATE_WAITING_NOTBUSY:
1616 mrq->data->error = -ENOMEDIUM;
1617 break;
1618 case STATE_SENDING_STOP:
1619 mrq->stop->error = -ENOMEDIUM;
1620 break;
1621 case STATE_END_REQUEST:
1622 break;
1623 }
1624
1625 atmci_request_end(host, mrq);
1626 } else {
1627 list_del(&slot->queue_node);
1628 mrq->cmd->error = -ENOMEDIUM;
1629 if (mrq->data)
1630 mrq->data->error = -ENOMEDIUM;
1631 if (mrq->stop)
1632 mrq->stop->error = -ENOMEDIUM;
1633
1634 spin_unlock(&host->lock);
1635 mmc_request_done(slot->mmc, mrq);
1636 spin_lock(&host->lock);
1637 }
1638 }
1639 spin_unlock(&host->lock);
1640
1641 mmc_detect_change(slot->mmc, 0);
1642 }
1643 }
1644
atmci_tasklet_func(unsigned long priv)1645 static void atmci_tasklet_func(unsigned long priv)
1646 {
1647 struct atmel_mci *host = (struct atmel_mci *)priv;
1648 struct mmc_request *mrq = host->mrq;
1649 struct mmc_data *data = host->data;
1650 enum atmel_mci_state state = host->state;
1651 enum atmel_mci_state prev_state;
1652 u32 status;
1653
1654 spin_lock(&host->lock);
1655
1656 state = host->state;
1657
1658 dev_vdbg(&host->pdev->dev,
1659 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1660 state, host->pending_events, host->completed_events,
1661 atmci_readl(host, ATMCI_IMR));
1662
1663 do {
1664 prev_state = state;
1665 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1666
1667 switch (state) {
1668 case STATE_IDLE:
1669 break;
1670
1671 case STATE_SENDING_CMD:
1672 /*
1673 * Command has been sent, we are waiting for command
1674 * ready. Then we have three next states possible:
1675 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1676 * command needing it or DATA_XFER if there is data.
1677 */
1678 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1679 if (!atmci_test_and_clear_pending(host,
1680 EVENT_CMD_RDY))
1681 break;
1682
1683 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1684 host->cmd = NULL;
1685 atmci_set_completed(host, EVENT_CMD_RDY);
1686 atmci_command_complete(host, mrq->cmd);
1687 if (mrq->data) {
1688 dev_dbg(&host->pdev->dev,
1689 "command with data transfer");
1690 /*
1691 * If there is a command error don't start
1692 * data transfer.
1693 */
1694 if (mrq->cmd->error) {
1695 host->stop_transfer(host);
1696 host->data = NULL;
1697 atmci_writel(host, ATMCI_IDR,
1698 ATMCI_TXRDY | ATMCI_RXRDY
1699 | ATMCI_DATA_ERROR_FLAGS);
1700 state = STATE_END_REQUEST;
1701 } else
1702 state = STATE_DATA_XFER;
1703 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1704 dev_dbg(&host->pdev->dev,
1705 "command response need waiting notbusy");
1706 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1707 state = STATE_WAITING_NOTBUSY;
1708 } else
1709 state = STATE_END_REQUEST;
1710
1711 break;
1712
1713 case STATE_DATA_XFER:
1714 if (atmci_test_and_clear_pending(host,
1715 EVENT_DATA_ERROR)) {
1716 dev_dbg(&host->pdev->dev, "set completed data error\n");
1717 atmci_set_completed(host, EVENT_DATA_ERROR);
1718 state = STATE_END_REQUEST;
1719 break;
1720 }
1721
1722 /*
1723 * A data transfer is in progress. The event expected
1724 * to move to the next state depends of data transfer
1725 * type (PDC or DMA). Once transfer done we can move
1726 * to the next step which is WAITING_NOTBUSY in write
1727 * case and directly SENDING_STOP in read case.
1728 */
1729 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1730 if (!atmci_test_and_clear_pending(host,
1731 EVENT_XFER_COMPLETE))
1732 break;
1733
1734 dev_dbg(&host->pdev->dev,
1735 "(%s) set completed xfer complete\n",
1736 __func__);
1737 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1738
1739 if (host->caps.need_notbusy_for_read_ops ||
1740 (host->data->flags & MMC_DATA_WRITE)) {
1741 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1742 state = STATE_WAITING_NOTBUSY;
1743 } else if (host->mrq->stop) {
1744 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1745 atmci_send_stop_cmd(host, data);
1746 state = STATE_SENDING_STOP;
1747 } else {
1748 host->data = NULL;
1749 data->bytes_xfered = data->blocks * data->blksz;
1750 data->error = 0;
1751 state = STATE_END_REQUEST;
1752 }
1753 break;
1754
1755 case STATE_WAITING_NOTBUSY:
1756 /*
1757 * We can be in the state for two reasons: a command
1758 * requiring waiting not busy signal (stop command
1759 * included) or a write operation. In the latest case,
1760 * we need to send a stop command.
1761 */
1762 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1763 if (!atmci_test_and_clear_pending(host,
1764 EVENT_NOTBUSY))
1765 break;
1766
1767 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1768 atmci_set_completed(host, EVENT_NOTBUSY);
1769
1770 if (host->data) {
1771 /*
1772 * For some commands such as CMD53, even if
1773 * there is data transfer, there is no stop
1774 * command to send.
1775 */
1776 if (host->mrq->stop) {
1777 atmci_writel(host, ATMCI_IER,
1778 ATMCI_CMDRDY);
1779 atmci_send_stop_cmd(host, data);
1780 state = STATE_SENDING_STOP;
1781 } else {
1782 host->data = NULL;
1783 data->bytes_xfered = data->blocks
1784 * data->blksz;
1785 data->error = 0;
1786 state = STATE_END_REQUEST;
1787 }
1788 } else
1789 state = STATE_END_REQUEST;
1790 break;
1791
1792 case STATE_SENDING_STOP:
1793 /*
1794 * In this state, it is important to set host->data to
1795 * NULL (which is tested in the waiting notbusy state)
1796 * in order to go to the end request state instead of
1797 * sending stop again.
1798 */
1799 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1800 if (!atmci_test_and_clear_pending(host,
1801 EVENT_CMD_RDY))
1802 break;
1803
1804 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1805 host->cmd = NULL;
1806 data->bytes_xfered = data->blocks * data->blksz;
1807 data->error = 0;
1808 atmci_command_complete(host, mrq->stop);
1809 if (mrq->stop->error) {
1810 host->stop_transfer(host);
1811 atmci_writel(host, ATMCI_IDR,
1812 ATMCI_TXRDY | ATMCI_RXRDY
1813 | ATMCI_DATA_ERROR_FLAGS);
1814 state = STATE_END_REQUEST;
1815 } else {
1816 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1817 state = STATE_WAITING_NOTBUSY;
1818 }
1819 host->data = NULL;
1820 break;
1821
1822 case STATE_END_REQUEST:
1823 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1824 | ATMCI_DATA_ERROR_FLAGS);
1825 status = host->data_status;
1826 if (unlikely(status)) {
1827 host->stop_transfer(host);
1828 host->data = NULL;
1829 if (data) {
1830 if (status & ATMCI_DTOE) {
1831 data->error = -ETIMEDOUT;
1832 } else if (status & ATMCI_DCRCE) {
1833 data->error = -EILSEQ;
1834 } else {
1835 data->error = -EIO;
1836 }
1837 }
1838 }
1839
1840 atmci_request_end(host, host->mrq);
1841 state = STATE_IDLE;
1842 break;
1843 }
1844 } while (state != prev_state);
1845
1846 host->state = state;
1847
1848 spin_unlock(&host->lock);
1849 }
1850
atmci_read_data_pio(struct atmel_mci * host)1851 static void atmci_read_data_pio(struct atmel_mci *host)
1852 {
1853 struct scatterlist *sg = host->sg;
1854 void *buf = sg_virt(sg);
1855 unsigned int offset = host->pio_offset;
1856 struct mmc_data *data = host->data;
1857 u32 value;
1858 u32 status;
1859 unsigned int nbytes = 0;
1860
1861 do {
1862 value = atmci_readl(host, ATMCI_RDR);
1863 if (likely(offset + 4 <= sg->length)) {
1864 put_unaligned(value, (u32 *)(buf + offset));
1865
1866 offset += 4;
1867 nbytes += 4;
1868
1869 if (offset == sg->length) {
1870 flush_dcache_page(sg_page(sg));
1871 host->sg = sg = sg_next(sg);
1872 host->sg_len--;
1873 if (!sg || !host->sg_len)
1874 goto done;
1875
1876 offset = 0;
1877 buf = sg_virt(sg);
1878 }
1879 } else {
1880 unsigned int remaining = sg->length - offset;
1881 memcpy(buf + offset, &value, remaining);
1882 nbytes += remaining;
1883
1884 flush_dcache_page(sg_page(sg));
1885 host->sg = sg = sg_next(sg);
1886 host->sg_len--;
1887 if (!sg || !host->sg_len)
1888 goto done;
1889
1890 offset = 4 - remaining;
1891 buf = sg_virt(sg);
1892 memcpy(buf, (u8 *)&value + remaining, offset);
1893 nbytes += offset;
1894 }
1895
1896 status = atmci_readl(host, ATMCI_SR);
1897 if (status & ATMCI_DATA_ERROR_FLAGS) {
1898 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1899 | ATMCI_DATA_ERROR_FLAGS));
1900 host->data_status = status;
1901 data->bytes_xfered += nbytes;
1902 return;
1903 }
1904 } while (status & ATMCI_RXRDY);
1905
1906 host->pio_offset = offset;
1907 data->bytes_xfered += nbytes;
1908
1909 return;
1910
1911 done:
1912 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1913 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1914 data->bytes_xfered += nbytes;
1915 smp_wmb();
1916 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1917 }
1918
atmci_write_data_pio(struct atmel_mci * host)1919 static void atmci_write_data_pio(struct atmel_mci *host)
1920 {
1921 struct scatterlist *sg = host->sg;
1922 void *buf = sg_virt(sg);
1923 unsigned int offset = host->pio_offset;
1924 struct mmc_data *data = host->data;
1925 u32 value;
1926 u32 status;
1927 unsigned int nbytes = 0;
1928
1929 do {
1930 if (likely(offset + 4 <= sg->length)) {
1931 value = get_unaligned((u32 *)(buf + offset));
1932 atmci_writel(host, ATMCI_TDR, value);
1933
1934 offset += 4;
1935 nbytes += 4;
1936 if (offset == sg->length) {
1937 host->sg = sg = sg_next(sg);
1938 host->sg_len--;
1939 if (!sg || !host->sg_len)
1940 goto done;
1941
1942 offset = 0;
1943 buf = sg_virt(sg);
1944 }
1945 } else {
1946 unsigned int remaining = sg->length - offset;
1947
1948 value = 0;
1949 memcpy(&value, buf + offset, remaining);
1950 nbytes += remaining;
1951
1952 host->sg = sg = sg_next(sg);
1953 host->sg_len--;
1954 if (!sg || !host->sg_len) {
1955 atmci_writel(host, ATMCI_TDR, value);
1956 goto done;
1957 }
1958
1959 offset = 4 - remaining;
1960 buf = sg_virt(sg);
1961 memcpy((u8 *)&value + remaining, buf, offset);
1962 atmci_writel(host, ATMCI_TDR, value);
1963 nbytes += offset;
1964 }
1965
1966 status = atmci_readl(host, ATMCI_SR);
1967 if (status & ATMCI_DATA_ERROR_FLAGS) {
1968 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1969 | ATMCI_DATA_ERROR_FLAGS));
1970 host->data_status = status;
1971 data->bytes_xfered += nbytes;
1972 return;
1973 }
1974 } while (status & ATMCI_TXRDY);
1975
1976 host->pio_offset = offset;
1977 data->bytes_xfered += nbytes;
1978
1979 return;
1980
1981 done:
1982 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1983 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1984 data->bytes_xfered += nbytes;
1985 smp_wmb();
1986 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1987 }
1988
atmci_sdio_interrupt(struct atmel_mci * host,u32 status)1989 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1990 {
1991 int i;
1992
1993 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1994 struct atmel_mci_slot *slot = host->slot[i];
1995 if (slot && (status & slot->sdio_irq)) {
1996 mmc_signal_sdio_irq(slot->mmc);
1997 }
1998 }
1999 }
2000
2001
atmci_interrupt(int irq,void * dev_id)2002 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2003 {
2004 struct atmel_mci *host = dev_id;
2005 u32 status, mask, pending;
2006 unsigned int pass_count = 0;
2007
2008 do {
2009 status = atmci_readl(host, ATMCI_SR);
2010 mask = atmci_readl(host, ATMCI_IMR);
2011 pending = status & mask;
2012 if (!pending)
2013 break;
2014
2015 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2016 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2017 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2018 | ATMCI_RXRDY | ATMCI_TXRDY
2019 | ATMCI_ENDRX | ATMCI_ENDTX
2020 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2021
2022 host->data_status = status;
2023 dev_dbg(&host->pdev->dev, "set pending data error\n");
2024 smp_wmb();
2025 atmci_set_pending(host, EVENT_DATA_ERROR);
2026 tasklet_schedule(&host->tasklet);
2027 }
2028
2029 if (pending & ATMCI_TXBUFE) {
2030 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2031 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2032 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2033 /*
2034 * We can receive this interruption before having configured
2035 * the second pdc buffer, so we need to reconfigure first and
2036 * second buffers again
2037 */
2038 if (host->data_size) {
2039 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2040 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2041 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2042 } else {
2043 atmci_pdc_complete(host);
2044 }
2045 } else if (pending & ATMCI_ENDTX) {
2046 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2047 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2048
2049 if (host->data_size) {
2050 atmci_pdc_set_single_buf(host,
2051 XFER_TRANSMIT, PDC_SECOND_BUF);
2052 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2053 }
2054 }
2055
2056 if (pending & ATMCI_RXBUFF) {
2057 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2058 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2059 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2060 /*
2061 * We can receive this interruption before having configured
2062 * the second pdc buffer, so we need to reconfigure first and
2063 * second buffers again
2064 */
2065 if (host->data_size) {
2066 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2067 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2068 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2069 } else {
2070 atmci_pdc_complete(host);
2071 }
2072 } else if (pending & ATMCI_ENDRX) {
2073 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2074 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2075
2076 if (host->data_size) {
2077 atmci_pdc_set_single_buf(host,
2078 XFER_RECEIVE, PDC_SECOND_BUF);
2079 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2080 }
2081 }
2082
2083 /*
2084 * First mci IPs, so mainly the ones having pdc, have some
2085 * issues with the notbusy signal. You can't get it after
2086 * data transmission if you have not sent a stop command.
2087 * The appropriate workaround is to use the BLKE signal.
2088 */
2089 if (pending & ATMCI_BLKE) {
2090 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2091 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2092 smp_wmb();
2093 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2094 atmci_set_pending(host, EVENT_NOTBUSY);
2095 tasklet_schedule(&host->tasklet);
2096 }
2097
2098 if (pending & ATMCI_NOTBUSY) {
2099 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2100 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2101 smp_wmb();
2102 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2103 atmci_set_pending(host, EVENT_NOTBUSY);
2104 tasklet_schedule(&host->tasklet);
2105 }
2106
2107 if (pending & ATMCI_RXRDY)
2108 atmci_read_data_pio(host);
2109 if (pending & ATMCI_TXRDY)
2110 atmci_write_data_pio(host);
2111
2112 if (pending & ATMCI_CMDRDY) {
2113 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2114 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2115 host->cmd_status = status;
2116 smp_wmb();
2117 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2118 atmci_set_pending(host, EVENT_CMD_RDY);
2119 tasklet_schedule(&host->tasklet);
2120 }
2121
2122 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2123 atmci_sdio_interrupt(host, status);
2124
2125 } while (pass_count++ < 5);
2126
2127 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2128 }
2129
atmci_detect_interrupt(int irq,void * dev_id)2130 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2131 {
2132 struct atmel_mci_slot *slot = dev_id;
2133
2134 /*
2135 * Disable interrupts until the pin has stabilized and check
2136 * the state then. Use mod_timer() since we may be in the
2137 * middle of the timer routine when this interrupt triggers.
2138 */
2139 disable_irq_nosync(irq);
2140 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2141
2142 return IRQ_HANDLED;
2143 }
2144
atmci_init_slot(struct atmel_mci * host,struct mci_slot_pdata * slot_data,unsigned int id,u32 sdc_reg,u32 sdio_irq)2145 static int __init atmci_init_slot(struct atmel_mci *host,
2146 struct mci_slot_pdata *slot_data, unsigned int id,
2147 u32 sdc_reg, u32 sdio_irq)
2148 {
2149 struct mmc_host *mmc;
2150 struct atmel_mci_slot *slot;
2151
2152 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2153 if (!mmc)
2154 return -ENOMEM;
2155
2156 slot = mmc_priv(mmc);
2157 slot->mmc = mmc;
2158 slot->host = host;
2159 slot->detect_pin = slot_data->detect_pin;
2160 slot->wp_pin = slot_data->wp_pin;
2161 slot->detect_is_active_high = slot_data->detect_is_active_high;
2162 slot->sdc_reg = sdc_reg;
2163 slot->sdio_irq = sdio_irq;
2164
2165 dev_dbg(&mmc->class_dev,
2166 "slot[%u]: bus_width=%u, detect_pin=%d, "
2167 "detect_is_active_high=%s, wp_pin=%d\n",
2168 id, slot_data->bus_width, slot_data->detect_pin,
2169 slot_data->detect_is_active_high ? "true" : "false",
2170 slot_data->wp_pin);
2171
2172 mmc->ops = &atmci_ops;
2173 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2174 mmc->f_max = host->bus_hz / 2;
2175 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2176 if (sdio_irq)
2177 mmc->caps |= MMC_CAP_SDIO_IRQ;
2178 if (host->caps.has_highspeed)
2179 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2180 /*
2181 * Without the read/write proof capability, it is strongly suggested to
2182 * use only one bit for data to prevent fifo underruns and overruns
2183 * which will corrupt data.
2184 */
2185 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2186 mmc->caps |= MMC_CAP_4_BIT_DATA;
2187
2188 if (atmci_get_version(host) < 0x200) {
2189 mmc->max_segs = 256;
2190 mmc->max_blk_size = 4095;
2191 mmc->max_blk_count = 256;
2192 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2193 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2194 } else {
2195 mmc->max_segs = 64;
2196 mmc->max_req_size = 32768 * 512;
2197 mmc->max_blk_size = 32768;
2198 mmc->max_blk_count = 512;
2199 }
2200
2201 /* Assume card is present initially */
2202 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2203 if (gpio_is_valid(slot->detect_pin)) {
2204 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2205 "mmc_detect")) {
2206 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2207 slot->detect_pin = -EBUSY;
2208 } else if (gpio_get_value(slot->detect_pin) ^
2209 slot->detect_is_active_high) {
2210 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2211 }
2212 }
2213
2214 if (!gpio_is_valid(slot->detect_pin))
2215 mmc->caps |= MMC_CAP_NEEDS_POLL;
2216
2217 if (gpio_is_valid(slot->wp_pin)) {
2218 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2219 "mmc_wp")) {
2220 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2221 slot->wp_pin = -EBUSY;
2222 }
2223 }
2224
2225 host->slot[id] = slot;
2226 mmc_regulator_get_supply(mmc);
2227 mmc_add_host(mmc);
2228
2229 if (gpio_is_valid(slot->detect_pin)) {
2230 int ret;
2231
2232 setup_timer(&slot->detect_timer, atmci_detect_change,
2233 (unsigned long)slot);
2234
2235 ret = request_irq(gpio_to_irq(slot->detect_pin),
2236 atmci_detect_interrupt,
2237 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2238 "mmc-detect", slot);
2239 if (ret) {
2240 dev_dbg(&mmc->class_dev,
2241 "could not request IRQ %d for detect pin\n",
2242 gpio_to_irq(slot->detect_pin));
2243 slot->detect_pin = -EBUSY;
2244 }
2245 }
2246
2247 atmci_init_debugfs(slot);
2248
2249 return 0;
2250 }
2251
atmci_cleanup_slot(struct atmel_mci_slot * slot,unsigned int id)2252 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2253 unsigned int id)
2254 {
2255 /* Debugfs stuff is cleaned up by mmc core */
2256
2257 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2258 smp_wmb();
2259
2260 mmc_remove_host(slot->mmc);
2261
2262 if (gpio_is_valid(slot->detect_pin)) {
2263 int pin = slot->detect_pin;
2264
2265 free_irq(gpio_to_irq(pin), slot);
2266 del_timer_sync(&slot->detect_timer);
2267 }
2268
2269 slot->host->slot[id] = NULL;
2270 mmc_free_host(slot->mmc);
2271 }
2272
atmci_filter(struct dma_chan * chan,void * pdata)2273 static bool atmci_filter(struct dma_chan *chan, void *pdata)
2274 {
2275 struct mci_platform_data *sl_pdata = pdata;
2276 struct mci_dma_data *sl;
2277
2278 if (!sl_pdata)
2279 return false;
2280
2281 sl = sl_pdata->dma_slave;
2282 if (sl && find_slave_dev(sl) == chan->device->dev) {
2283 chan->private = slave_data_ptr(sl);
2284 return true;
2285 } else {
2286 return false;
2287 }
2288 }
2289
atmci_configure_dma(struct atmel_mci * host)2290 static bool atmci_configure_dma(struct atmel_mci *host)
2291 {
2292 struct mci_platform_data *pdata;
2293 dma_cap_mask_t mask;
2294
2295 if (host == NULL)
2296 return false;
2297
2298 pdata = host->pdev->dev.platform_data;
2299
2300 dma_cap_zero(mask);
2301 dma_cap_set(DMA_SLAVE, mask);
2302
2303 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2304 &host->pdev->dev, "rxtx");
2305 if (!host->dma.chan) {
2306 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2307 return false;
2308 } else {
2309 dev_info(&host->pdev->dev,
2310 "using %s for DMA transfers\n",
2311 dma_chan_name(host->dma.chan));
2312
2313 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2314 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2315 host->dma_conf.src_maxburst = 1;
2316 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2317 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2318 host->dma_conf.dst_maxburst = 1;
2319 host->dma_conf.device_fc = false;
2320 return true;
2321 }
2322 }
2323
2324 /*
2325 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2326 * HSMCI provides DMA support and a new config register but no more supports
2327 * PDC.
2328 */
atmci_get_cap(struct atmel_mci * host)2329 static void __init atmci_get_cap(struct atmel_mci *host)
2330 {
2331 unsigned int version;
2332
2333 version = atmci_get_version(host);
2334 dev_info(&host->pdev->dev,
2335 "version: 0x%x\n", version);
2336
2337 host->caps.has_dma_conf_reg = 0;
2338 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2339 host->caps.has_cfg_reg = 0;
2340 host->caps.has_cstor_reg = 0;
2341 host->caps.has_highspeed = 0;
2342 host->caps.has_rwproof = 0;
2343 host->caps.has_odd_clk_div = 0;
2344 host->caps.has_bad_data_ordering = 1;
2345 host->caps.need_reset_after_xfer = 1;
2346 host->caps.need_blksz_mul_4 = 1;
2347 host->caps.need_notbusy_for_read_ops = 0;
2348
2349 /* keep only major version number */
2350 switch (version & 0xf00) {
2351 case 0x600:
2352 case 0x500:
2353 host->caps.has_odd_clk_div = 1;
2354 case 0x400:
2355 case 0x300:
2356 host->caps.has_dma_conf_reg = 1;
2357 host->caps.has_pdc = 0;
2358 host->caps.has_cfg_reg = 1;
2359 host->caps.has_cstor_reg = 1;
2360 host->caps.has_highspeed = 1;
2361 case 0x200:
2362 host->caps.has_rwproof = 1;
2363 host->caps.need_blksz_mul_4 = 0;
2364 host->caps.need_notbusy_for_read_ops = 1;
2365 case 0x100:
2366 host->caps.has_bad_data_ordering = 0;
2367 host->caps.need_reset_after_xfer = 0;
2368 case 0x0:
2369 break;
2370 default:
2371 host->caps.has_pdc = 0;
2372 dev_warn(&host->pdev->dev,
2373 "Unmanaged mci version, set minimum capabilities\n");
2374 break;
2375 }
2376 }
2377
atmci_probe(struct platform_device * pdev)2378 static int __init atmci_probe(struct platform_device *pdev)
2379 {
2380 struct mci_platform_data *pdata;
2381 struct atmel_mci *host;
2382 struct resource *regs;
2383 unsigned int nr_slots;
2384 int irq;
2385 int ret, i;
2386
2387 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2388 if (!regs)
2389 return -ENXIO;
2390 pdata = pdev->dev.platform_data;
2391 if (!pdata) {
2392 pdata = atmci_of_init(pdev);
2393 if (IS_ERR(pdata)) {
2394 dev_err(&pdev->dev, "platform data not available\n");
2395 return PTR_ERR(pdata);
2396 }
2397 }
2398
2399 irq = platform_get_irq(pdev, 0);
2400 if (irq < 0)
2401 return irq;
2402
2403 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2404 if (!host)
2405 return -ENOMEM;
2406
2407 host->pdev = pdev;
2408 spin_lock_init(&host->lock);
2409 INIT_LIST_HEAD(&host->queue);
2410
2411 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2412 if (IS_ERR(host->mck))
2413 return PTR_ERR(host->mck);
2414
2415 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2416 if (!host->regs)
2417 return -ENOMEM;
2418
2419 ret = clk_prepare_enable(host->mck);
2420 if (ret)
2421 return ret;
2422
2423 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2424 host->bus_hz = clk_get_rate(host->mck);
2425 clk_disable_unprepare(host->mck);
2426
2427 host->mapbase = regs->start;
2428
2429 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2430
2431 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2432 if (ret)
2433 return ret;
2434
2435 /* Get MCI capabilities and set operations according to it */
2436 atmci_get_cap(host);
2437 if (atmci_configure_dma(host)) {
2438 host->prepare_data = &atmci_prepare_data_dma;
2439 host->submit_data = &atmci_submit_data_dma;
2440 host->stop_transfer = &atmci_stop_transfer_dma;
2441 } else if (host->caps.has_pdc) {
2442 dev_info(&pdev->dev, "using PDC\n");
2443 host->prepare_data = &atmci_prepare_data_pdc;
2444 host->submit_data = &atmci_submit_data_pdc;
2445 host->stop_transfer = &atmci_stop_transfer_pdc;
2446 } else {
2447 dev_info(&pdev->dev, "using PIO\n");
2448 host->prepare_data = &atmci_prepare_data;
2449 host->submit_data = &atmci_submit_data;
2450 host->stop_transfer = &atmci_stop_transfer;
2451 }
2452
2453 platform_set_drvdata(pdev, host);
2454
2455 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2456
2457 /* We need at least one slot to succeed */
2458 nr_slots = 0;
2459 ret = -ENODEV;
2460 if (pdata->slot[0].bus_width) {
2461 ret = atmci_init_slot(host, &pdata->slot[0],
2462 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2463 if (!ret) {
2464 nr_slots++;
2465 host->buf_size = host->slot[0]->mmc->max_req_size;
2466 }
2467 }
2468 if (pdata->slot[1].bus_width) {
2469 ret = atmci_init_slot(host, &pdata->slot[1],
2470 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2471 if (!ret) {
2472 nr_slots++;
2473 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2474 host->buf_size =
2475 host->slot[1]->mmc->max_req_size;
2476 }
2477 }
2478
2479 if (!nr_slots) {
2480 dev_err(&pdev->dev, "init failed: no slot defined\n");
2481 goto err_init_slot;
2482 }
2483
2484 if (!host->caps.has_rwproof) {
2485 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2486 &host->buf_phys_addr,
2487 GFP_KERNEL);
2488 if (!host->buffer) {
2489 ret = -ENOMEM;
2490 dev_err(&pdev->dev, "buffer allocation failed\n");
2491 goto err_dma_alloc;
2492 }
2493 }
2494
2495 dev_info(&pdev->dev,
2496 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2497 host->mapbase, irq, nr_slots);
2498
2499 return 0;
2500
2501 err_dma_alloc:
2502 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2503 if (host->slot[i])
2504 atmci_cleanup_slot(host->slot[i], i);
2505 }
2506 err_init_slot:
2507 del_timer_sync(&host->timer);
2508 if (host->dma.chan)
2509 dma_release_channel(host->dma.chan);
2510 free_irq(irq, host);
2511 return ret;
2512 }
2513
atmci_remove(struct platform_device * pdev)2514 static int __exit atmci_remove(struct platform_device *pdev)
2515 {
2516 struct atmel_mci *host = platform_get_drvdata(pdev);
2517 unsigned int i;
2518
2519 if (host->buffer)
2520 dma_free_coherent(&pdev->dev, host->buf_size,
2521 host->buffer, host->buf_phys_addr);
2522
2523 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2524 if (host->slot[i])
2525 atmci_cleanup_slot(host->slot[i], i);
2526 }
2527
2528 clk_prepare_enable(host->mck);
2529 atmci_writel(host, ATMCI_IDR, ~0UL);
2530 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2531 atmci_readl(host, ATMCI_SR);
2532 clk_disable_unprepare(host->mck);
2533
2534 del_timer_sync(&host->timer);
2535 if (host->dma.chan)
2536 dma_release_channel(host->dma.chan);
2537
2538 free_irq(platform_get_irq(pdev, 0), host);
2539
2540 return 0;
2541 }
2542
2543 static struct platform_driver atmci_driver = {
2544 .remove = __exit_p(atmci_remove),
2545 .driver = {
2546 .name = "atmel_mci",
2547 .of_match_table = of_match_ptr(atmci_dt_ids),
2548 },
2549 };
2550
atmci_init(void)2551 static int __init atmci_init(void)
2552 {
2553 return platform_driver_probe(&atmci_driver, atmci_probe);
2554 }
2555
atmci_exit(void)2556 static void __exit atmci_exit(void)
2557 {
2558 platform_driver_unregister(&atmci_driver);
2559 }
2560
2561 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2562 module_exit(atmci_exit);
2563
2564 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2565 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2566 MODULE_LICENSE("GPL v2");
2567