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Searched refs:cbar (Results 1 – 3 of 3) sorted by relevance

/drivers/iommu/
Darm-smmu.c399 u32 cbar; member
616 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_tlb_inv_context()
740 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank()
744 reg = cfg->cbar; in arm_smmu_init_context_bank()
914 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()
917 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()
920 cfg->cbar = CBAR_TYPE_S2_TRANS; in arm_smmu_init_domain_context()
1462 if (cfg->cbar == CBAR_TYPE_S2_TRANS) { in arm_smmu_handle_mapping()
/drivers/vme/bridges/
Dvme_tsi148.c2270 u32 cbar, crat, vstat; in tsi148_crcsr_init() local
2292 cbar = ioread32be(bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2293 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; in tsi148_crcsr_init()
2297 if (cbar != vstat) { in tsi148_crcsr_init()
2298 cbar = vstat; in tsi148_crcsr_init()
2300 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2302 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); in tsi148_crcsr_init()
/drivers/pci/hotplug/
Dibmphp.h118 u32 cbar; member