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Searched refs:cfg1 (Results 1 – 12 of 12) sorted by relevance

/drivers/staging/comedi/drivers/
Dni_at_ao.c118 unsigned short cfg1; member
130 devpriv->cfg1 |= ATAO_CFG1_GRP2WR; in atao_select_reg_group()
132 devpriv->cfg1 &= ~ATAO_CFG1_GRP2WR; in atao_select_reg_group()
133 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_select_reg_group()
298 devpriv->cfg1 = 0; in atao_reset()
299 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_reset()
/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c543 u32 cfg1, cfg2; in fimc_src_set_transf() local
547 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_src_set_transf()
548 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
557 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
559 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
564 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
566 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
569 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
572 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
574 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
[all …]
/drivers/media/platform/soc_camera/
Datmel-isi.c336 u32 ctrl, cfg1; in start_dma() local
338 cfg1 = isi_readl(isi, ISI_CFG1); in start_dma()
353 cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; in start_dma()
355 cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR; in start_dma()
360 isi_writel(isi, ISI_CFG1, cfg1); in start_dma()
776 u32 cfg1 = 0; in isi_camera_set_bus_param() local
831 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
833 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
835 cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING; in isi_camera_set_bus_param()
838 cfg1 |= ISI_CFG1_EMB_SYNC; in isi_camera_set_bus_param()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
Darb.c206 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb() local
226 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb()
227 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); in nv04_update_arb()
/drivers/video/fbdev/nvidia/
Dnv_hw.c387 unsigned int MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
397 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
626 unsigned int MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
637 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
/drivers/net/ethernet/agere/
Det131x.c818 &macregs->cfg1); in et1310_config_mac_regs1()
860 writel(0, &macregs->cfg1); in et1310_config_mac_regs1()
868 u32 cfg1; in et1310_config_mac_regs2() local
874 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
888 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | in et1310_config_mac_regs2()
891 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); in et1310_config_mac_regs2()
893 cfg1 |= ET_MAC_CFG1_RX_FLOW; in et1310_config_mac_regs2()
894 writel(cfg1, &mac->cfg1); in et1310_config_mac_regs2()
920 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
921 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); in et1310_config_mac_regs2()
[all …]
Det131x.h1048 u32 cfg1; /* 0x5000 */ member
/drivers/video/fbdev/riva/
Driva_hw.c808 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
822 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
824 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1087 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
1089 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
/drivers/scsi/
Dqla1280.c2218 uint16_t hwrev, cfg1, cdma_conf, ddma_conf; in qla1280_nvram_config() local
2222 cfg1 = RD_REG_WORD(&reg->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2228 cfg1 |= nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config()
2230 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config()
2231 WRT_REG_WORD(&reg->cfg_1, cfg1); in qla1280_nvram_config()
2236 uint16_t cfg1, term; in qla1280_nvram_config() local
2239 cfg1 = nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config()
2240 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config()
2243 cfg1 |= BIT_13; in qla1280_nvram_config()
2244 WRT_REG_WORD(&reg->cfg_1, cfg1); in qla1280_nvram_config()
/drivers/net/ethernet/smsc/
Dsmc91x.c911 int bmcr, cfg1; in smc_phy_fixed() local
916 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); in smc_phy_fixed()
917 cfg1 |= PHY_CFG1_LNKDIS; in smc_phy_fixed()
918 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); in smc_phy_fixed()
/drivers/gpu/drm/nouveau/core/subdev/fb/
Dramnve0.c1492 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); in nve0_ram_ctor() local
1493 if (tmp && tmp != cfg1) { in nve0_ram_ctor()
1497 tmp = cfg1; in nve0_ram_ctor()
/drivers/net/ethernet/realtek/
Dr8169.c6369 u8 cfg1; in rtl_hw_start_8102e_1() local
6381 cfg1 = RTL_R8(Config1); in rtl_hw_start_8102e_1()
6382 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) in rtl_hw_start_8102e_1()
6383 RTL_W8(Config1, cfg1 & ~LEDS0); in rtl_hw_start_8102e_1()