1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/gpio.h>
26
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/bios/rammap.h>
31 #include <subdev/bios/timing.h>
32 #include <subdev/bios/M0205.h>
33 #include <subdev/bios/M0209.h>
34
35 #include <subdev/clock.h>
36 #include <subdev/clock/pll.h>
37
38 #include <subdev/timer.h>
39
40 #include <core/option.h>
41
42 #include "nvc0.h"
43
44 #include "ramfuc.h"
45
46 struct nve0_ramfuc {
47 struct ramfuc base;
48
49 struct nvbios_pll refpll;
50 struct nvbios_pll mempll;
51
52 struct ramfuc_reg r_gpioMV;
53 u32 r_funcMV[2];
54 struct ramfuc_reg r_gpio2E;
55 u32 r_func2E[2];
56 struct ramfuc_reg r_gpiotrig;
57
58 struct ramfuc_reg r_0x132020;
59 struct ramfuc_reg r_0x132028;
60 struct ramfuc_reg r_0x132024;
61 struct ramfuc_reg r_0x132030;
62 struct ramfuc_reg r_0x132034;
63 struct ramfuc_reg r_0x132000;
64 struct ramfuc_reg r_0x132004;
65 struct ramfuc_reg r_0x132040;
66
67 struct ramfuc_reg r_0x10f248;
68 struct ramfuc_reg r_0x10f290;
69 struct ramfuc_reg r_0x10f294;
70 struct ramfuc_reg r_0x10f298;
71 struct ramfuc_reg r_0x10f29c;
72 struct ramfuc_reg r_0x10f2a0;
73 struct ramfuc_reg r_0x10f2a4;
74 struct ramfuc_reg r_0x10f2a8;
75 struct ramfuc_reg r_0x10f2ac;
76 struct ramfuc_reg r_0x10f2cc;
77 struct ramfuc_reg r_0x10f2e8;
78 struct ramfuc_reg r_0x10f250;
79 struct ramfuc_reg r_0x10f24c;
80 struct ramfuc_reg r_0x10fec4;
81 struct ramfuc_reg r_0x10fec8;
82 struct ramfuc_reg r_0x10f604;
83 struct ramfuc_reg r_0x10f614;
84 struct ramfuc_reg r_0x10f610;
85 struct ramfuc_reg r_0x100770;
86 struct ramfuc_reg r_0x100778;
87 struct ramfuc_reg r_0x10f224;
88
89 struct ramfuc_reg r_0x10f870;
90 struct ramfuc_reg r_0x10f698;
91 struct ramfuc_reg r_0x10f694;
92 struct ramfuc_reg r_0x10f6b8;
93 struct ramfuc_reg r_0x10f808;
94 struct ramfuc_reg r_0x10f670;
95 struct ramfuc_reg r_0x10f60c;
96 struct ramfuc_reg r_0x10f830;
97 struct ramfuc_reg r_0x1373ec;
98 struct ramfuc_reg r_0x10f800;
99 struct ramfuc_reg r_0x10f82c;
100
101 struct ramfuc_reg r_0x10f978;
102 struct ramfuc_reg r_0x10f910;
103 struct ramfuc_reg r_0x10f914;
104
105 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
106
107 struct ramfuc_reg r_0x62c000;
108
109 struct ramfuc_reg r_0x10f200;
110
111 struct ramfuc_reg r_0x10f210;
112 struct ramfuc_reg r_0x10f310;
113 struct ramfuc_reg r_0x10f314;
114 struct ramfuc_reg r_0x10f318;
115 struct ramfuc_reg r_0x10f090;
116 struct ramfuc_reg r_0x10f69c;
117 struct ramfuc_reg r_0x10f824;
118 struct ramfuc_reg r_0x1373f0;
119 struct ramfuc_reg r_0x1373f4;
120 struct ramfuc_reg r_0x137320;
121 struct ramfuc_reg r_0x10f65c;
122 struct ramfuc_reg r_0x10f6bc;
123 struct ramfuc_reg r_0x100710;
124 struct ramfuc_reg r_0x100750;
125 };
126
127 struct nve0_ram {
128 struct nouveau_ram base;
129 struct nve0_ramfuc fuc;
130
131 struct list_head cfg;
132 u32 parts;
133 u32 pmask;
134 u32 pnuts;
135
136 struct nvbios_ramcfg diff;
137 int from;
138 int mode;
139 int N1, fN1, M1, P1;
140 int N2, M2, P2;
141 };
142
143 /*******************************************************************************
144 * GDDR5
145 ******************************************************************************/
146 static void
nve0_ram_train(struct nve0_ramfuc * fuc,u32 mask,u32 data)147 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
148 {
149 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
150 u32 addr = 0x110974, i;
151
152 ram_mask(fuc, 0x10f910, mask, data);
153 ram_mask(fuc, 0x10f914, mask, data);
154
155 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
156 if (ram->pmask & (1 << i))
157 continue;
158 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
159 }
160 }
161
162 static void
r1373f4_init(struct nve0_ramfuc * fuc)163 r1373f4_init(struct nve0_ramfuc *fuc)
164 {
165 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
166 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
167 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
168 const u32 runk0 = ram->fN1 << 16;
169 const u32 runk1 = ram->fN1;
170
171 if (ram->from == 2) {
172 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
173 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
174 } else {
175 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
176 }
177
178 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
179 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
180
181 /* (re)program refpll, if required */
182 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
183 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
184 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
185 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
186 ram_wr32(fuc, 0x137320, 0x00000000);
187 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
188 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
189 ram_wr32(fuc, 0x132024, rcoef);
190 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
191 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
192 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
193 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
194 }
195
196 /* (re)program mempll, if required */
197 if (ram->mode == 2) {
198 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
199 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
200 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
201 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
202 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
203 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
204 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
205 } else {
206 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
207 }
208
209 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
210 }
211
212 static void
r1373f4_fini(struct nve0_ramfuc * fuc)213 r1373f4_fini(struct nve0_ramfuc *fuc)
214 {
215 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
216 struct nouveau_ram_data *next = ram->base.next;
217 u8 v0 = next->bios.ramcfg_11_03_c0;
218 u8 v1 = next->bios.ramcfg_11_03_30;
219 u32 tmp;
220
221 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
222 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
223 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
224 if (ram->mode == 2) {
225 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
226 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
227 } else {
228 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
229 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
230 }
231 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
232 }
233
234 static void
nve0_ram_nuts(struct nve0_ram * ram,struct ramfuc_reg * reg,u32 _mask,u32 _data,u32 _copy)235 nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
236 u32 _mask, u32 _data, u32 _copy)
237 {
238 struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
239 struct ramfuc *fuc = &ram->fuc.base;
240 u32 addr = 0x110000 + (reg->addr & 0xfff);
241 u32 mask = _mask | _copy;
242 u32 data = (_data & _mask) | (reg->data & _copy);
243 u32 i;
244
245 for (i = 0; i < 16; i++, addr += 0x1000) {
246 if (ram->pnuts & (1 << i)) {
247 u32 prev = nv_rd32(priv, addr);
248 u32 next = (prev & ~mask) | data;
249 nouveau_memx_wr32(fuc->memx, addr, next);
250 }
251 }
252 }
253 #define ram_nuts(s,r,m,d,c) \
254 nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
255
256 static int
nve0_ram_calc_gddr5(struct nouveau_fb * pfb,u32 freq)257 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
258 {
259 struct nve0_ram *ram = (void *)pfb->ram;
260 struct nve0_ramfuc *fuc = &ram->fuc;
261 struct nouveau_ram_data *next = ram->base.next;
262 int vc = !next->bios.ramcfg_11_02_08;
263 int mv = !next->bios.ramcfg_11_02_04;
264 u32 mask, data;
265
266 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
267 ram_block(fuc);
268 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
269
270 /* MR1: turn termination on early, for some reason.. */
271 if ((ram->base.mr[1] & 0x03c) != 0x030) {
272 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
273 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
274 }
275
276 if (vc == 1 && ram_have(fuc, gpio2E)) {
277 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
278 if (temp != ram_rd32(fuc, gpio2E)) {
279 ram_wr32(fuc, gpiotrig, 1);
280 ram_nsec(fuc, 20000);
281 }
282 }
283
284 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
285
286 nve0_ram_train(fuc, 0x01020000, 0x000c0000);
287
288 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
289 ram_nsec(fuc, 1000);
290 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
291 ram_nsec(fuc, 1000);
292
293 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
294 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
295 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
296 ram_wr32(fuc, 0x10f090, 0x00000061);
297 ram_wr32(fuc, 0x10f090, 0xc000007f);
298 ram_nsec(fuc, 1000);
299
300 ram_wr32(fuc, 0x10f698, 0x00000000);
301 ram_wr32(fuc, 0x10f69c, 0x00000000);
302
303 /*XXX: there does appear to be some kind of condition here, simply
304 * modifying these bits in the vbios from the default pl0
305 * entries shows no change. however, the data does appear to
306 * be correct and may be required for the transition back
307 */
308 mask = 0x800f07e0;
309 data = 0x00030000;
310 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
311 data |= 0x00040000;
312
313 if (1) {
314 data |= 0x800807e0;
315 switch (next->bios.ramcfg_11_03_c0) {
316 case 3: data &= ~0x00000040; break;
317 case 2: data &= ~0x00000100; break;
318 case 1: data &= ~0x80000000; break;
319 case 0: data &= ~0x00000400; break;
320 }
321
322 switch (next->bios.ramcfg_11_03_30) {
323 case 3: data &= ~0x00000020; break;
324 case 2: data &= ~0x00000080; break;
325 case 1: data &= ~0x00080000; break;
326 case 0: data &= ~0x00000200; break;
327 }
328 }
329
330 if (next->bios.ramcfg_11_02_80)
331 mask |= 0x03000000;
332 if (next->bios.ramcfg_11_02_40)
333 mask |= 0x00002000;
334 if (next->bios.ramcfg_11_07_10)
335 mask |= 0x00004000;
336 if (next->bios.ramcfg_11_07_08)
337 mask |= 0x00000003;
338 else {
339 mask |= 0x34000000;
340 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
341 mask |= 0x40000000;
342 }
343 ram_mask(fuc, 0x10f824, mask, data);
344
345 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
346
347 if (ram->from == 2 && ram->mode != 2) {
348 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
349 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
350 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
351 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
352 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
353 r1373f4_init(fuc);
354 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
355 r1373f4_fini(fuc);
356 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
357 } else
358 if (ram->from != 2 && ram->mode != 2) {
359 r1373f4_init(fuc);
360 r1373f4_fini(fuc);
361 }
362
363 if (ram_have(fuc, gpioMV)) {
364 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
365 if (temp != ram_rd32(fuc, gpioMV)) {
366 ram_wr32(fuc, gpiotrig, 1);
367 ram_nsec(fuc, 64000);
368 }
369 }
370
371 if (next->bios.ramcfg_11_02_40 ||
372 next->bios.ramcfg_11_07_10) {
373 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
374 ram_nsec(fuc, 20000);
375 }
376
377 if (ram->from != 2 && ram->mode == 2) {
378 if (0 /*XXX: Titan */)
379 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
380 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
381 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
382 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
383 r1373f4_init(fuc);
384 r1373f4_fini(fuc);
385 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
386 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
387 } else
388 if (ram->from == 2 && ram->mode == 2) {
389 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
390 r1373f4_init(fuc);
391 r1373f4_fini(fuc);
392 }
393
394 if (ram->mode != 2) /*XXX*/ {
395 if (next->bios.ramcfg_11_07_40)
396 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
397 }
398
399 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
400 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
401 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
402
403 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
404 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
405 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
406 } else
407 if (!next->bios.ramcfg_11_07_08) {
408 ram_wr32(fuc, 0x10f698, 0x00000000);
409 ram_wr32(fuc, 0x10f69c, 0x00000000);
410 }
411
412 if (ram->mode != 2) {
413 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
414 ram_nuke(fuc, 0x10f694);
415 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
416 }
417
418 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
419 data = 0x00000080;
420 else
421 data = 0x00000000;
422 ram_mask(fuc, 0x10f60c, 0x00000080, data);
423
424 mask = 0x00070000;
425 data = 0x00000000;
426 if (!next->bios.ramcfg_11_02_80)
427 data |= 0x03000000;
428 if (!next->bios.ramcfg_11_02_40)
429 data |= 0x00002000;
430 if (!next->bios.ramcfg_11_07_10)
431 data |= 0x00004000;
432 if (!next->bios.ramcfg_11_07_08)
433 data |= 0x00000003;
434 else
435 data |= 0x74000000;
436 ram_mask(fuc, 0x10f824, mask, data);
437
438 if (next->bios.ramcfg_11_01_08)
439 data = 0x00000000;
440 else
441 data = 0x00001000;
442 ram_mask(fuc, 0x10f200, 0x00001000, data);
443
444 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
445 ram_nsec(fuc, 10000);
446 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
447 }
448
449 if (next->bios.ramcfg_11_08_01)
450 data = 0x00100000;
451 else
452 data = 0x00000000;
453 ram_mask(fuc, 0x10f82c, 0x00100000, data);
454
455 data = 0x00000000;
456 if (next->bios.ramcfg_11_08_08)
457 data |= 0x00002000;
458 if (next->bios.ramcfg_11_08_04)
459 data |= 0x00001000;
460 if (next->bios.ramcfg_11_08_02)
461 data |= 0x00004000;
462 ram_mask(fuc, 0x10f830, 0x00007000, data);
463
464 /* PFB timing */
465 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
466 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
467 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
468 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
469 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
470 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
471 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
472 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
473 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
474 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
475 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
476
477 data = mask = 0x00000000;
478 if (ram->diff.ramcfg_11_08_20) {
479 if (next->bios.ramcfg_11_08_20)
480 data |= 0x01000000;
481 mask |= 0x01000000;
482 }
483 ram_mask(fuc, 0x10f200, mask, data);
484
485 data = mask = 0x00000000;
486 if (ram->diff.ramcfg_11_02_03) {
487 data |= next->bios.ramcfg_11_02_03 << 8;
488 mask |= 0x00000300;
489 }
490 if (ram->diff.ramcfg_11_01_10) {
491 if (next->bios.ramcfg_11_01_10)
492 data |= 0x70000000;
493 mask |= 0x70000000;
494 }
495 ram_mask(fuc, 0x10f604, mask, data);
496
497 data = mask = 0x00000000;
498 if (ram->diff.timing_20_30_07) {
499 data |= next->bios.timing_20_30_07 << 28;
500 mask |= 0x70000000;
501 }
502 if (ram->diff.ramcfg_11_01_01) {
503 if (next->bios.ramcfg_11_01_01)
504 data |= 0x00000100;
505 mask |= 0x00000100;
506 }
507 ram_mask(fuc, 0x10f614, mask, data);
508
509 data = mask = 0x00000000;
510 if (ram->diff.timing_20_30_07) {
511 data |= next->bios.timing_20_30_07 << 28;
512 mask |= 0x70000000;
513 }
514 if (ram->diff.ramcfg_11_01_02) {
515 if (next->bios.ramcfg_11_01_02)
516 data |= 0x00000100;
517 mask |= 0x00000100;
518 }
519 ram_mask(fuc, 0x10f610, mask, data);
520
521 mask = 0x33f00000;
522 data = 0x00000000;
523 if (!next->bios.ramcfg_11_01_04)
524 data |= 0x20200000;
525 if (!next->bios.ramcfg_11_07_80)
526 data |= 0x12800000;
527 /*XXX: see note above about there probably being some condition
528 * for the 10f824 stuff that uses ramcfg 3...
529 */
530 if (next->bios.ramcfg_11_03_f0) {
531 if (next->bios.rammap_11_08_0c) {
532 if (!next->bios.ramcfg_11_07_80)
533 mask |= 0x00000020;
534 else
535 data |= 0x00000020;
536 mask |= 0x00000004;
537 }
538 } else {
539 mask |= 0x40000020;
540 data |= 0x00000004;
541 }
542
543 ram_mask(fuc, 0x10f808, mask, data);
544
545 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
546
547 data = mask = 0x00000000;
548 if (ram->diff.ramcfg_11_02_03) {
549 data |= next->bios.ramcfg_11_02_03;
550 mask |= 0x00000003;
551 }
552 if (ram->diff.ramcfg_11_01_10) {
553 if (next->bios.ramcfg_11_01_10)
554 data |= 0x00000004;
555 mask |= 0x00000004;
556 }
557
558 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
559 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
560 ram_wr32(fuc, 0x100710, 0x00000000);
561 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
562 }
563
564 data = next->bios.timing_20_30_07 << 8;
565 if (next->bios.ramcfg_11_01_01)
566 data |= 0x80000000;
567 ram_mask(fuc, 0x100778, 0x00000700, data);
568
569 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
570 data = (next->bios.timing[10] & 0x7f000000) >> 24;
571 if (data < next->bios.timing_20_2c_1fc0)
572 data = next->bios.timing_20_2c_1fc0;
573 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
574 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
575
576 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
577 next->bios.timing_20_31_0780 << 17 |
578 next->bios.timing_20_31_0078 << 8 |
579 next->bios.timing_20_31_0007);
580 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
581 next->bios.timing_20_31_7000);
582
583 ram_wr32(fuc, 0x10f090, 0x4000007e);
584 ram_nsec(fuc, 2000);
585 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
586 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
587 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
588
589 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
590 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
591 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
592 ram_nsec(fuc, 1000);
593 ram_wr32(fuc, 0x10f294, temp);
594 }
595
596 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
597 ram_wr32(fuc, mr[0], ram->base.mr[0]);
598 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
599 ram_nsec(fuc, 1000);
600 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
601 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
602 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
603 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
604
605 if (vc == 0 && ram_have(fuc, gpio2E)) {
606 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
607 if (temp != ram_rd32(fuc, gpio2E)) {
608 ram_wr32(fuc, gpiotrig, 1);
609 ram_nsec(fuc, 20000);
610 }
611 }
612
613 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
614 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
615 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
616 ram_nsec(fuc, 1000);
617 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
618
619 data = ram_rd32(fuc, 0x10f978);
620 data &= ~0x00046144;
621 data |= 0x0000000b;
622 if (!next->bios.ramcfg_11_07_08) {
623 if (!next->bios.ramcfg_11_07_04)
624 data |= 0x0000200c;
625 else
626 data |= 0x00000000;
627 } else {
628 data |= 0x00040044;
629 }
630 ram_wr32(fuc, 0x10f978, data);
631
632 if (ram->mode == 1) {
633 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
634 ram_wr32(fuc, 0x10f830, data);
635 }
636
637 if (!next->bios.ramcfg_11_07_08) {
638 data = 0x88020000;
639 if ( next->bios.ramcfg_11_07_04)
640 data |= 0x10000000;
641 if (!next->bios.rammap_11_08_10)
642 data |= 0x00080000;
643 } else {
644 data = 0xa40e0000;
645 }
646 nve0_ram_train(fuc, 0xbc0f0000, data);
647 if (1) /* XXX: not always? */
648 ram_nsec(fuc, 1000);
649
650 if (ram->mode == 2) { /*XXX*/
651 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
652 }
653
654 /* LP3 */
655 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
656 ram_nsec(fuc, 1000);
657
658 if (ram->mode != 2) {
659 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
660 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
661 }
662
663 if (next->bios.ramcfg_11_07_02)
664 nve0_ram_train(fuc, 0x80020000, 0x01000000);
665
666 ram_unblock(fuc);
667 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
668
669 if (next->bios.rammap_11_08_01)
670 data = 0x00000800;
671 else
672 data = 0x00000000;
673 ram_mask(fuc, 0x10f200, 0x00000800, data);
674 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
675 return 0;
676 }
677
678 /*******************************************************************************
679 * DDR3
680 ******************************************************************************/
681
682 static int
nve0_ram_calc_sddr3(struct nouveau_fb * pfb,u32 freq)683 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
684 {
685 struct nve0_ram *ram = (void *)pfb->ram;
686 struct nve0_ramfuc *fuc = &ram->fuc;
687 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
688 const u32 runk0 = ram->fN1 << 16;
689 const u32 runk1 = ram->fN1;
690 struct nouveau_ram_data *next = ram->base.next;
691 int vc = !next->bios.ramcfg_11_02_08;
692 int mv = !next->bios.ramcfg_11_02_04;
693 u32 mask, data;
694
695 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
696 ram_block(fuc);
697 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
698
699 if (vc == 1 && ram_have(fuc, gpio2E)) {
700 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
701 if (temp != ram_rd32(fuc, gpio2E)) {
702 ram_wr32(fuc, gpiotrig, 1);
703 ram_nsec(fuc, 20000);
704 }
705 }
706
707 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
708 if (next->bios.ramcfg_11_03_f0)
709 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
710
711 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
712 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
713 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
714 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
715 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
716 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
717 ram_nsec(fuc, 1000);
718
719 ram_wr32(fuc, 0x10f090, 0x00000060);
720 ram_wr32(fuc, 0x10f090, 0xc000007e);
721
722 /*XXX: there does appear to be some kind of condition here, simply
723 * modifying these bits in the vbios from the default pl0
724 * entries shows no change. however, the data does appear to
725 * be correct and may be required for the transition back
726 */
727 mask = 0x00010000;
728 data = 0x00010000;
729
730 if (1) {
731 mask |= 0x800807e0;
732 data |= 0x800807e0;
733 switch (next->bios.ramcfg_11_03_c0) {
734 case 3: data &= ~0x00000040; break;
735 case 2: data &= ~0x00000100; break;
736 case 1: data &= ~0x80000000; break;
737 case 0: data &= ~0x00000400; break;
738 }
739
740 switch (next->bios.ramcfg_11_03_30) {
741 case 3: data &= ~0x00000020; break;
742 case 2: data &= ~0x00000080; break;
743 case 1: data &= ~0x00080000; break;
744 case 0: data &= ~0x00000200; break;
745 }
746 }
747
748 if (next->bios.ramcfg_11_02_80)
749 mask |= 0x03000000;
750 if (next->bios.ramcfg_11_02_40)
751 mask |= 0x00002000;
752 if (next->bios.ramcfg_11_07_10)
753 mask |= 0x00004000;
754 if (next->bios.ramcfg_11_07_08)
755 mask |= 0x00000003;
756 else
757 mask |= 0x14000000;
758 ram_mask(fuc, 0x10f824, mask, data);
759
760 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
761
762 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
763 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
764 data |= next->bios.ramcfg_11_03_30 << 16;
765 ram_wr32(fuc, 0x1373ec, data);
766 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
767 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
768
769 /* (re)program refpll, if required */
770 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
771 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
772 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
773 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
774 ram_wr32(fuc, 0x137320, 0x00000000);
775 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
776 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
777 ram_wr32(fuc, 0x132024, rcoef);
778 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
779 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
780 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
781 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
782 }
783
784 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
785 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
786 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
787
788 if (ram_have(fuc, gpioMV)) {
789 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
790 if (temp != ram_rd32(fuc, gpioMV)) {
791 ram_wr32(fuc, gpiotrig, 1);
792 ram_nsec(fuc, 64000);
793 }
794 }
795
796 if (next->bios.ramcfg_11_02_40 ||
797 next->bios.ramcfg_11_07_10) {
798 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
799 ram_nsec(fuc, 20000);
800 }
801
802 if (ram->mode != 2) /*XXX*/ {
803 if (next->bios.ramcfg_11_07_40)
804 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
805 }
806
807 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
808 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
809 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
810
811 mask = 0x00010000;
812 data = 0x00000000;
813 if (!next->bios.ramcfg_11_02_80)
814 data |= 0x03000000;
815 if (!next->bios.ramcfg_11_02_40)
816 data |= 0x00002000;
817 if (!next->bios.ramcfg_11_07_10)
818 data |= 0x00004000;
819 if (!next->bios.ramcfg_11_07_08)
820 data |= 0x00000003;
821 else
822 data |= 0x14000000;
823 ram_mask(fuc, 0x10f824, mask, data);
824 ram_nsec(fuc, 1000);
825
826 if (next->bios.ramcfg_11_08_01)
827 data = 0x00100000;
828 else
829 data = 0x00000000;
830 ram_mask(fuc, 0x10f82c, 0x00100000, data);
831
832 /* PFB timing */
833 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
834 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
835 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
836 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
837 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
838 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
839 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
840 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
841 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
842 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
843 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
844
845 mask = 0x33f00000;
846 data = 0x00000000;
847 if (!next->bios.ramcfg_11_01_04)
848 data |= 0x20200000;
849 if (!next->bios.ramcfg_11_07_80)
850 data |= 0x12800000;
851 /*XXX: see note above about there probably being some condition
852 * for the 10f824 stuff that uses ramcfg 3...
853 */
854 if (next->bios.ramcfg_11_03_f0) {
855 if (next->bios.rammap_11_08_0c) {
856 if (!next->bios.ramcfg_11_07_80)
857 mask |= 0x00000020;
858 else
859 data |= 0x00000020;
860 mask |= 0x08000004;
861 }
862 data |= 0x04000000;
863 } else {
864 mask |= 0x44000020;
865 data |= 0x08000004;
866 }
867
868 ram_mask(fuc, 0x10f808, mask, data);
869
870 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
871
872 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
873
874 data = (next->bios.timing[10] & 0x7f000000) >> 24;
875 if (data < next->bios.timing_20_2c_1fc0)
876 data = next->bios.timing_20_2c_1fc0;
877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
878
879 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
880
881 ram_wr32(fuc, 0x10f090, 0x4000007f);
882 ram_nsec(fuc, 1000);
883
884 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
885 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
886 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
887 ram_nsec(fuc, 1000);
888
889 ram_nuke(fuc, mr[0]);
890 ram_mask(fuc, mr[0], 0x100, 0x100);
891 ram_mask(fuc, mr[0], 0x100, 0x000);
892
893 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
894 ram_wr32(fuc, mr[0], ram->base.mr[0]);
895 ram_nsec(fuc, 1000);
896
897 ram_nuke(fuc, mr[0]);
898 ram_mask(fuc, mr[0], 0x100, 0x100);
899 ram_mask(fuc, mr[0], 0x100, 0x000);
900
901 if (vc == 0 && ram_have(fuc, gpio2E)) {
902 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
903 if (temp != ram_rd32(fuc, gpio2E)) {
904 ram_wr32(fuc, gpiotrig, 1);
905 ram_nsec(fuc, 20000);
906 }
907 }
908
909 if (ram->mode != 2) {
910 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
911 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
912 }
913
914 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
915 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
916 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
917 ram_nsec(fuc, 1000);
918
919 ram_unblock(fuc);
920 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
921
922 if (next->bios.rammap_11_08_01)
923 data = 0x00000800;
924 else
925 data = 0x00000000;
926 ram_mask(fuc, 0x10f200, 0x00000800, data);
927 return 0;
928 }
929
930 /*******************************************************************************
931 * main hooks
932 ******************************************************************************/
933
934 static int
nve0_ram_calc_data(struct nouveau_fb * pfb,u32 khz,struct nouveau_ram_data * data)935 nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz,
936 struct nouveau_ram_data *data)
937 {
938 struct nve0_ram *ram = (void *)pfb->ram;
939 struct nouveau_ram_data *cfg;
940 u32 mhz = khz / 1000;
941
942 list_for_each_entry(cfg, &ram->cfg, head) {
943 if (mhz >= cfg->bios.rammap_min &&
944 mhz <= cfg->bios.rammap_max) {
945 *data = *cfg;
946 data->freq = khz;
947 return 0;
948 }
949 }
950
951 nv_error(ram, "ramcfg data for %dMHz not found\n", mhz);
952 return -EINVAL;
953 }
954
955 static int
nve0_ram_calc_xits(struct nouveau_fb * pfb,struct nouveau_ram_data * next)956 nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
957 {
958 struct nve0_ram *ram = (void *)pfb->ram;
959 struct nve0_ramfuc *fuc = &ram->fuc;
960 int refclk, i;
961 int ret;
962
963 ret = ram_init(fuc, pfb);
964 if (ret)
965 return ret;
966
967 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
968 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
969
970 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
971 * select, based on some unknown condition, one of the two possible
972 * reference frequencies listed in the vbios table for mempll and
973 * program refpll to that frequency.
974 *
975 * so far, i've seen very weird values being chosen by nvidia on
976 * kepler boards, no idea how/why they're chosen.
977 */
978 refclk = next->freq;
979 if (ram->mode == 2)
980 refclk = fuc->mempll.refclk;
981
982 /* calculate refpll coefficients */
983 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
984 &ram->fN1, &ram->M1, &ram->P1);
985 fuc->mempll.refclk = ret;
986 if (ret <= 0) {
987 nv_error(pfb, "unable to calc refpll\n");
988 return -EINVAL;
989 }
990
991 /* calculate mempll coefficients, if we're using it */
992 if (ram->mode == 2) {
993 /* post-divider doesn't work... the reg takes the values but
994 * appears to completely ignore it. there *is* a bit at
995 * bit 28 that appears to divide the clock by 2 if set.
996 */
997 fuc->mempll.min_p = 1;
998 fuc->mempll.max_p = 2;
999
1000 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
1001 &ram->N2, NULL, &ram->M2, &ram->P2);
1002 if (ret <= 0) {
1003 nv_error(pfb, "unable to calc mempll\n");
1004 return -EINVAL;
1005 }
1006 }
1007
1008 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1009 if (ram_have(fuc, mr[i]))
1010 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1011 }
1012 ram->base.freq = next->freq;
1013
1014 switch (ram->base.type) {
1015 case NV_MEM_TYPE_DDR3:
1016 ret = nouveau_sddr3_calc(&ram->base);
1017 if (ret == 0)
1018 ret = nve0_ram_calc_sddr3(pfb, next->freq);
1019 break;
1020 case NV_MEM_TYPE_GDDR5:
1021 ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
1022 if (ret == 0)
1023 ret = nve0_ram_calc_gddr5(pfb, next->freq);
1024 break;
1025 default:
1026 ret = -ENOSYS;
1027 break;
1028 }
1029
1030 return ret;
1031 }
1032
1033 static int
nve0_ram_calc(struct nouveau_fb * pfb,u32 freq)1034 nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
1035 {
1036 struct nouveau_clock *clk = nouveau_clock(pfb);
1037 struct nve0_ram *ram = (void *)pfb->ram;
1038 struct nouveau_ram_data *xits = &ram->base.xition;
1039 struct nouveau_ram_data *copy;
1040 int ret;
1041
1042 if (ram->base.next == NULL) {
1043 ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
1044 &ram->base.former);
1045 if (ret)
1046 return ret;
1047
1048 ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
1049 if (ret)
1050 return ret;
1051
1052 if (ram->base.target.freq < ram->base.former.freq) {
1053 *xits = ram->base.target;
1054 copy = &ram->base.former;
1055 } else {
1056 *xits = ram->base.former;
1057 copy = &ram->base.target;
1058 }
1059
1060 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1061 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1062 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1063
1064 ram->base.next = &ram->base.target;
1065 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1066 ram->base.next = &ram->base.xition;
1067 } else {
1068 BUG_ON(ram->base.next != &ram->base.xition);
1069 ram->base.next = &ram->base.target;
1070 }
1071
1072 return nve0_ram_calc_xits(pfb, ram->base.next);
1073 }
1074
1075 static void
nve0_ram_prog_0(struct nouveau_fb * pfb,u32 freq)1076 nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq)
1077 {
1078 struct nve0_ram *ram = (void *)pfb->ram;
1079 struct nouveau_ram_data *cfg;
1080 u32 mhz = freq / 1000;
1081 u32 mask, data;
1082
1083 list_for_each_entry(cfg, &ram->cfg, head) {
1084 if (mhz >= cfg->bios.rammap_min &&
1085 mhz <= cfg->bios.rammap_max)
1086 break;
1087 }
1088
1089 if (&cfg->head == &ram->cfg)
1090 return;
1091
1092 if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
1093 data |= cfg->bios.rammap_11_0a_03fe << 12;
1094 mask |= 0x001ff000;
1095 }
1096 if (ram->diff.rammap_11_09_01ff) {
1097 data |= cfg->bios.rammap_11_09_01ff;
1098 mask |= 0x000001ff;
1099 }
1100 nv_mask(pfb, 0x10f468, mask, data);
1101
1102 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
1103 data |= cfg->bios.rammap_11_0a_0400;
1104 mask |= 0x00000001;
1105 }
1106 nv_mask(pfb, 0x10f420, mask, data);
1107
1108 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
1109 data |= cfg->bios.rammap_11_0a_0800;
1110 mask |= 0x00000001;
1111 }
1112 nv_mask(pfb, 0x10f430, mask, data);
1113
1114 if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
1115 data |= cfg->bios.rammap_11_0b_01f0;
1116 mask |= 0x0000001f;
1117 }
1118 nv_mask(pfb, 0x10f400, mask, data);
1119
1120 if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
1121 data |= cfg->bios.rammap_11_0b_0200 << 9;
1122 mask |= 0x00000200;
1123 }
1124 nv_mask(pfb, 0x10f410, mask, data);
1125
1126 if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
1127 data |= cfg->bios.rammap_11_0d << 16;
1128 mask |= 0x00ff0000;
1129 }
1130 if (ram->diff.rammap_11_0f) {
1131 data |= cfg->bios.rammap_11_0f << 8;
1132 mask |= 0x0000ff00;
1133 }
1134 nv_mask(pfb, 0x10f440, mask, data);
1135
1136 if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
1137 data |= cfg->bios.rammap_11_0e << 8;
1138 mask |= 0x0000ff00;
1139 }
1140 if (ram->diff.rammap_11_0b_0800) {
1141 data |= cfg->bios.rammap_11_0b_0800 << 7;
1142 mask |= 0x00000080;
1143 }
1144 if (ram->diff.rammap_11_0b_0400) {
1145 data |= cfg->bios.rammap_11_0b_0400 << 5;
1146 mask |= 0x00000020;
1147 }
1148 nv_mask(pfb, 0x10f444, mask, data);
1149 }
1150
1151 static int
nve0_ram_prog(struct nouveau_fb * pfb)1152 nve0_ram_prog(struct nouveau_fb *pfb)
1153 {
1154 struct nouveau_device *device = nv_device(pfb);
1155 struct nve0_ram *ram = (void *)pfb->ram;
1156 struct nve0_ramfuc *fuc = &ram->fuc;
1157 struct nouveau_ram_data *next = ram->base.next;
1158
1159 if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) {
1160 ram_exec(fuc, false);
1161 return (ram->base.next == &ram->base.xition);
1162 }
1163
1164 nve0_ram_prog_0(pfb, 1000);
1165 ram_exec(fuc, true);
1166 nve0_ram_prog_0(pfb, next->freq);
1167
1168 return (ram->base.next == &ram->base.xition);
1169 }
1170
1171 static void
nve0_ram_tidy(struct nouveau_fb * pfb)1172 nve0_ram_tidy(struct nouveau_fb *pfb)
1173 {
1174 struct nve0_ram *ram = (void *)pfb->ram;
1175 struct nve0_ramfuc *fuc = &ram->fuc;
1176 ram->base.next = NULL;
1177 ram_exec(fuc, false);
1178 }
1179
1180 struct nve0_ram_train {
1181 u16 mask;
1182 struct nvbios_M0209S remap;
1183 struct nvbios_M0209S type00;
1184 struct nvbios_M0209S type01;
1185 struct nvbios_M0209S type04;
1186 struct nvbios_M0209S type06;
1187 struct nvbios_M0209S type07;
1188 struct nvbios_M0209S type08;
1189 struct nvbios_M0209S type09;
1190 };
1191
1192 static int
nve0_ram_train_type(struct nouveau_fb * pfb,int i,u8 ramcfg,struct nve0_ram_train * train)1193 nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
1194 struct nve0_ram_train *train)
1195 {
1196 struct nouveau_bios *bios = nouveau_bios(pfb);
1197 struct nvbios_M0205E M0205E;
1198 struct nvbios_M0205S M0205S;
1199 struct nvbios_M0209E M0209E;
1200 struct nvbios_M0209S *remap = &train->remap;
1201 struct nvbios_M0209S *value;
1202 u8 ver, hdr, cnt, len;
1203 u32 data;
1204
1205 /* determine type of data for this index */
1206 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
1207 return -ENOENT;
1208
1209 switch (M0205E.type) {
1210 case 0x00: value = &train->type00; break;
1211 case 0x01: value = &train->type01; break;
1212 case 0x04: value = &train->type04; break;
1213 case 0x06: value = &train->type06; break;
1214 case 0x07: value = &train->type07; break;
1215 case 0x08: value = &train->type08; break;
1216 case 0x09: value = &train->type09; break;
1217 default:
1218 return 0;
1219 }
1220
1221 /* training data index determined by ramcfg strap */
1222 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
1223 return -EINVAL;
1224 i = M0205S.data;
1225
1226 /* training data format information */
1227 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
1228 return -EINVAL;
1229
1230 /* ... and the raw data */
1231 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
1232 return -EINVAL;
1233
1234 if (M0209E.v02_07 == 2) {
1235 /* of course! why wouldn't we have a pointer to another entry
1236 * in the same table, and use the first one as an array of
1237 * remap indices...
1238 */
1239 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
1240 remap)))
1241 return -EINVAL;
1242
1243 for (i = 0; i < ARRAY_SIZE(value->data); i++)
1244 value->data[i] = remap->data[value->data[i]];
1245 } else
1246 if (M0209E.v02_07 != 1)
1247 return -EINVAL;
1248
1249 train->mask |= 1 << M0205E.type;
1250 return 0;
1251 }
1252
1253 static int
nve0_ram_train_init_0(struct nouveau_fb * pfb,struct nve0_ram_train * train)1254 nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
1255 {
1256 int i, j;
1257
1258 if ((train->mask & 0x03d3) != 0x03d3) {
1259 nv_warn(pfb, "missing link training data\n");
1260 return -EINVAL;
1261 }
1262
1263 for (i = 0; i < 0x30; i++) {
1264 for (j = 0; j < 8; j += 4) {
1265 nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
1266 nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
1267 train->type08.data[i] << 4 |
1268 train->type06.data[i]);
1269 nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
1270 nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
1271 train->type09.data[i] << 4 |
1272 train->type07.data[i]);
1273 nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
1274 }
1275 }
1276
1277 for (j = 0; j < 8; j += 4) {
1278 for (i = 0; i < 0x100; i++) {
1279 nv_wr32(pfb, 0x10f968 + j, i);
1280 nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
1281 }
1282 }
1283
1284 return 0;
1285 }
1286
1287 static int
nve0_ram_train_init(struct nouveau_fb * pfb)1288 nve0_ram_train_init(struct nouveau_fb *pfb)
1289 {
1290 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
1291 struct nve0_ram_train *train;
1292 int ret = -ENOMEM, i;
1293
1294 if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
1295 for (i = 0; i < 0x100; i++) {
1296 ret = nve0_ram_train_type(pfb, i, ramcfg, train);
1297 if (ret && ret != -ENOENT)
1298 break;
1299 }
1300 }
1301
1302 switch (pfb->ram->type) {
1303 case NV_MEM_TYPE_GDDR5:
1304 ret = nve0_ram_train_init_0(pfb, train);
1305 break;
1306 default:
1307 ret = 0;
1308 break;
1309 }
1310
1311 kfree(train);
1312 return ret;
1313 }
1314
1315 int
nve0_ram_init(struct nouveau_object * object)1316 nve0_ram_init(struct nouveau_object *object)
1317 {
1318 struct nouveau_fb *pfb = (void *)object->parent;
1319 struct nve0_ram *ram = (void *)object;
1320 struct nouveau_bios *bios = nouveau_bios(pfb);
1321 u8 ver, hdr, cnt, len, snr, ssz;
1322 u32 data, save;
1323 int ret, i;
1324
1325 ret = nouveau_ram_init(&ram->base);
1326 if (ret)
1327 return ret;
1328
1329 /* run a bunch of tables from rammap table. there's actually
1330 * individual pointers for each rammap entry too, but, nvidia
1331 * seem to just run the last two entries' scripts early on in
1332 * their init, and never again.. we'll just run 'em all once
1333 * for now.
1334 *
1335 * i strongly suspect that each script is for a separate mode
1336 * (likely selected by 0x10f65c's lower bits?), and the
1337 * binary driver skips the one that's already been setup by
1338 * the init tables.
1339 */
1340 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1341 if (!data || hdr < 0x15)
1342 return -EINVAL;
1343
1344 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1345 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1346 save = nv_rd32(pfb, 0x10f65c) & 0x000000f0;
1347 for (i = 0; i < cnt; i++, data += 4) {
1348 if (i != save >> 4) {
1349 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1350 nvbios_exec(&(struct nvbios_init) {
1351 .subdev = nv_subdev(pfb),
1352 .bios = bios,
1353 .offset = nv_ro32(bios, data),
1354 .execute = 1,
1355 });
1356 }
1357 }
1358 nv_mask(pfb, 0x10f65c, 0x000000f0, save);
1359 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
1360 nv_wr32(pfb, 0x10ecc0, 0xffffffff);
1361 nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
1362
1363 return nve0_ram_train_init(pfb);
1364 }
1365
1366 static int
nve0_ram_ctor_data(struct nve0_ram * ram,u8 ramcfg,int i)1367 nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i)
1368 {
1369 struct nouveau_fb *pfb = (void *)nv_object(ram)->parent;
1370 struct nouveau_bios *bios = nouveau_bios(pfb);
1371 struct nouveau_ram_data *cfg;
1372 struct nvbios_ramcfg *d = &ram->diff;
1373 struct nvbios_ramcfg *p, *n;
1374 u8 ver, hdr, cnt, len;
1375 u32 data;
1376 int ret;
1377
1378 if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
1379 return -ENOMEM;
1380 p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
1381 n = &cfg->bios;
1382
1383 /* memory config data for a range of target frequencies */
1384 data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
1385 if (ret = -ENOENT, !data)
1386 goto done;
1387 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
1388 goto done;
1389
1390 /* ... and a portion specific to the attached memory */
1391 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
1392 &ver, &hdr, &cfg->bios);
1393 if (ret = -EINVAL, !data)
1394 goto done;
1395 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
1396 goto done;
1397
1398 /* lookup memory timings, if bios says they're present */
1399 if (cfg->bios.ramcfg_timing != 0xff) {
1400 data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
1401 &ver, &hdr, &cnt, &len,
1402 &cfg->bios);
1403 if (ret = -EINVAL, !data)
1404 goto done;
1405 if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
1406 goto done;
1407 }
1408
1409 list_add_tail(&cfg->head, &ram->cfg);
1410 if (ret = 0, i == 0)
1411 goto done;
1412
1413 d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
1414 d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
1415 d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
1416 d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
1417 d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
1418 d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
1419 d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
1420 d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
1421 d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
1422 d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
1423 d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
1424 d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
1425 d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
1426 d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
1427 d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
1428 d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
1429 d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
1430 done:
1431 if (ret)
1432 kfree(cfg);
1433 return ret;
1434 }
1435
1436 static void
nve0_ram_dtor(struct nouveau_object * object)1437 nve0_ram_dtor(struct nouveau_object *object)
1438 {
1439 struct nve0_ram *ram = (void *)object;
1440 struct nouveau_ram_data *cfg, *tmp;
1441
1442 list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
1443 kfree(cfg);
1444 }
1445
1446 nouveau_ram_destroy(&ram->base);
1447 }
1448
1449 static int
nve0_ram_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)1450 nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1451 struct nouveau_oclass *oclass, void *data, u32 size,
1452 struct nouveau_object **pobject)
1453 {
1454 struct nouveau_fb *pfb = nouveau_fb(parent);
1455 struct nouveau_bios *bios = nouveau_bios(pfb);
1456 struct nouveau_gpio *gpio = nouveau_gpio(pfb);
1457 struct dcb_gpio_func func;
1458 struct nve0_ram *ram;
1459 int ret, i;
1460 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
1461 u32 tmp;
1462
1463 ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
1464 *pobject = nv_object(ram);
1465 if (ret)
1466 return ret;
1467
1468 INIT_LIST_HEAD(&ram->cfg);
1469
1470 switch (ram->base.type) {
1471 case NV_MEM_TYPE_DDR3:
1472 case NV_MEM_TYPE_GDDR5:
1473 ram->base.calc = nve0_ram_calc;
1474 ram->base.prog = nve0_ram_prog;
1475 ram->base.tidy = nve0_ram_tidy;
1476 break;
1477 default:
1478 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1479 break;
1480 }
1481
1482 /* calculate a mask of differently configured memory partitions,
1483 * because, of course reclocking wasn't complicated enough
1484 * already without having to treat some of them differently to
1485 * the others....
1486 */
1487 ram->parts = nv_rd32(pfb, 0x022438);
1488 ram->pmask = nv_rd32(pfb, 0x022554);
1489 ram->pnuts = 0;
1490 for (i = 0, tmp = 0; i < ram->parts; i++) {
1491 if (!(ram->pmask & (1 << i))) {
1492 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1493 if (tmp && tmp != cfg1) {
1494 ram->pnuts |= (1 << i);
1495 continue;
1496 }
1497 tmp = cfg1;
1498 }
1499 }
1500
1501 /* parse bios data for all rammap table entries up-front, and
1502 * build information on whether certain fields differ between
1503 * any of the entries.
1504 *
1505 * the binary driver appears to completely ignore some fields
1506 * when all entries contain the same value. at first, it was
1507 * hoped that these were mere optimisations and the bios init
1508 * tables had configured as per the values here, but there is
1509 * evidence now to suggest that this isn't the case and we do
1510 * need to treat this condition as a "don't touch" indicator.
1511 */
1512 for (i = 0; !ret; i++) {
1513 ret = nve0_ram_ctor_data(ram, ramcfg, i);
1514 if (ret && ret != -ENOENT) {
1515 nv_error(pfb, "failed to parse ramcfg data\n");
1516 return ret;
1517 }
1518 }
1519
1520 /* parse bios data for both pll's */
1521 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1522 if (ret) {
1523 nv_error(pfb, "mclk refpll data not found\n");
1524 return ret;
1525 }
1526
1527 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1528 if (ret) {
1529 nv_error(pfb, "mclk pll data not found\n");
1530 return ret;
1531 }
1532
1533 /* lookup memory voltage gpios */
1534 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1535 if (ret == 0) {
1536 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1537 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1538 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1539 }
1540
1541 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1542 if (ret == 0) {
1543 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1544 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1545 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1546 }
1547
1548 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1549
1550 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1551 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1552 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1553 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1554 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1555 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1556 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1557 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1558
1559 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1560 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1561 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1562 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1563 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1564 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1565 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1566 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1567 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1568 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1569 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1570 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1571 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1572 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1573 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1574 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1575 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1576 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1577 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1578 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1579 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1580
1581 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1582 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1583 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1584 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1585 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1586 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1587 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1588 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1589 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1590 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1591 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1592
1593 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1594 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1595 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1596
1597 switch (ram->base.type) {
1598 case NV_MEM_TYPE_GDDR5:
1599 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1600 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1601 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1602 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1603 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1604 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1605 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1606 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1607 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1608 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1609 break;
1610 case NV_MEM_TYPE_DDR3:
1611 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1612 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1613 break;
1614 default:
1615 break;
1616 }
1617
1618 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1619 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1620 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1621 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1622 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1623 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1624 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1625 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1626 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1627 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1628 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1629 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1630 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1631 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1632 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1633 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1634 return 0;
1635 }
1636
1637 struct nouveau_oclass
1638 nve0_ram_oclass = {
1639 .handle = 0,
1640 .ofuncs = &(struct nouveau_ofuncs) {
1641 .ctor = nve0_ram_ctor,
1642 .dtor = nve0_ram_dtor,
1643 .init = nve0_ram_init,
1644 .fini = _nouveau_ram_fini,
1645 }
1646 };
1647