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Searched refs:cpu_base (Results 1 – 7 of 7) sorted by relevance

/drivers/irqchip/
Dirq-gic.c58 union gic_base cpu_base; member
120 return data->get_base(&data->cpu_base); in gic_data_cpu_base()
130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
266 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq() local
269 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in gic_handle_irq()
277 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq()
365 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); in gic_cpu_if_up() local
371 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
374 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
431 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); in gic_cpu_if_down() local
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Dirq-hip04.c57 void __iomem *cpu_base; member
83 return hip04_data->cpu_base; in hip04_cpu_base()
172 void __iomem *cpu_base = hip04_data.cpu_base; in hip04_handle_irq() local
175 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in hip04_handle_irq()
184 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in hip04_handle_irq()
248 void __iomem *base = intc->cpu_base; in hip04_irq_cpu_init()
377 hip04_data.cpu_base = of_iomap(node, 1); in hip04_of_init()
378 WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n"); in hip04_of_init()
/drivers/net/ethernet/broadcom/
Dbgmac.c158 dma_desc = ring->cpu_base; in bgmac_dma_tx_add()
314 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; in bgmac_dma_rx_setup_desc()
457 if (ring->cpu_base) { in bgmac_dma_ring_free()
460 dma_free_coherent(dma_dev, size, ring->cpu_base, in bgmac_dma_ring_free()
500 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, in bgmac_dma_alloc()
503 if (!ring->cpu_base) { in bgmac_dma_alloc()
530 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, in bgmac_dma_alloc()
533 if (!ring->cpu_base) { in bgmac_dma_alloc()
Dbgmac.h417 struct bgmac_dma_desc *cpu_base; member
Dtg3.c3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3591 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu()
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); in tg3_pause_cpu()
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3623 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_resume_cpu()
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000); in tg3_resume_cpu()
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3646 if (cpu_base == RX_CPU_BASE) { in tg3_halt_cpu()
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/drivers/block/
DDAC960.c230 loaf->cpu_free = loaf->cpu_base = cpu_addr; in init_dma_loaf()
243 BUG_ON(cpu_end > loaf->cpu_base + loaf->length); in slice_dma_loaf()
252 if (loaf_handle->cpu_base != NULL) in free_dma_loaf()
254 loaf_handle->cpu_base, loaf_handle->dma_base); in free_dma_loaf()
DDAC960.h112 void *cpu_base; member