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Searched refs:enable_mask (Results 1 – 25 of 88) sorted by relevance

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/drivers/clk/qcom/
Dgcc-ipq806x.c53 .enable_mask = BIT(0),
96 .enable_mask = BIT(8),
123 .enable_mask = BIT(14),
227 .enable_mask = BIT(11),
243 .enable_mask = BIT(9),
278 .enable_mask = BIT(11),
294 .enable_mask = BIT(9),
329 .enable_mask = BIT(11),
345 .enable_mask = BIT(9),
380 .enable_mask = BIT(11),
[all …]
Dgcc-msm8660.c53 .enable_mask = BIT(8),
128 .enable_mask = BIT(11),
144 .enable_mask = BIT(9),
179 .enable_mask = BIT(11),
195 .enable_mask = BIT(9),
230 .enable_mask = BIT(11),
246 .enable_mask = BIT(9),
281 .enable_mask = BIT(11),
297 .enable_mask = BIT(9),
332 .enable_mask = BIT(11),
[all …]
Dgcc-msm8960.c69 .enable_mask = BIT(8),
96 .enable_mask = BIT(14),
184 .enable_mask = BIT(11),
200 .enable_mask = BIT(9),
235 .enable_mask = BIT(11),
251 .enable_mask = BIT(9),
286 .enable_mask = BIT(11),
302 .enable_mask = BIT(9),
337 .enable_mask = BIT(11),
353 .enable_mask = BIT(9),
[all …]
Dmmcc-apq8084.c239 .enable_mask = BIT(0),
266 .enable_mask = BIT(1),
1125 .enable_mask = BIT(0),
1140 .enable_mask = BIT(0),
1157 .enable_mask = BIT(0),
1174 .enable_mask = BIT(0),
1191 .enable_mask = BIT(0),
1208 .enable_mask = BIT(0),
1225 .enable_mask = BIT(0),
1242 .enable_mask = BIT(0),
[all …]
Dmmcc-msm8960.c168 .enable_mask = BIT(2),
183 .enable_mask = BIT(0),
217 .enable_mask = BIT(2),
232 .enable_mask = BIT(0),
266 .enable_mask = BIT(2),
281 .enable_mask = BIT(0),
321 .enable_mask = BIT(2),
336 .enable_mask = BIT(0),
352 .enable_mask = BIT(8),
385 .enable_mask = BIT(2),
[all …]
Dmmcc-msm8974.c204 .enable_mask = BIT(0),
231 .enable_mask = BIT(1),
952 .enable_mask = BIT(0),
968 .enable_mask = BIT(0),
985 .enable_mask = BIT(0),
1001 .enable_mask = BIT(0),
1018 .enable_mask = BIT(0),
1035 .enable_mask = BIT(0),
1052 .enable_mask = BIT(0),
1069 .enable_mask = BIT(0),
[all …]
Dgcc-apq8084.c126 .enable_mask = BIT(0),
189 .enable_mask = BIT(1),
216 .enable_mask = BIT(4),
288 .enable_mask = BIT(0),
305 .enable_mask = BIT(0),
1331 .enable_mask = BIT(0),
1385 .enable_mask = BIT(12),
1402 .enable_mask = BIT(17),
1418 .enable_mask = BIT(0),
1435 .enable_mask = BIT(0),
[all …]
Dgcc-msm8974.c82 .enable_mask = BIT(0),
145 .enable_mask = BIT(1),
172 .enable_mask = BIT(4),
1047 .enable_mask = BIT(26),
1063 .enable_mask = BIT(12),
1080 .enable_mask = BIT(17),
1096 .enable_mask = BIT(0),
1113 .enable_mask = BIT(0),
1130 .enable_mask = BIT(0),
1147 .enable_mask = BIT(0),
[all …]
Dclk-regmap.c41 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
43 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
64 val = rclk->enable_mask; in clk_enable_regmap()
67 rclk->enable_mask, val); in clk_enable_regmap()
86 val = rclk->enable_mask; in clk_disable_regmap()
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask, in clk_disable_regmap()
/drivers/regulator/
Dlp8788-ldo.c203 .enable_mask = LP8788_EN_DLDO1_M,
216 .enable_mask = LP8788_EN_DLDO2_M,
229 .enable_mask = LP8788_EN_DLDO3_M,
242 .enable_mask = LP8788_EN_DLDO4_M,
255 .enable_mask = LP8788_EN_DLDO5_M,
268 .enable_mask = LP8788_EN_DLDO6_M,
281 .enable_mask = LP8788_EN_DLDO7_M,
294 .enable_mask = LP8788_EN_DLDO8_M,
307 .enable_mask = LP8788_EN_DLDO9_M,
320 .enable_mask = LP8788_EN_DLDO10_M,
[all …]
Drk808-regulator.c134 .enable_mask = BIT(0),
148 .enable_mask = BIT(1),
158 .enable_mask = BIT(2),
172 .enable_mask = BIT(3),
186 .enable_mask = BIT(0),
201 .enable_mask = BIT(1),
216 .enable_mask = BIT(2),
231 .enable_mask = BIT(3),
246 .enable_mask = BIT(4),
261 .enable_mask = BIT(5),
[all …]
Das3722-regulator.c68 u8 enable_mask; member
97 .enable_mask = AS3722_SDn_CTRL(0),
109 .enable_mask = AS3722_SDn_CTRL(1),
122 .enable_mask = AS3722_SDn_CTRL(2),
136 .enable_mask = AS3722_SDn_CTRL(3),
150 .enable_mask = AS3722_SDn_CTRL(4),
164 .enable_mask = AS3722_SDn_CTRL(5),
177 .enable_mask = AS3722_SDn_CTRL(6),
190 .enable_mask = AS3722_LDO0_CTRL,
202 .enable_mask = AS3722_LDO1_CTRL,
[all …]
Ds2mps11.c270 .enable_mask = S2MPS11_ENABLE_MASK \
286 .enable_mask = S2MPS11_ENABLE_MASK \
302 .enable_mask = S2MPS11_ENABLE_MASK \
318 .enable_mask = S2MPS11_ENABLE_MASK \
334 .enable_mask = S2MPS11_ENABLE_MASK \
400 val = rdev->desc->enable_mask; in s2mps14_regulator_enable()
406 val = rdev->desc->enable_mask; in s2mps14_regulator_enable()
413 rdev->desc->enable_mask, val); in s2mps14_regulator_enable()
464 if (!(val & rdev->desc->enable_mask)) in s2mps14_regulator_set_suspend_disable()
468 rdev->desc->enable_mask, state); in s2mps14_regulator_set_suspend_disable()
[all …]
Dmax77686.c84 rdev->desc->enable_mask, val); in max77686_buck_set_suspend_disable()
118 rdev->desc->enable_mask, val); in max77686_set_suspend_mode()
151 rdev->desc->enable_mask, val); in max77686_ldo_set_suspend_mode()
164 rdev->desc->enable_mask, in max77686_enable()
255 .enable_mask = MAX77686_OPMODE_MASK \
271 .enable_mask = MAX77686_OPMODE_MASK \
287 .enable_mask = MAX77686_OPMODE_MASK \
303 .enable_mask = MAX77686_OPMODE_MASK \
319 .enable_mask = MAX77686_OPMODE_MASK, \
334 .enable_mask = MAX77686_OPMODE_MASK, \
[all …]
Dpbias-regulator.c32 u32 enable_mask; member
63 .enable_mask = BIT(1),
71 .enable_mask = BIT(9),
79 .enable_mask = BIT(26) | BIT(25) | BIT(22),
87 .enable_mask = BIT(27) | BIT(25) | BIT(26),
160 drvdata[data_idx].desc.enable_mask = info->enable_mask; in pbias_regulator_probe()
Daat2870-regulator.c38 u8 enable_mask; member
74 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, in aat2870_ldo_enable()
75 ri->enable_mask); in aat2870_ldo_enable()
83 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, 0); in aat2870_ldo_disable()
97 return val & ri->enable_mask ? 1 : 0; in aat2870_ldo_is_enabled()
153 ri->enable_mask = 0x1 << ri->enable_shift; in aat2870_get_regulator()
Dmax77802.c103 rdev->desc->enable_mask, val << shift); in max77802_buck_set_suspend_disable()
139 rdev->desc->enable_mask, val << shift); in max77802_ldo_set_suspend_mode_logic1()
172 rdev->desc->enable_mask, val << shift); in max77802_ldo_set_suspend_mode_logic2()
182 rdev->desc->enable_mask, in max77802_enable()
311 .enable_mask = MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
329 .enable_mask = MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
347 .enable_mask = MAX77802_OPMODE_MASK, \
365 .enable_mask = MAX77802_OPMODE_MASK << \
384 .enable_mask = MAX77802_OPMODE_MASK, \
402 .enable_mask = MAX77802_OPMODE_MASK, \
Dwm8400-regulator.c128 .enable_mask = WM8400_LDO1_ENA,
142 .enable_mask = WM8400_LDO2_ENA,
156 .enable_mask = WM8400_LDO3_ENA,
170 .enable_mask = WM8400_LDO4_ENA,
184 .enable_mask = WM8400_DC1_ENA_MASK,
198 .enable_mask = WM8400_DC1_ENA_MASK,
Dlp872x.c533 .enable_mask = LP872X_EN_LDO1_M,
546 .enable_mask = LP872X_EN_LDO2_M,
559 .enable_mask = LP872X_EN_LDO3_M,
572 .enable_mask = LP872X_EN_LDO4_M,
585 .enable_mask = LP872X_EN_LDO5_M,
596 .enable_mask = LP8720_EN_BUCK_M,
612 .enable_mask = LP872X_EN_LDO1_M,
625 .enable_mask = LP872X_EN_LDO2_M,
638 .enable_mask = LP872X_EN_LDO3_M,
651 .enable_mask = LP872X_EN_LDO4_M,
[all …]
/drivers/tty/
Dsysrq.c97 .enable_mask = SYSRQ_ENABLE_LOG,
110 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
126 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
144 .enable_mask = SYSRQ_ENABLE_DUMP,
157 .enable_mask = SYSRQ_ENABLE_BOOT,
168 .enable_mask = SYSRQ_ENABLE_SYNC,
190 .enable_mask = SYSRQ_ENABLE_REMOUNT,
256 .enable_mask = SYSRQ_ENABLE_DUMP,
274 .enable_mask = SYSRQ_ENABLE_DUMP,
285 .enable_mask = SYSRQ_ENABLE_DUMP,
[all …]
/drivers/clk/ti/
Dapll.c61 v &= ~ad->enable_mask; in dra7_apll_enable()
62 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); in dra7_apll_enable()
100 v &= ~ad->enable_mask; in dra7_apll_disable()
101 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); in dra7_apll_disable()
114 v &= ad->enable_mask; in dra7_apll_is_enabled()
116 v >>= __ffs(ad->enable_mask); in dra7_apll_is_enabled()
210 ad->enable_mask = 0x3; in of_dra7_apll_setup()
233 v &= ad->enable_mask; in omap2_apll_is_enabled()
235 v >>= __ffs(ad->enable_mask); in omap2_apll_is_enabled()
259 v &= ~ad->enable_mask; in omap2_apll_enable()
[all …]
Ddpll.c340 .enable_mask = 0x7, in of_ti_omap3_dpll_setup()
360 .enable_mask = 0x7, in of_ti_omap3_core_dpll_setup()
379 .enable_mask = 0x7 << 16, in of_ti_omap3_per_dpll_setup()
399 .enable_mask = 0x7 << 16, in of_ti_omap3_per_jtype_dpll_setup()
422 .enable_mask = 0x7, in of_ti_omap4_dpll_setup()
441 .enable_mask = 0x7, in of_ti_omap5_mpu_dpll_setup()
462 .enable_mask = 0x7, in of_ti_omap4_core_dpll_setup()
483 .enable_mask = 0x7, in of_ti_omap4_m4xen_dpll_setup()
504 .enable_mask = 0x7, in of_ti_omap4_jtype_dpll_setup()
526 .enable_mask = 0x7, in of_ti_am3_no_gate_dpll_setup()
[all …]
/drivers/clk/mmp/
Dclk-apmu.c26 u32 enable_mask; member
39 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; in clk_apmu_disable()
70 void __iomem *base, u32 enable_mask, spinlock_t *lock) in mmp_clk_register_apmu() argument
87 apmu->enable_mask = enable_mask; in mmp_clk_register_apmu()
/drivers/clocksource/
Dtime-armada-370-xp.c79 static u32 enable_mask; variable
119 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask); in armada_370_xp_clkevt_next_event()
138 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); in armada_370_xp_clkevt_mode()
237 enable_mask = TIMER0_EN; in armada_370_xp_timer_common_init()
240 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); in armada_370_xp_timer_common_init()
261 TIMER0_RELOAD_EN | enable_mask, in armada_370_xp_timer_common_init()
262 TIMER0_RELOAD_EN | enable_mask); in armada_370_xp_timer_common_init()
/drivers/clk/
Dclk-palmas.c37 unsigned int enable_mask; member
70 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
71 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
95 cinfo->clk_desc->enable_mask, 0); in palmas_clks_unprepare()
117 return !!(val & cinfo->clk_desc->enable_mask); in palmas_clks_is_prepared()
141 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
157 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,

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