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Searched refs:ep0state (Results 1 – 18 of 18) sorted by relevance

/drivers/usb/gadget/udc/
Dbcm63xx_udc.c303 int ep0state; member
961 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_init_udc_hw()
1531 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()
1535 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()
1537 udc->ep0state = bcm63xx_ep0_do_setup(udc); in bcm63xx_ep0_do_idle()
1538 return udc->ep0state == EP0_IDLE ? -EAGAIN : 0; in bcm63xx_ep0_do_idle()
1549 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_ep0_do_idle()
1573 enum bcm63xx_ep0_state ep0state = udc->ep0state; in bcm63xx_ep0_one_round() local
1576 switch (udc->ep0state) { in bcm63xx_ep0_one_round()
1581 ep0state = EP0_IDLE; in bcm63xx_ep0_one_round()
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Dgoku_udc.c250 if (dev->ep0state == EP0_SUSPEND) in goku_ep_disable()
358 if (unlikely(ep->num == 0 && dev->ep0state != EP0_IN)) in write_fifo()
376 dev->ep0state = EP0_STATUS; in write_fifo()
416 if (unlikely(ep->num == 0 && ep->dev->ep0state != EP0_OUT)) in read_fifo()
482 ep->dev->ep0state = EP0_STATUS; in read_fifo()
728 if (dev->ep0state == EP0_SUSPEND) in goku_queue()
821 if (dev->ep0state == EP0_SUSPEND) in goku_dequeue()
889 ep->dev->ep0state = EP0_STALL; in goku_set_halt()
1084 switch(dev->ep0state){ in udc_proc_read()
1232 dev->ep0state = EP0_DISCONNECT; in udc_reinit()
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Ds3c2410_udc.c398 ep->dev->ep0state = EP0_IDLE; in s3c2410_udc_write_fifo()
521 ep->dev->ep0state = EP0_IDLE; in s3c2410_udc_read_fifo()
726 dev->ep0state = EP0_IN_DATA_PHASE; in s3c2410_udc_handle_ep0_idle()
728 dev->ep0state = EP0_OUT_DATA_PHASE; in s3c2410_udc_handle_ep0_idle()
751 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0_idle()
758 dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]); in s3c2410_udc_handle_ep0_idle()
780 ep0csr, ep0states[dev->ep0state]); in s3c2410_udc_handle_ep0()
787 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0()
796 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0()
799 switch (dev->ep0state) { in s3c2410_udc_handle_ep0()
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Ds3c-hsudc.c154 int ep0state; member
255 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_complete_request()
639 hsudc->ep0state = DATA_STATE_XMIT; in s3c_hsudc_process_setup()
642 hsudc->ep0state = DATA_STATE_RECV; in s3c_hsudc_process_setup()
649 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
663 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
674 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
681 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
710 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_handle_ep0_intr()
728 if (hsudc->ep0state == WAIT_FOR_SETUP) in s3c_hsudc_handle_ep0_intr()
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Dpxa25x_udc.h103 enum ep0_state ep0state; member
189 label, state_name[the_controller->ep0state], udccs0, in dump_udccs0()
207 state_name[dev->ep0state], in dump_state()
Dgr_udc.c199 seq_printf(seq, "ep0state = %s\n", gr_ep0state_string(dev->ep0state)); in gr_seq_show()
620 if (dev->ep0state == GR_EP0_SUSPEND) { in gr_queue()
716 dev->ep0state = GR_EP0_STALL; in gr_control_stall()
772 if (dev->ep0state != value) in gr_set_ep0state()
775 dev->ep0state = value; in gr_set_ep0state()
1080 if (dev->ep0state == GR_EP0_STALL) { in gr_ep0_setup()
1086 if (dev->ep0state == GR_EP0_ISTATUS) { in gr_ep0_setup()
1094 } else if (dev->ep0state != GR_EP0_SETUP) { in gr_ep0_setup()
1097 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()
1103 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()
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Dgoku_udc.h232 enum ep0state { enum
248 enum ep0state ep0state; member
Dpxa25x_udc.c357 dev->ep0state = EP0_IDLE; in ep0_idle()
676 switch (dev->ep0state) { in pxa25x_ep_queue()
693 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()
708 DMSG("ep0 i/o, odd state %d\n", dev->ep0state); in pxa25x_ep_queue()
823 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()
1183 dev->ep0state = EP0_IDLE; in udc_reinit()
1390 if (dev->ep0state == EP0_STALL in udc_watchdog()
1425 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { in handle_ep0()
1431 switch (dev->ep0state) { in handle_ep0()
1507 dev->ep0state = EP0_IN_DATA_PHASE; in handle_ep0()
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Dlpc32xx_udc.c195 int ep0state; member
1456 udc->ep0state = WAIT_FOR_SETUP; in udc_reinit()
1535 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_in_req()
1557 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()
1575 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()
1878 udc->ep0state = DATA_IN; in lpc32xx_ep_queue()
1882 udc->ep0state = DATA_OUT; in lpc32xx_ep_queue()
2373 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_setup()
2409 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_in()
2416 if (udc->ep0state == DATA_IN) in udc_handle_ep0_in()
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Ds3c2410_udc.h88 int ep0state; member
Dpxa27x_udc.h398 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
452 enum ep0_state ep0state; member
Dgr_udc.h199 enum gr_ep0state ep0state; member
Dpxa27x_udc.c562 udc->ep0state = state; in set_ep0state()
1194 switch (dev->ep0state) { in pxa_ep_queue()
2026 switch (udc->ep0state) { in handle_ep0()
/drivers/usb/dwc3/
Dep0.c131 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()
155 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()
200 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()
239 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_gadget_ep0_queue()
270 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()
884 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()
897 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()
913 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()
1058 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()
1078 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_ep0_interrupt()
Dcore.h740 enum dwc3_ep0_state ep0state; member
Dgadget.c1643 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_gadget_start()
2865 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_gadget_resume()
/drivers/staging/emxx_udc/
Demxx_udc.c1259 switch (udc->ep0state) { in _nbu2ss_start_transfer()
1730 udc->ep0state = EP0_IN_STATUS_PHASE; in _nbu2ss_decode_request()
1734 udc->ep0state = EP0_IN_DATA_PHASE; in _nbu2ss_decode_request()
1736 udc->ep0state = EP0_OUT_DATA_PHASE; in _nbu2ss_decode_request()
1771 if (udc->ep0state == EP0_IN_STATUS_PHASE) { in _nbu2ss_decode_request()
1786 udc->ep0state = EP0_IDLE; in _nbu2ss_decode_request()
1811 udc->ep0state = EP0_OUT_STATUS_PAHSE; in _nbu2ss_ep0_in_data_stage()
1835 udc->ep0state = EP0_IN_STATUS_PHASE; in _nbu2ss_ep0_out_data_stage()
1867 udc->ep0state = EP0_IDLE; in _nbu2ss_ep0_status_stage()
1897 switch (udc->ep0state) { in _nbu2ss_ep0_int()
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Demxx_udc.h614 enum ep0_state ep0state; member