1 /* linux/drivers/usb/gadget/s3c-hsudc.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S3C24XX USB 2.0 High-speed USB controller gadget driver
7 *
8 * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
9 * Each endpoint can be configured as either in or out endpoint. Endpoints
10 * can be configured for Bulk or Interrupt transfer mode.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/otg.h>
31 #include <linux/prefetch.h>
32 #include <linux/platform_data/s3c-hsudc.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/pm_runtime.h>
35
36 #include <mach/regs-s3c2443-clock.h>
37
38 #define S3C_HSUDC_REG(x) (x)
39
40 /* Non-Indexed Registers */
41 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
42 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
43 #define S3C_EIR_EP0 (1<<0)
44 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
45 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
46 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
47 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
48 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
49 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
50 #define S3C_SSR_DTZIEN_EN (0xff8f)
51 #define S3C_SSR_ERR (0xff80)
52 #define S3C_SSR_VBUSON (1 << 8)
53 #define S3C_SSR_HSP (1 << 4)
54 #define S3C_SSR_SDE (1 << 3)
55 #define S3C_SSR_RESUME (1 << 2)
56 #define S3C_SSR_SUSPEND (1 << 1)
57 #define S3C_SSR_RESET (1 << 0)
58 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
59 #define S3C_SCR_DTZIEN_EN (1 << 14)
60 #define S3C_SCR_RRD_EN (1 << 5)
61 #define S3C_SCR_SUS_EN (1 << 1)
62 #define S3C_SCR_RST_EN (1 << 0)
63 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
64 #define S3C_EP0SR_EP0_LWO (1 << 6)
65 #define S3C_EP0SR_STALL (1 << 4)
66 #define S3C_EP0SR_TX_SUCCESS (1 << 1)
67 #define S3C_EP0SR_RX_SUCCESS (1 << 0)
68 #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
69 #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
70
71 /* Indexed Registers */
72 #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
73 #define S3C_ESR_FLUSH (1 << 6)
74 #define S3C_ESR_STALL (1 << 5)
75 #define S3C_ESR_LWO (1 << 4)
76 #define S3C_ESR_PSIF_ONE (1 << 2)
77 #define S3C_ESR_PSIF_TWO (2 << 2)
78 #define S3C_ESR_TX_SUCCESS (1 << 1)
79 #define S3C_ESR_RX_SUCCESS (1 << 0)
80 #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
81 #define S3C_ECR_DUEN (1 << 7)
82 #define S3C_ECR_FLUSH (1 << 6)
83 #define S3C_ECR_STALL (1 << 1)
84 #define S3C_ECR_IEMS (1 << 0)
85 #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
86 #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
87 #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
88
89 #define WAIT_FOR_SETUP (0)
90 #define DATA_STATE_XMIT (1)
91 #define DATA_STATE_RECV (2)
92
93 static const char * const s3c_hsudc_supply_names[] = {
94 "vdda", /* analog phy supply, 3.3V */
95 "vddi", /* digital phy supply, 1.2V */
96 "vddosc", /* oscillator supply, 1.8V - 3.3V */
97 };
98
99 /**
100 * struct s3c_hsudc_ep - Endpoint representation used by driver.
101 * @ep: USB gadget layer representation of device endpoint.
102 * @name: Endpoint name (as required by ep autoconfiguration).
103 * @dev: Reference to the device controller to which this EP belongs.
104 * @desc: Endpoint descriptor obtained from the gadget driver.
105 * @queue: Transfer request queue for the endpoint.
106 * @stopped: Maintains state of endpoint, set if EP is halted.
107 * @bEndpointAddress: EP address (including direction bit).
108 * @fifo: Base address of EP FIFO.
109 */
110 struct s3c_hsudc_ep {
111 struct usb_ep ep;
112 char name[20];
113 struct s3c_hsudc *dev;
114 struct list_head queue;
115 u8 stopped;
116 u8 wedge;
117 u8 bEndpointAddress;
118 void __iomem *fifo;
119 };
120
121 /**
122 * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
123 * @req: Reference to USB gadget transfer request.
124 * @queue: Used for inserting this request to the endpoint request queue.
125 */
126 struct s3c_hsudc_req {
127 struct usb_request req;
128 struct list_head queue;
129 };
130
131 /**
132 * struct s3c_hsudc - Driver's abstraction of the device controller.
133 * @gadget: Instance of usb_gadget which is referenced by gadget driver.
134 * @driver: Reference to currenty active gadget driver.
135 * @dev: The device reference used by probe function.
136 * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
137 * @regs: Remapped base address of controller's register space.
138 * irq: IRQ number used by the controller.
139 * uclk: Reference to the controller clock.
140 * ep0state: Current state of EP0.
141 * ep: List of endpoints supported by the controller.
142 */
143 struct s3c_hsudc {
144 struct usb_gadget gadget;
145 struct usb_gadget_driver *driver;
146 struct device *dev;
147 struct s3c24xx_hsudc_platdata *pd;
148 struct usb_phy *transceiver;
149 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
150 spinlock_t lock;
151 void __iomem *regs;
152 int irq;
153 struct clk *uclk;
154 int ep0state;
155 struct s3c_hsudc_ep ep[];
156 };
157
158 #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
159 #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
160 #define ep_index(_ep) ((_ep)->bEndpointAddress & \
161 USB_ENDPOINT_NUMBER_MASK)
162
163 static const char driver_name[] = "s3c-udc";
164 static const char ep0name[] = "ep0-control";
165
our_req(struct usb_request * req)166 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
167 {
168 return container_of(req, struct s3c_hsudc_req, req);
169 }
170
our_ep(struct usb_ep * ep)171 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
172 {
173 return container_of(ep, struct s3c_hsudc_ep, ep);
174 }
175
to_hsudc(struct usb_gadget * gadget)176 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
177 {
178 return container_of(gadget, struct s3c_hsudc, gadget);
179 }
180
set_index(struct s3c_hsudc * hsudc,int ep_addr)181 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
182 {
183 ep_addr &= USB_ENDPOINT_NUMBER_MASK;
184 writel(ep_addr, hsudc->regs + S3C_IR);
185 }
186
__orr32(void __iomem * ptr,u32 val)187 static inline void __orr32(void __iomem *ptr, u32 val)
188 {
189 writel(readl(ptr) | val, ptr);
190 }
191
s3c_hsudc_init_phy(void)192 static void s3c_hsudc_init_phy(void)
193 {
194 u32 cfg;
195
196 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
197 writel(cfg, S3C2443_PWRCFG);
198
199 cfg = readl(S3C2443_URSTCON);
200 cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
201 writel(cfg, S3C2443_URSTCON);
202 mdelay(1);
203
204 cfg = readl(S3C2443_URSTCON);
205 cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
206 writel(cfg, S3C2443_URSTCON);
207
208 cfg = readl(S3C2443_PHYCTRL);
209 cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
210 cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
211 writel(cfg, S3C2443_PHYCTRL);
212
213 cfg = readl(S3C2443_PHYPWR);
214 cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
215 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
216 S3C2443_PHYPWR_ANALOG_PD);
217 cfg |= S3C2443_PHYPWR_COMMON_ON;
218 writel(cfg, S3C2443_PHYPWR);
219
220 cfg = readl(S3C2443_UCLKCON);
221 cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
222 S3C2443_UCLKCON_TCLKEN);
223 writel(cfg, S3C2443_UCLKCON);
224 }
225
s3c_hsudc_uninit_phy(void)226 static void s3c_hsudc_uninit_phy(void)
227 {
228 u32 cfg;
229
230 cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
231 writel(cfg, S3C2443_PWRCFG);
232
233 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
234
235 cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
236 writel(cfg, S3C2443_UCLKCON);
237 }
238
239 /**
240 * s3c_hsudc_complete_request - Complete a transfer request.
241 * @hsep: Endpoint to which the request belongs.
242 * @hsreq: Transfer request to be completed.
243 * @status: Transfer completion status for the transfer request.
244 */
s3c_hsudc_complete_request(struct s3c_hsudc_ep * hsep,struct s3c_hsudc_req * hsreq,int status)245 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
246 struct s3c_hsudc_req *hsreq, int status)
247 {
248 unsigned int stopped = hsep->stopped;
249 struct s3c_hsudc *hsudc = hsep->dev;
250
251 list_del_init(&hsreq->queue);
252 hsreq->req.status = status;
253
254 if (!ep_index(hsep)) {
255 hsudc->ep0state = WAIT_FOR_SETUP;
256 hsep->bEndpointAddress &= ~USB_DIR_IN;
257 }
258
259 hsep->stopped = 1;
260 spin_unlock(&hsudc->lock);
261 usb_gadget_giveback_request(&hsep->ep, &hsreq->req);
262 spin_lock(&hsudc->lock);
263 hsep->stopped = stopped;
264 }
265
266 /**
267 * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
268 * @hsep: Endpoint for which queued requests have to be terminated.
269 * @status: Transfer completion status for the transfer request.
270 */
s3c_hsudc_nuke_ep(struct s3c_hsudc_ep * hsep,int status)271 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
272 {
273 struct s3c_hsudc_req *hsreq;
274
275 while (!list_empty(&hsep->queue)) {
276 hsreq = list_entry(hsep->queue.next,
277 struct s3c_hsudc_req, queue);
278 s3c_hsudc_complete_request(hsep, hsreq, status);
279 }
280 }
281
282 /**
283 * s3c_hsudc_stop_activity - Stop activity on all endpoints.
284 * @hsudc: Device controller for which EP activity is to be stopped.
285 *
286 * All the endpoints are stopped and any pending transfer requests if any on
287 * the endpoint are terminated.
288 */
s3c_hsudc_stop_activity(struct s3c_hsudc * hsudc)289 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
290 {
291 struct s3c_hsudc_ep *hsep;
292 int epnum;
293
294 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
295
296 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
297 hsep = &hsudc->ep[epnum];
298 hsep->stopped = 1;
299 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
300 }
301 }
302
303 /**
304 * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
305 * @hsudc: Device controller from which setup packet is to be read.
306 * @buf: The buffer into which the setup packet is read.
307 *
308 * The setup packet received in the EP0 fifo is read and stored into a
309 * given buffer address.
310 */
311
s3c_hsudc_read_setup_pkt(struct s3c_hsudc * hsudc,u16 * buf)312 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
313 {
314 int count;
315
316 count = readl(hsudc->regs + S3C_BRCR);
317 while (count--)
318 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
319
320 writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
321 }
322
323 /**
324 * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
325 * @hsep: Endpoint to which the data is to be written.
326 * @hsreq: Transfer request from which the next chunk of data is written.
327 *
328 * Write the next chunk of data from a transfer request to the endpoint FIFO.
329 * If the transfer request completes, 1 is returned, otherwise 0 is returned.
330 */
s3c_hsudc_write_fifo(struct s3c_hsudc_ep * hsep,struct s3c_hsudc_req * hsreq)331 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
332 struct s3c_hsudc_req *hsreq)
333 {
334 u16 *buf;
335 u32 max = ep_maxpacket(hsep);
336 u32 count, length;
337 bool is_last;
338 void __iomem *fifo = hsep->fifo;
339
340 buf = hsreq->req.buf + hsreq->req.actual;
341 prefetch(buf);
342
343 length = hsreq->req.length - hsreq->req.actual;
344 length = min(length, max);
345 hsreq->req.actual += length;
346
347 writel(length, hsep->dev->regs + S3C_BWCR);
348 for (count = 0; count < length; count += 2)
349 writel(*buf++, fifo);
350
351 if (count != max) {
352 is_last = true;
353 } else {
354 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
355 is_last = false;
356 else
357 is_last = true;
358 }
359
360 if (is_last) {
361 s3c_hsudc_complete_request(hsep, hsreq, 0);
362 return 1;
363 }
364
365 return 0;
366 }
367
368 /**
369 * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
370 * @hsep: Endpoint from which the data is to be read.
371 * @hsreq: Transfer request to which the next chunk of data read is written.
372 *
373 * Read the next chunk of data from the endpoint FIFO and a write it to the
374 * transfer request buffer. If the transfer request completes, 1 is returned,
375 * otherwise 0 is returned.
376 */
s3c_hsudc_read_fifo(struct s3c_hsudc_ep * hsep,struct s3c_hsudc_req * hsreq)377 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
378 struct s3c_hsudc_req *hsreq)
379 {
380 struct s3c_hsudc *hsudc = hsep->dev;
381 u32 csr, offset;
382 u16 *buf, word;
383 u32 buflen, rcnt, rlen;
384 void __iomem *fifo = hsep->fifo;
385 u32 is_short = 0;
386
387 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
388 csr = readl(hsudc->regs + offset);
389 if (!(csr & S3C_ESR_RX_SUCCESS))
390 return -EINVAL;
391
392 buf = hsreq->req.buf + hsreq->req.actual;
393 prefetchw(buf);
394 buflen = hsreq->req.length - hsreq->req.actual;
395
396 rcnt = readl(hsudc->regs + S3C_BRCR);
397 rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
398
399 hsreq->req.actual += min(rlen, buflen);
400 is_short = (rlen < hsep->ep.maxpacket);
401
402 while (rcnt-- != 0) {
403 word = (u16)readl(fifo);
404 if (buflen) {
405 *buf++ = word;
406 buflen--;
407 } else {
408 hsreq->req.status = -EOVERFLOW;
409 }
410 }
411
412 writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
413
414 if (is_short || hsreq->req.actual == hsreq->req.length) {
415 s3c_hsudc_complete_request(hsep, hsreq, 0);
416 return 1;
417 }
418
419 return 0;
420 }
421
422 /**
423 * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
424 * @hsudc - Device controller for which the interrupt is to be handled.
425 * @ep_idx - Endpoint number on which an interrupt is pending.
426 *
427 * Handles interrupt for a in-endpoint. The interrupts that are handled are
428 * stall and data transmit complete interrupt.
429 */
s3c_hsudc_epin_intr(struct s3c_hsudc * hsudc,u32 ep_idx)430 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
431 {
432 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
433 struct s3c_hsudc_req *hsreq;
434 u32 csr;
435
436 csr = readl(hsudc->regs + S3C_ESR);
437 if (csr & S3C_ESR_STALL) {
438 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
439 return;
440 }
441
442 if (csr & S3C_ESR_TX_SUCCESS) {
443 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
444 if (list_empty(&hsep->queue))
445 return;
446
447 hsreq = list_entry(hsep->queue.next,
448 struct s3c_hsudc_req, queue);
449 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
450 (csr & S3C_ESR_PSIF_TWO))
451 s3c_hsudc_write_fifo(hsep, hsreq);
452 }
453 }
454
455 /**
456 * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
457 * @hsudc - Device controller for which the interrupt is to be handled.
458 * @ep_idx - Endpoint number on which an interrupt is pending.
459 *
460 * Handles interrupt for a out-endpoint. The interrupts that are handled are
461 * stall, flush and data ready interrupt.
462 */
s3c_hsudc_epout_intr(struct s3c_hsudc * hsudc,u32 ep_idx)463 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
464 {
465 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
466 struct s3c_hsudc_req *hsreq;
467 u32 csr;
468
469 csr = readl(hsudc->regs + S3C_ESR);
470 if (csr & S3C_ESR_STALL) {
471 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
472 return;
473 }
474
475 if (csr & S3C_ESR_FLUSH) {
476 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
477 return;
478 }
479
480 if (csr & S3C_ESR_RX_SUCCESS) {
481 if (list_empty(&hsep->queue))
482 return;
483
484 hsreq = list_entry(hsep->queue.next,
485 struct s3c_hsudc_req, queue);
486 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
487 (csr & S3C_ESR_PSIF_TWO))
488 s3c_hsudc_read_fifo(hsep, hsreq);
489 }
490 }
491
492 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
493 * @_ep: Endpoint on which halt has to be set or cleared.
494 * @value: 1 for setting halt on endpoint, 0 to clear halt.
495 *
496 * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
497 * If halt is cleared, for in-endpoints, if there are any pending
498 * transfer requests, transfers are started.
499 */
s3c_hsudc_set_halt(struct usb_ep * _ep,int value)500 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
501 {
502 struct s3c_hsudc_ep *hsep = our_ep(_ep);
503 struct s3c_hsudc *hsudc = hsep->dev;
504 struct s3c_hsudc_req *hsreq;
505 unsigned long irqflags;
506 u32 ecr;
507 u32 offset;
508
509 if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
510 return -EAGAIN;
511
512 spin_lock_irqsave(&hsudc->lock, irqflags);
513 set_index(hsudc, ep_index(hsep));
514 offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
515 ecr = readl(hsudc->regs + offset);
516
517 if (value) {
518 ecr |= S3C_ECR_STALL;
519 if (ep_index(hsep))
520 ecr |= S3C_ECR_FLUSH;
521 hsep->stopped = 1;
522 } else {
523 ecr &= ~S3C_ECR_STALL;
524 hsep->stopped = hsep->wedge = 0;
525 }
526 writel(ecr, hsudc->regs + offset);
527
528 if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
529 hsreq = list_entry(hsep->queue.next,
530 struct s3c_hsudc_req, queue);
531 if (hsreq)
532 s3c_hsudc_write_fifo(hsep, hsreq);
533 }
534
535 spin_unlock_irqrestore(&hsudc->lock, irqflags);
536 return 0;
537 }
538
539 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
540 * @_ep: Endpoint on which wedge has to be set.
541 *
542 * Sets the halt feature with the clear requests ignored.
543 */
s3c_hsudc_set_wedge(struct usb_ep * _ep)544 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
545 {
546 struct s3c_hsudc_ep *hsep = our_ep(_ep);
547
548 if (!hsep)
549 return -EINVAL;
550
551 hsep->wedge = 1;
552 return usb_ep_set_halt(_ep);
553 }
554
555 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
556 * @_ep: Device controller on which the set/clear feature needs to be handled.
557 * @ctrl: Control request as received on the endpoint 0.
558 *
559 * Handle set feature or clear feature control requests on the control endpoint.
560 */
s3c_hsudc_handle_reqfeat(struct s3c_hsudc * hsudc,struct usb_ctrlrequest * ctrl)561 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
562 struct usb_ctrlrequest *ctrl)
563 {
564 struct s3c_hsudc_ep *hsep;
565 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
566 u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
567
568 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
569 hsep = &hsudc->ep[ep_num];
570 switch (le16_to_cpu(ctrl->wValue)) {
571 case USB_ENDPOINT_HALT:
572 if (set || (!set && !hsep->wedge))
573 s3c_hsudc_set_halt(&hsep->ep, set);
574 return 0;
575 }
576 }
577
578 return -ENOENT;
579 }
580
581 /**
582 * s3c_hsudc_process_req_status - Handle get status control request.
583 * @hsudc: Device controller on which get status request has be handled.
584 * @ctrl: Control request as received on the endpoint 0.
585 *
586 * Handle get status control request received on control endpoint.
587 */
s3c_hsudc_process_req_status(struct s3c_hsudc * hsudc,struct usb_ctrlrequest * ctrl)588 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
589 struct usb_ctrlrequest *ctrl)
590 {
591 struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
592 struct s3c_hsudc_req hsreq;
593 struct s3c_hsudc_ep *hsep;
594 __le16 reply;
595 u8 epnum;
596
597 switch (ctrl->bRequestType & USB_RECIP_MASK) {
598 case USB_RECIP_DEVICE:
599 reply = cpu_to_le16(0);
600 break;
601
602 case USB_RECIP_INTERFACE:
603 reply = cpu_to_le16(0);
604 break;
605
606 case USB_RECIP_ENDPOINT:
607 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
608 hsep = &hsudc->ep[epnum];
609 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
610 break;
611 }
612
613 INIT_LIST_HEAD(&hsreq.queue);
614 hsreq.req.length = 2;
615 hsreq.req.buf = &reply;
616 hsreq.req.actual = 0;
617 hsreq.req.complete = NULL;
618 s3c_hsudc_write_fifo(hsep0, &hsreq);
619 }
620
621 /**
622 * s3c_hsudc_process_setup - Process control request received on endpoint 0.
623 * @hsudc: Device controller on which control request has been received.
624 *
625 * Read the control request received on endpoint 0, decode it and handle
626 * the request.
627 */
s3c_hsudc_process_setup(struct s3c_hsudc * hsudc)628 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
629 {
630 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
631 struct usb_ctrlrequest ctrl = {0};
632 int ret;
633
634 s3c_hsudc_nuke_ep(hsep, -EPROTO);
635 s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
636
637 if (ctrl.bRequestType & USB_DIR_IN) {
638 hsep->bEndpointAddress |= USB_DIR_IN;
639 hsudc->ep0state = DATA_STATE_XMIT;
640 } else {
641 hsep->bEndpointAddress &= ~USB_DIR_IN;
642 hsudc->ep0state = DATA_STATE_RECV;
643 }
644
645 switch (ctrl.bRequest) {
646 case USB_REQ_SET_ADDRESS:
647 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
648 break;
649 hsudc->ep0state = WAIT_FOR_SETUP;
650 return;
651
652 case USB_REQ_GET_STATUS:
653 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
654 break;
655 s3c_hsudc_process_req_status(hsudc, &ctrl);
656 return;
657
658 case USB_REQ_SET_FEATURE:
659 case USB_REQ_CLEAR_FEATURE:
660 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
661 break;
662 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
663 hsudc->ep0state = WAIT_FOR_SETUP;
664 return;
665 }
666
667 if (hsudc->driver) {
668 spin_unlock(&hsudc->lock);
669 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
670 spin_lock(&hsudc->lock);
671
672 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
673 hsep->bEndpointAddress &= ~USB_DIR_IN;
674 hsudc->ep0state = WAIT_FOR_SETUP;
675 }
676
677 if (ret < 0) {
678 dev_err(hsudc->dev, "setup failed, returned %d\n",
679 ret);
680 s3c_hsudc_set_halt(&hsep->ep, 1);
681 hsudc->ep0state = WAIT_FOR_SETUP;
682 hsep->bEndpointAddress &= ~USB_DIR_IN;
683 }
684 }
685 }
686
687 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
688 * @hsudc: Device controller on which endpoint 0 interrupt has occured.
689 *
690 * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
691 * when a stall handshake is sent to host or data is sent/received on
692 * endpoint 0.
693 */
s3c_hsudc_handle_ep0_intr(struct s3c_hsudc * hsudc)694 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
695 {
696 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
697 struct s3c_hsudc_req *hsreq;
698 u32 csr = readl(hsudc->regs + S3C_EP0SR);
699 u32 ecr;
700
701 if (csr & S3C_EP0SR_STALL) {
702 ecr = readl(hsudc->regs + S3C_EP0CR);
703 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
704 writel(ecr, hsudc->regs + S3C_EP0CR);
705
706 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
707 hsep->stopped = 0;
708
709 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
710 hsudc->ep0state = WAIT_FOR_SETUP;
711 hsep->bEndpointAddress &= ~USB_DIR_IN;
712 return;
713 }
714
715 if (csr & S3C_EP0SR_TX_SUCCESS) {
716 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
717 if (ep_is_in(hsep)) {
718 if (list_empty(&hsep->queue))
719 return;
720
721 hsreq = list_entry(hsep->queue.next,
722 struct s3c_hsudc_req, queue);
723 s3c_hsudc_write_fifo(hsep, hsreq);
724 }
725 }
726
727 if (csr & S3C_EP0SR_RX_SUCCESS) {
728 if (hsudc->ep0state == WAIT_FOR_SETUP)
729 s3c_hsudc_process_setup(hsudc);
730 else {
731 if (!ep_is_in(hsep)) {
732 if (list_empty(&hsep->queue))
733 return;
734 hsreq = list_entry(hsep->queue.next,
735 struct s3c_hsudc_req, queue);
736 s3c_hsudc_read_fifo(hsep, hsreq);
737 }
738 }
739 }
740 }
741
742 /**
743 * s3c_hsudc_ep_enable - Enable a endpoint.
744 * @_ep: The endpoint to be enabled.
745 * @desc: Endpoint descriptor.
746 *
747 * Enables a endpoint when called from the gadget driver. Endpoint stall if
748 * any is cleared, transfer type is configured and endpoint interrupt is
749 * enabled.
750 */
s3c_hsudc_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)751 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
752 const struct usb_endpoint_descriptor *desc)
753 {
754 struct s3c_hsudc_ep *hsep;
755 struct s3c_hsudc *hsudc;
756 unsigned long flags;
757 u32 ecr = 0;
758
759 hsep = our_ep(_ep);
760 if (!_ep || !desc || _ep->name == ep0name
761 || desc->bDescriptorType != USB_DT_ENDPOINT
762 || hsep->bEndpointAddress != desc->bEndpointAddress
763 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
764 return -EINVAL;
765
766 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
767 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
768 || !desc->wMaxPacketSize)
769 return -ERANGE;
770
771 hsudc = hsep->dev;
772 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
773 return -ESHUTDOWN;
774
775 spin_lock_irqsave(&hsudc->lock, flags);
776
777 set_index(hsudc, hsep->bEndpointAddress);
778 ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
779 writel(ecr, hsudc->regs + S3C_ECR);
780
781 hsep->stopped = hsep->wedge = 0;
782 hsep->ep.desc = desc;
783 hsep->ep.maxpacket = usb_endpoint_maxp(desc);
784
785 s3c_hsudc_set_halt(_ep, 0);
786 __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
787
788 spin_unlock_irqrestore(&hsudc->lock, flags);
789 return 0;
790 }
791
792 /**
793 * s3c_hsudc_ep_disable - Disable a endpoint.
794 * @_ep: The endpoint to be disabled.
795 * @desc: Endpoint descriptor.
796 *
797 * Disables a endpoint when called from the gadget driver.
798 */
s3c_hsudc_ep_disable(struct usb_ep * _ep)799 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
800 {
801 struct s3c_hsudc_ep *hsep = our_ep(_ep);
802 struct s3c_hsudc *hsudc = hsep->dev;
803 unsigned long flags;
804
805 if (!_ep || !hsep->ep.desc)
806 return -EINVAL;
807
808 spin_lock_irqsave(&hsudc->lock, flags);
809
810 set_index(hsudc, hsep->bEndpointAddress);
811 __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
812
813 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
814
815 hsep->ep.desc = NULL;
816 hsep->stopped = 1;
817
818 spin_unlock_irqrestore(&hsudc->lock, flags);
819 return 0;
820 }
821
822 /**
823 * s3c_hsudc_alloc_request - Allocate a new request.
824 * @_ep: Endpoint for which request is allocated (not used).
825 * @gfp_flags: Flags used for the allocation.
826 *
827 * Allocates a single transfer request structure when called from gadget driver.
828 */
s3c_hsudc_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)829 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
830 gfp_t gfp_flags)
831 {
832 struct s3c_hsudc_req *hsreq;
833
834 hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
835 if (!hsreq)
836 return NULL;
837
838 INIT_LIST_HEAD(&hsreq->queue);
839 return &hsreq->req;
840 }
841
842 /**
843 * s3c_hsudc_free_request - Deallocate a request.
844 * @ep: Endpoint for which request is deallocated (not used).
845 * @_req: Request to be deallocated.
846 *
847 * Allocates a single transfer request structure when called from gadget driver.
848 */
s3c_hsudc_free_request(struct usb_ep * ep,struct usb_request * _req)849 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
850 {
851 struct s3c_hsudc_req *hsreq;
852
853 hsreq = our_req(_req);
854 WARN_ON(!list_empty(&hsreq->queue));
855 kfree(hsreq);
856 }
857
858 /**
859 * s3c_hsudc_queue - Queue a transfer request for the endpoint.
860 * @_ep: Endpoint for which the request is queued.
861 * @_req: Request to be queued.
862 * @gfp_flags: Not used.
863 *
864 * Start or enqueue a request for a endpoint when called from gadget driver.
865 */
s3c_hsudc_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)866 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
867 gfp_t gfp_flags)
868 {
869 struct s3c_hsudc_req *hsreq;
870 struct s3c_hsudc_ep *hsep;
871 struct s3c_hsudc *hsudc;
872 unsigned long flags;
873 u32 offset;
874 u32 csr;
875
876 hsreq = our_req(_req);
877 if ((!_req || !_req->complete || !_req->buf ||
878 !list_empty(&hsreq->queue)))
879 return -EINVAL;
880
881 hsep = our_ep(_ep);
882 hsudc = hsep->dev;
883 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
884 return -ESHUTDOWN;
885
886 spin_lock_irqsave(&hsudc->lock, flags);
887 set_index(hsudc, hsep->bEndpointAddress);
888
889 _req->status = -EINPROGRESS;
890 _req->actual = 0;
891
892 if (!ep_index(hsep) && _req->length == 0) {
893 hsudc->ep0state = WAIT_FOR_SETUP;
894 s3c_hsudc_complete_request(hsep, hsreq, 0);
895 spin_unlock_irqrestore(&hsudc->lock, flags);
896 return 0;
897 }
898
899 if (list_empty(&hsep->queue) && !hsep->stopped) {
900 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
901 if (ep_is_in(hsep)) {
902 csr = readl(hsudc->regs + offset);
903 if (!(csr & S3C_ESR_TX_SUCCESS) &&
904 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
905 hsreq = NULL;
906 } else {
907 csr = readl(hsudc->regs + offset);
908 if ((csr & S3C_ESR_RX_SUCCESS)
909 && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
910 hsreq = NULL;
911 }
912 }
913
914 if (hsreq)
915 list_add_tail(&hsreq->queue, &hsep->queue);
916
917 spin_unlock_irqrestore(&hsudc->lock, flags);
918 return 0;
919 }
920
921 /**
922 * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
923 * @_ep: Endpoint from which the request is dequeued.
924 * @_req: Request to be dequeued.
925 *
926 * Dequeue a request from a endpoint when called from gadget driver.
927 */
s3c_hsudc_dequeue(struct usb_ep * _ep,struct usb_request * _req)928 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
929 {
930 struct s3c_hsudc_ep *hsep = our_ep(_ep);
931 struct s3c_hsudc *hsudc = hsep->dev;
932 struct s3c_hsudc_req *hsreq;
933 unsigned long flags;
934
935 hsep = our_ep(_ep);
936 if (!_ep || hsep->ep.name == ep0name)
937 return -EINVAL;
938
939 spin_lock_irqsave(&hsudc->lock, flags);
940
941 list_for_each_entry(hsreq, &hsep->queue, queue) {
942 if (&hsreq->req == _req)
943 break;
944 }
945 if (&hsreq->req != _req) {
946 spin_unlock_irqrestore(&hsudc->lock, flags);
947 return -EINVAL;
948 }
949
950 set_index(hsudc, hsep->bEndpointAddress);
951 s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
952
953 spin_unlock_irqrestore(&hsudc->lock, flags);
954 return 0;
955 }
956
957 static struct usb_ep_ops s3c_hsudc_ep_ops = {
958 .enable = s3c_hsudc_ep_enable,
959 .disable = s3c_hsudc_ep_disable,
960 .alloc_request = s3c_hsudc_alloc_request,
961 .free_request = s3c_hsudc_free_request,
962 .queue = s3c_hsudc_queue,
963 .dequeue = s3c_hsudc_dequeue,
964 .set_halt = s3c_hsudc_set_halt,
965 .set_wedge = s3c_hsudc_set_wedge,
966 };
967
968 /**
969 * s3c_hsudc_initep - Initialize a endpoint to default state.
970 * @hsudc - Reference to the device controller.
971 * @hsep - Endpoint to be initialized.
972 * @epnum - Address to be assigned to the endpoint.
973 *
974 * Initialize a endpoint with default configuration.
975 */
s3c_hsudc_initep(struct s3c_hsudc * hsudc,struct s3c_hsudc_ep * hsep,int epnum)976 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
977 struct s3c_hsudc_ep *hsep, int epnum)
978 {
979 char *dir;
980
981 if ((epnum % 2) == 0) {
982 dir = "out";
983 } else {
984 dir = "in";
985 hsep->bEndpointAddress = USB_DIR_IN;
986 }
987
988 hsep->bEndpointAddress |= epnum;
989 if (epnum)
990 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
991 else
992 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
993
994 INIT_LIST_HEAD(&hsep->queue);
995 INIT_LIST_HEAD(&hsep->ep.ep_list);
996 if (epnum)
997 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
998
999 hsep->dev = hsudc;
1000 hsep->ep.name = hsep->name;
1001 usb_ep_set_maxpacket_limit(&hsep->ep, epnum ? 512 : 64);
1002 hsep->ep.ops = &s3c_hsudc_ep_ops;
1003 hsep->fifo = hsudc->regs + S3C_BR(epnum);
1004 hsep->ep.desc = NULL;
1005 hsep->stopped = 0;
1006 hsep->wedge = 0;
1007
1008 set_index(hsudc, epnum);
1009 writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1010 }
1011
1012 /**
1013 * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1014 * @hsudc: Reference to device controller.
1015 *
1016 * Configures all endpoints to default state.
1017 */
s3c_hsudc_setup_ep(struct s3c_hsudc * hsudc)1018 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1019 {
1020 int epnum;
1021
1022 hsudc->ep0state = WAIT_FOR_SETUP;
1023 INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1024 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1025 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1026 }
1027
1028 /**
1029 * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1030 * @hsudc: Reference to device controller.
1031 *
1032 * Reconfigures the device controller registers to a default state.
1033 */
s3c_hsudc_reconfig(struct s3c_hsudc * hsudc)1034 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1035 {
1036 writel(0xAA, hsudc->regs + S3C_EDR);
1037 writel(1, hsudc->regs + S3C_EIER);
1038 writel(0, hsudc->regs + S3C_TR);
1039 writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1040 S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1041 writel(0, hsudc->regs + S3C_EP0CR);
1042
1043 s3c_hsudc_setup_ep(hsudc);
1044 }
1045
1046 /**
1047 * s3c_hsudc_irq - Interrupt handler for device controller.
1048 * @irq: Not used.
1049 * @_dev: Reference to the device controller.
1050 *
1051 * Interrupt handler for the device controller. This handler handles controller
1052 * interrupts and endpoint interrupts.
1053 */
s3c_hsudc_irq(int irq,void * _dev)1054 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1055 {
1056 struct s3c_hsudc *hsudc = _dev;
1057 struct s3c_hsudc_ep *hsep;
1058 u32 ep_intr;
1059 u32 sys_status;
1060 u32 ep_idx;
1061
1062 spin_lock(&hsudc->lock);
1063
1064 sys_status = readl(hsudc->regs + S3C_SSR);
1065 ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1066
1067 if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1068 spin_unlock(&hsudc->lock);
1069 return IRQ_HANDLED;
1070 }
1071
1072 if (sys_status) {
1073 if (sys_status & S3C_SSR_VBUSON)
1074 writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1075
1076 if (sys_status & S3C_SSR_ERR)
1077 writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1078
1079 if (sys_status & S3C_SSR_SDE) {
1080 writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1081 hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1082 USB_SPEED_HIGH : USB_SPEED_FULL;
1083 }
1084
1085 if (sys_status & S3C_SSR_SUSPEND) {
1086 writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1087 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1088 && hsudc->driver && hsudc->driver->suspend)
1089 hsudc->driver->suspend(&hsudc->gadget);
1090 }
1091
1092 if (sys_status & S3C_SSR_RESUME) {
1093 writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1094 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1095 && hsudc->driver && hsudc->driver->resume)
1096 hsudc->driver->resume(&hsudc->gadget);
1097 }
1098
1099 if (sys_status & S3C_SSR_RESET) {
1100 writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1101 for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1102 hsep = &hsudc->ep[ep_idx];
1103 hsep->stopped = 1;
1104 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1105 }
1106 s3c_hsudc_reconfig(hsudc);
1107 hsudc->ep0state = WAIT_FOR_SETUP;
1108 }
1109 }
1110
1111 if (ep_intr & S3C_EIR_EP0) {
1112 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1113 set_index(hsudc, 0);
1114 s3c_hsudc_handle_ep0_intr(hsudc);
1115 }
1116
1117 ep_intr >>= 1;
1118 ep_idx = 1;
1119 while (ep_intr) {
1120 if (ep_intr & 1) {
1121 hsep = &hsudc->ep[ep_idx];
1122 set_index(hsudc, ep_idx);
1123 writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1124 if (ep_is_in(hsep))
1125 s3c_hsudc_epin_intr(hsudc, ep_idx);
1126 else
1127 s3c_hsudc_epout_intr(hsudc, ep_idx);
1128 }
1129 ep_intr >>= 1;
1130 ep_idx++;
1131 }
1132
1133 spin_unlock(&hsudc->lock);
1134 return IRQ_HANDLED;
1135 }
1136
s3c_hsudc_start(struct usb_gadget * gadget,struct usb_gadget_driver * driver)1137 static int s3c_hsudc_start(struct usb_gadget *gadget,
1138 struct usb_gadget_driver *driver)
1139 {
1140 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1141 int ret;
1142
1143 if (!driver
1144 || driver->max_speed < USB_SPEED_FULL
1145 || !driver->setup)
1146 return -EINVAL;
1147
1148 if (!hsudc)
1149 return -ENODEV;
1150
1151 if (hsudc->driver)
1152 return -EBUSY;
1153
1154 hsudc->driver = driver;
1155
1156 ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1157 hsudc->supplies);
1158 if (ret != 0) {
1159 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1160 goto err_supplies;
1161 }
1162
1163 /* connect to bus through transceiver */
1164 if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1165 ret = otg_set_peripheral(hsudc->transceiver->otg,
1166 &hsudc->gadget);
1167 if (ret) {
1168 dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1169 hsudc->gadget.name);
1170 goto err_otg;
1171 }
1172 }
1173
1174 enable_irq(hsudc->irq);
1175 dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1176
1177 s3c_hsudc_reconfig(hsudc);
1178
1179 pm_runtime_get_sync(hsudc->dev);
1180
1181 s3c_hsudc_init_phy();
1182 if (hsudc->pd->gpio_init)
1183 hsudc->pd->gpio_init();
1184
1185 return 0;
1186 err_otg:
1187 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1188 err_supplies:
1189 hsudc->driver = NULL;
1190 return ret;
1191 }
1192
s3c_hsudc_stop(struct usb_gadget * gadget,struct usb_gadget_driver * driver)1193 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1194 struct usb_gadget_driver *driver)
1195 {
1196 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1197 unsigned long flags;
1198
1199 if (!hsudc)
1200 return -ENODEV;
1201
1202 if (!driver || driver != hsudc->driver)
1203 return -EINVAL;
1204
1205 spin_lock_irqsave(&hsudc->lock, flags);
1206 hsudc->driver = NULL;
1207 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1208 s3c_hsudc_uninit_phy();
1209
1210 pm_runtime_put(hsudc->dev);
1211
1212 if (hsudc->pd->gpio_uninit)
1213 hsudc->pd->gpio_uninit();
1214 s3c_hsudc_stop_activity(hsudc);
1215 spin_unlock_irqrestore(&hsudc->lock, flags);
1216
1217 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1218 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1219
1220 disable_irq(hsudc->irq);
1221
1222 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1223
1224 dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1225 driver->driver.name);
1226 return 0;
1227 }
1228
s3c_hsudc_read_frameno(struct s3c_hsudc * hsudc)1229 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1230 {
1231 return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1232 }
1233
s3c_hsudc_gadget_getframe(struct usb_gadget * gadget)1234 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1235 {
1236 return s3c_hsudc_read_frameno(to_hsudc(gadget));
1237 }
1238
s3c_hsudc_vbus_draw(struct usb_gadget * gadget,unsigned mA)1239 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1240 {
1241 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1242
1243 if (!hsudc)
1244 return -ENODEV;
1245
1246 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1247 return usb_phy_set_power(hsudc->transceiver, mA);
1248
1249 return -EOPNOTSUPP;
1250 }
1251
1252 static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1253 .get_frame = s3c_hsudc_gadget_getframe,
1254 .udc_start = s3c_hsudc_start,
1255 .udc_stop = s3c_hsudc_stop,
1256 .vbus_draw = s3c_hsudc_vbus_draw,
1257 };
1258
s3c_hsudc_probe(struct platform_device * pdev)1259 static int s3c_hsudc_probe(struct platform_device *pdev)
1260 {
1261 struct device *dev = &pdev->dev;
1262 struct resource *res;
1263 struct s3c_hsudc *hsudc;
1264 struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev);
1265 int ret, i;
1266
1267 hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) +
1268 sizeof(struct s3c_hsudc_ep) * pd->epnum,
1269 GFP_KERNEL);
1270 if (!hsudc) {
1271 dev_err(dev, "cannot allocate memory\n");
1272 return -ENOMEM;
1273 }
1274
1275 platform_set_drvdata(pdev, dev);
1276 hsudc->dev = dev;
1277 hsudc->pd = dev_get_platdata(&pdev->dev);
1278
1279 hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
1280
1281 for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1282 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1283
1284 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1285 hsudc->supplies);
1286 if (ret != 0) {
1287 dev_err(dev, "failed to request supplies: %d\n", ret);
1288 goto err_supplies;
1289 }
1290
1291 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292
1293 hsudc->regs = devm_ioremap_resource(&pdev->dev, res);
1294 if (IS_ERR(hsudc->regs)) {
1295 ret = PTR_ERR(hsudc->regs);
1296 goto err_res;
1297 }
1298
1299 spin_lock_init(&hsudc->lock);
1300
1301 hsudc->gadget.max_speed = USB_SPEED_HIGH;
1302 hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1303 hsudc->gadget.name = dev_name(dev);
1304 hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1305 hsudc->gadget.is_otg = 0;
1306 hsudc->gadget.is_a_peripheral = 0;
1307 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1308
1309 s3c_hsudc_setup_ep(hsudc);
1310
1311 ret = platform_get_irq(pdev, 0);
1312 if (ret < 0) {
1313 dev_err(dev, "unable to obtain IRQ number\n");
1314 goto err_res;
1315 }
1316 hsudc->irq = ret;
1317
1318 ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
1319 driver_name, hsudc);
1320 if (ret < 0) {
1321 dev_err(dev, "irq request failed\n");
1322 goto err_res;
1323 }
1324
1325 hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
1326 if (IS_ERR(hsudc->uclk)) {
1327 dev_err(dev, "failed to find usb-device clock source\n");
1328 ret = PTR_ERR(hsudc->uclk);
1329 goto err_res;
1330 }
1331 clk_enable(hsudc->uclk);
1332
1333 local_irq_disable();
1334
1335 disable_irq(hsudc->irq);
1336 local_irq_enable();
1337
1338 ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1339 if (ret)
1340 goto err_add_udc;
1341
1342 pm_runtime_enable(dev);
1343
1344 return 0;
1345 err_add_udc:
1346 clk_disable(hsudc->uclk);
1347 err_res:
1348 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1349 usb_put_phy(hsudc->transceiver);
1350
1351 err_supplies:
1352 return ret;
1353 }
1354
1355 static struct platform_driver s3c_hsudc_driver = {
1356 .driver = {
1357 .owner = THIS_MODULE,
1358 .name = "s3c-hsudc",
1359 },
1360 .probe = s3c_hsudc_probe,
1361 };
1362
1363 module_platform_driver(s3c_hsudc_driver);
1364
1365 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1366 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1367 MODULE_LICENSE("GPL");
1368 MODULE_ALIAS("platform:s3c-hsudc");
1369