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Searched refs:lvds (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/rcar-du/
Drcar_du_lvdsenc.c36 static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data) in rcar_lvds_write() argument
38 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
41 static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds, in rcar_du_lvdsenc_start() argument
51 if (lvds->dpms == DRM_MODE_DPMS_ON) in rcar_du_lvdsenc_start()
54 ret = clk_prepare_enable(lvds->clock); in rcar_du_lvdsenc_start()
68 rcar_lvds_write(lvds, LVDPLLCR, pllcr); in rcar_du_lvdsenc_start()
77 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO | in rcar_du_lvdsenc_start()
81 if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES)) in rcar_du_lvdsenc_start()
88 rcar_lvds_write(lvds, LVDCHCR, lvdhcr); in rcar_du_lvdsenc_start()
96 rcar_lvds_write(lvds, LVDCR0, lvdcr0); in rcar_du_lvdsenc_start()
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Drcar_du_encoder.c47 if (renc->lvds) in rcar_du_encoder_dpms()
48 rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc, mode); in rcar_du_encoder_dpms()
96 if (renc->lvds) in rcar_du_encoder_mode_fixup()
107 if (renc->lvds) in rcar_du_encoder_mode_prepare()
108 rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc, in rcar_du_encoder_mode_prepare()
116 if (renc->lvds) in rcar_du_encoder_mode_commit()
117 rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc, in rcar_du_encoder_mode_commit()
160 renc->lvds = rcdu->lvds[0]; in rcar_du_encoder_init()
164 renc->lvds = rcdu->lvds[1]; in rcar_du_encoder_init()
195 data ? &data->connector.lvds.panel : NULL; in rcar_du_encoder_init()
Drcar_du_lvdsenc.h32 int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
39 static inline int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds, in rcar_du_lvdsenc_dpms() argument
Drcar_du_encoder.h27 struct rcar_du_lvdsenc *lvds; member
Drcar_du_drv.h84 struct rcar_du_lvdsenc *lvds[2]; member
/drivers/gpu/drm/radeon/
Dradeon_combios.c1104 struct radeon_encoder_lvds *lvds = NULL; in radeon_legacy_get_lvds_info_from_regs() local
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); in radeon_legacy_get_lvds_info_from_regs()
1111 if (!lvds) in radeon_legacy_get_lvds_info_from_regs()
1118 lvds->panel_pwr_delay = 200; in radeon_legacy_get_lvds_info_from_regs()
1119 lvds->panel_vcc_delay = 2000; in radeon_legacy_get_lvds_info_from_regs()
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1126 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
1130 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
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Dradeon_legacy_encoders.c62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
63 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
64 if (lvds->bl_dev) in radeon_legacy_lvds_update()
65 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
68 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
69 if (lvds->bl_dev) in radeon_legacy_lvds_update()
70 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_dpms() local
144 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()
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Dradeon_atombios.c1604 struct radeon_encoder_atom_dig *lvds = NULL; in radeon_atombios_get_lvds_info() local
1611 lvds = in radeon_atombios_get_lvds_info()
1614 if (!lvds) in radeon_atombios_get_lvds_info()
1617 lvds->native_mode.clock = in radeon_atombios_get_lvds_info()
1619 lvds->native_mode.hdisplay = in radeon_atombios_get_lvds_info()
1621 lvds->native_mode.vdisplay = in radeon_atombios_get_lvds_info()
1623 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1625 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1627 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_atombios_get_lvds_info()
1629 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()
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Dradeon_legacy_crtc.c799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll() local
800 if (lvds) { in radeon_set_pll()
801 if (lvds->use_bios_dividers) { in radeon_set_pll()
802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
803 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()
804 (lvds->panel_post_divider << 16)); in radeon_set_pll()
/drivers/staging/xgifb/
Dvb_init.c877 struct XGI21_LVDSCapStruct *lvds; in xgifb_read_vbios() local
915 lvds = &xgifb_info->lvds_data; in xgifb_read_vbios()
918 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8); in xgifb_read_vbios()
919 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8); in xgifb_read_vbios()
920 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8); in xgifb_read_vbios()
921 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8); in xgifb_read_vbios()
922 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8); in xgifb_read_vbios()
923 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8); in xgifb_read_vbios()
924 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8); in xgifb_read_vbios()
925 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8); in xgifb_read_vbios()
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/drivers/gpu/drm/gma500/
Dpsb_intel_display.c234 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set() local
236 lvds &= ~LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
238 lvds |= LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
240 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in psb_intel_crtc_mode_set()
245 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in psb_intel_crtc_mode_set()
247 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in psb_intel_crtc_mode_set()
254 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
Dcdv_intel_lvds.c619 u32 lvds; in cdv_intel_lvds_init() local
741 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
742 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in cdv_intel_lvds_init()
745 if (crtc && (lvds & LVDS_PORT_EN)) { in cdv_intel_lvds_init()
Dcdv_intel_display.c749 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set() local
751 lvds |= in cdv_intel_crtc_mode_set()
759 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in cdv_intel_crtc_mode_set()
761 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in cdv_intel_crtc_mode_set()
768 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
Dpsb_intel_lvds.c694 u32 lvds; in psb_intel_lvds_init() local
809 lvds = REG_READ(LVDS); in psb_intel_lvds_init()
810 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in psb_intel_lvds_init()
813 if (crtc && (lvds & LVDS_PORT_EN)) { in psb_intel_lvds_init()
DMakefile53 tc35876x-dsi-lvds.o
/drivers/gpu/drm/nouveau/
Dnv50_display.c1905 struct nv50_disp_sor_lvds_script_v0 lvds; in nv50_sor_mode_set() member
1906 } lvds = { in nv50_sor_mode_set() local
1944 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1946 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
1950 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1953 lvds.lvds.script |= 0x0100; in nv50_sor_mode_set()
1956 if (lvds.lvds.script & 0x0100) { in nv50_sor_mode_set()
1958 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
1961 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
1965 lvds.lvds.script |= 0x0200; in nv50_sor_mode_set()
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Dnouveau_bios.c1034 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); in parse_bit_structure()
/drivers/gpu/drm/i915/
Dintel_lvds.c914 u32 lvds; in intel_lvds_init() local
1099 lvds = I915_READ(LVDS); in intel_lvds_init()
1100 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in intel_lvds_init()
1103 if (crtc && (lvds & LVDS_PORT_EN)) { in intel_lvds_init()
Dintel_display.c8909 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); in i9xx_crtc_clock_get() local
8910 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); in i9xx_crtc_clock_get()
8916 if (lvds & LVDS_CLKB_POWER_UP) in i9xx_crtc_clock_get()
/drivers/video/fbdev/intelfb/
Dintelfb.h206 u32 lvds; member
Dintelfbhw.c580 hw->lvds = INREG(LVDS); in intelfbhw_read_hw_state()
665 int lvds) in calc_vclock() argument
808 printk(" LVDS: 0x%08x\n", hw->lvds); in intelfbhw_print_hw_state()