1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 extern void
34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
35 uint32_t supported_device, u16 caps);
36
37 /* from radeon_legacy_encoder.c */
38 extern void
39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42 union atom_supported_devices {
43 struct _ATOM_SUPPORTED_DEVICES_INFO info;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46 };
47
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
49 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 u8 index)
51 {
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
59 gpio->ucClkMaskShift = 0x19;
60 gpio->ucDataMaskShift = 0x18;
61 }
62 }
63
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev)) {
66 if ((index == 7) &&
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
68 (gpio->sucI2cId.ucAccess == 0)) {
69 gpio->sucI2cId.ucAccess = 0x97;
70 gpio->ucDataMaskShift = 8;
71 gpio->ucDataEnShift = 8;
72 gpio->ucDataY_Shift = 8;
73 gpio->ucDataA_Shift = 8;
74 }
75 }
76
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev)) {
79 if ((index == 4) &&
80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
81 (gpio->sucI2cId.ucAccess == 0x94))
82 gpio->sucI2cId.ucAccess = 0x14;
83 }
84 }
85
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
87 {
88 struct radeon_i2c_bus_rec i2c;
89
90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
91
92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
103 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
108
109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
110 i2c.hw_capable = true;
111 else
112 i2c.hw_capable = false;
113
114 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.mm_i2c = true;
116 else
117 i2c.mm_i2c = false;
118
119 i2c.i2c_id = gpio->sucI2cId.ucAccess;
120
121 if (i2c.mask_clk_reg)
122 i2c.valid = true;
123 else
124 i2c.valid = false;
125
126 return i2c;
127 }
128
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 uint8_t id)
131 {
132 struct atom_context *ctx = rdev->mode_info.atom_context;
133 ATOM_GPIO_I2C_ASSIGMENT *gpio;
134 struct radeon_i2c_bus_rec i2c;
135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
136 struct _ATOM_GPIO_I2C_INFO *i2c_info;
137 uint16_t data_offset, size;
138 int i, num_indices;
139
140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 i2c.valid = false;
142
143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
145
146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
148
149 gpio = &i2c_info->asGPIO_Info[0];
150 for (i = 0; i < num_indices; i++) {
151
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
153
154 if (gpio->sucI2cId.ucAccess == id) {
155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 break;
157 }
158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
160 }
161 }
162
163 return i2c;
164 }
165
radeon_atombios_i2c_init(struct radeon_device * rdev)166 void radeon_atombios_i2c_init(struct radeon_device *rdev)
167 {
168 struct atom_context *ctx = rdev->mode_info.atom_context;
169 ATOM_GPIO_I2C_ASSIGMENT *gpio;
170 struct radeon_i2c_bus_rec i2c;
171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
172 struct _ATOM_GPIO_I2C_INFO *i2c_info;
173 uint16_t data_offset, size;
174 int i, num_indices;
175 char stmp[32];
176
177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
179
180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
181 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
182
183 gpio = &i2c_info->asGPIO_Info[0];
184 for (i = 0; i < num_indices; i++) {
185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
186
187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
188
189 if (i2c.valid) {
190 sprintf(stmp, "0x%x", i2c.i2c_id);
191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
192 }
193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
195 }
196 }
197 }
198
radeon_lookup_gpio(struct radeon_device * rdev,u8 id)199 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
200 u8 id)
201 {
202 struct atom_context *ctx = rdev->mode_info.atom_context;
203 struct radeon_gpio_rec gpio;
204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
205 struct _ATOM_GPIO_PIN_LUT *gpio_info;
206 ATOM_GPIO_PIN_ASSIGNMENT *pin;
207 u16 data_offset, size;
208 int i, num_indices;
209
210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
211 gpio.valid = false;
212
213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
215
216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
218
219 pin = gpio_info->asGPIO_Pin;
220 for (i = 0; i < num_indices; i++) {
221 if (id == pin->ucGPIO_ID) {
222 gpio.id = pin->ucGPIO_ID;
223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234 }
235
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238 {
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279 }
280
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)281 static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287 {
288
289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
290 if ((dev->pdev->device == 0x791e) &&
291 (dev->pdev->subsystem_vendor == 0x1043) &&
292 (dev->pdev->subsystem_device == 0x826d)) {
293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
295 *connector_type = DRM_MODE_CONNECTOR_DVID;
296 }
297
298 /* Asrock RS600 board lists the DVI port as HDMI */
299 if ((dev->pdev->device == 0x7941) &&
300 (dev->pdev->subsystem_vendor == 0x1849) &&
301 (dev->pdev->subsystem_device == 0x7941)) {
302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
304 *connector_type = DRM_MODE_CONNECTOR_DVID;
305 }
306
307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
308 if ((dev->pdev->device == 0x796e) &&
309 (dev->pdev->subsystem_vendor == 0x1462) &&
310 (dev->pdev->subsystem_device == 0x7302)) {
311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
313 return false;
314 }
315
316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
317 if ((dev->pdev->device == 0x7941) &&
318 (dev->pdev->subsystem_vendor == 0x147b) &&
319 (dev->pdev->subsystem_device == 0x2412)) {
320 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
321 return false;
322 }
323
324 /* Falcon NW laptop lists vga ddc line for LVDS */
325 if ((dev->pdev->device == 0x5653) &&
326 (dev->pdev->subsystem_vendor == 0x1462) &&
327 (dev->pdev->subsystem_device == 0x0291)) {
328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
329 i2c_bus->valid = false;
330 *line_mux = 53;
331 }
332 }
333
334 /* HIS X1300 is DVI+VGA, not DVI+DVI */
335 if ((dev->pdev->device == 0x7146) &&
336 (dev->pdev->subsystem_vendor == 0x17af) &&
337 (dev->pdev->subsystem_device == 0x2058)) {
338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
339 return false;
340 }
341
342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
343 if ((dev->pdev->device == 0x7142) &&
344 (dev->pdev->subsystem_vendor == 0x1458) &&
345 (dev->pdev->subsystem_device == 0x2134)) {
346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
347 return false;
348 }
349
350
351 /* Funky macbooks */
352 if ((dev->pdev->device == 0x71C5) &&
353 (dev->pdev->subsystem_vendor == 0x106b) &&
354 (dev->pdev->subsystem_device == 0x0080)) {
355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
357 return false;
358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
359 *line_mux = 0x90;
360 }
361
362 /* mac rv630, rv730, others */
363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
367 }
368
369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
370 if ((dev->pdev->device == 0x9598) &&
371 (dev->pdev->subsystem_vendor == 0x1043) &&
372 (dev->pdev->subsystem_device == 0x01da)) {
373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
374 *connector_type = DRM_MODE_CONNECTOR_DVII;
375 }
376 }
377
378 /* ASUS HD 3600 board lists the DVI port as HDMI */
379 if ((dev->pdev->device == 0x9598) &&
380 (dev->pdev->subsystem_vendor == 0x1043) &&
381 (dev->pdev->subsystem_device == 0x01e4)) {
382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
383 *connector_type = DRM_MODE_CONNECTOR_DVII;
384 }
385 }
386
387 /* ASUS HD 3450 board lists the DVI port as HDMI */
388 if ((dev->pdev->device == 0x95C5) &&
389 (dev->pdev->subsystem_vendor == 0x1043) &&
390 (dev->pdev->subsystem_device == 0x01e2)) {
391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
392 *connector_type = DRM_MODE_CONNECTOR_DVII;
393 }
394 }
395
396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
397 * HDMI + VGA reporting as HDMI
398 */
399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
401 *connector_type = DRM_MODE_CONNECTOR_VGA;
402 *line_mux = 0;
403 }
404 }
405
406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
407 * on the laptop and a DVI port on the docking station and
408 * both share the same encoder, hpd pin, and ddc line.
409 * So while the bios table is technically correct,
410 * we drop the DVI port here since xrandr has no concept of
411 * encoders and will try and drive both connectors
412 * with different crtcs which isn't possible on the hardware
413 * side and leaves no crtcs for LVDS or VGA.
414 */
415 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
416 (dev->pdev->subsystem_vendor == 0x1025) &&
417 (dev->pdev->subsystem_device == 0x013c)) {
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 /* actually it's a DVI-D port not DVI-I */
421 *connector_type = DRM_MODE_CONNECTOR_DVID;
422 return false;
423 }
424 }
425
426 /* XFX Pine Group device rv730 reports no VGA DDC lines
427 * even though they are wired up to record 0x93
428 */
429 if ((dev->pdev->device == 0x9498) &&
430 (dev->pdev->subsystem_vendor == 0x1682) &&
431 (dev->pdev->subsystem_device == 0x2452) &&
432 (i2c_bus->valid == false) &&
433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
436 }
437
438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
439 if (((dev->pdev->device == 0x9802) ||
440 (dev->pdev->device == 0x9805) ||
441 (dev->pdev->device == 0x9806)) &&
442 (dev->pdev->subsystem_vendor == 0x1734) &&
443 (dev->pdev->subsystem_device == 0x11bd)) {
444 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
445 *connector_type = DRM_MODE_CONNECTOR_DVII;
446 *line_mux = 0x3103;
447 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
448 *connector_type = DRM_MODE_CONNECTOR_DVII;
449 }
450 }
451
452 return true;
453 }
454
455 static const int supported_devices_connector_convert[] = {
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_VGA,
458 DRM_MODE_CONNECTOR_DVII,
459 DRM_MODE_CONNECTOR_DVID,
460 DRM_MODE_CONNECTOR_DVIA,
461 DRM_MODE_CONNECTOR_SVIDEO,
462 DRM_MODE_CONNECTOR_Composite,
463 DRM_MODE_CONNECTOR_LVDS,
464 DRM_MODE_CONNECTOR_Unknown,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_HDMIA,
467 DRM_MODE_CONNECTOR_HDMIB,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_9PinDIN,
471 DRM_MODE_CONNECTOR_DisplayPort
472 };
473
474 static const uint16_t supported_devices_connector_object_id_convert[] = {
475 CONNECTOR_OBJECT_ID_NONE,
476 CONNECTOR_OBJECT_ID_VGA,
477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
480 CONNECTOR_OBJECT_ID_COMPOSITE,
481 CONNECTOR_OBJECT_ID_SVIDEO,
482 CONNECTOR_OBJECT_ID_LVDS,
483 CONNECTOR_OBJECT_ID_9PIN_DIN,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_DISPLAYPORT,
486 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
488 CONNECTOR_OBJECT_ID_SVIDEO
489 };
490
491 static const int object_connector_convert[] = {
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_DVII,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVID,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_VGA,
498 DRM_MODE_CONNECTOR_Composite,
499 DRM_MODE_CONNECTOR_SVIDEO,
500 DRM_MODE_CONNECTOR_Unknown,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_9PinDIN,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_HDMIA,
505 DRM_MODE_CONNECTOR_HDMIB,
506 DRM_MODE_CONNECTOR_LVDS,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_DisplayPort,
512 DRM_MODE_CONNECTOR_eDP,
513 DRM_MODE_CONNECTOR_Unknown
514 };
515
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
517 {
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_mode_info *mode_info = &rdev->mode_info;
520 struct atom_context *ctx = mode_info->atom_context;
521 int index = GetIndexIntoMasterTable(DATA, Object_Header);
522 u16 size, data_offset;
523 u8 frev, crev;
524 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
525 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
526 ATOM_OBJECT_TABLE *router_obj;
527 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
528 ATOM_OBJECT_HEADER *obj_header;
529 int i, j, k, path_size, device_support;
530 int connector_type;
531 u16 igp_lane_info, conn_id, connector_object_id;
532 struct radeon_i2c_bus_rec ddc_bus;
533 struct radeon_router router;
534 struct radeon_gpio_rec gpio;
535 struct radeon_hpd hpd;
536
537 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
538 return false;
539
540 if (crev < 2)
541 return false;
542
543 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
544 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
545 (ctx->bios + data_offset +
546 le16_to_cpu(obj_header->usDisplayPathTableOffset));
547 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
548 (ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
550 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
551 (ctx->bios + data_offset +
552 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
553 router_obj = (ATOM_OBJECT_TABLE *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(obj_header->usRouterObjectTableOffset));
556 device_support = le16_to_cpu(obj_header->usDeviceSupport);
557
558 path_size = 0;
559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
560 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
561 ATOM_DISPLAY_OBJECT_PATH *path;
562 addr += path_size;
563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
564 path_size += le16_to_cpu(path->usSize);
565
566 if (device_support & le16_to_cpu(path->usDeviceTag)) {
567 uint8_t con_obj_id, con_obj_num, con_obj_type;
568
569 con_obj_id =
570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
571 >> OBJECT_ID_SHIFT;
572 con_obj_num =
573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
574 >> ENUM_ID_SHIFT;
575 con_obj_type =
576 (le16_to_cpu(path->usConnObjectId) &
577 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
578
579 /* TODO CV support */
580 if (le16_to_cpu(path->usDeviceTag) ==
581 ATOM_DEVICE_CV_SUPPORT)
582 continue;
583
584 /* IGP chips */
585 if ((rdev->flags & RADEON_IS_IGP) &&
586 (con_obj_id ==
587 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
588 uint16_t igp_offset = 0;
589 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
590
591 index =
592 GetIndexIntoMasterTable(DATA,
593 IntegratedSystemInfo);
594
595 if (atom_parse_data_header(ctx, index, &size, &frev,
596 &crev, &igp_offset)) {
597
598 if (crev >= 2) {
599 igp_obj =
600 (ATOM_INTEGRATED_SYSTEM_INFO_V2
601 *) (ctx->bios + igp_offset);
602
603 if (igp_obj) {
604 uint32_t slot_config, ct;
605
606 if (con_obj_num == 1)
607 slot_config =
608 igp_obj->
609 ulDDISlot1Config;
610 else
611 slot_config =
612 igp_obj->
613 ulDDISlot2Config;
614
615 ct = (slot_config >> 16) & 0xff;
616 connector_type =
617 object_connector_convert
618 [ct];
619 connector_object_id = ct;
620 igp_lane_info =
621 slot_config & 0xffff;
622 } else
623 continue;
624 } else
625 continue;
626 } else {
627 igp_lane_info = 0;
628 connector_type =
629 object_connector_convert[con_obj_id];
630 connector_object_id = con_obj_id;
631 }
632 } else {
633 igp_lane_info = 0;
634 connector_type =
635 object_connector_convert[con_obj_id];
636 connector_object_id = con_obj_id;
637 }
638
639 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
640 continue;
641
642 router.ddc_valid = false;
643 router.cd_valid = false;
644 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
645 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
646
647 grph_obj_id =
648 (le16_to_cpu(path->usGraphicObjIds[j]) &
649 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
650 grph_obj_num =
651 (le16_to_cpu(path->usGraphicObjIds[j]) &
652 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
653 grph_obj_type =
654 (le16_to_cpu(path->usGraphicObjIds[j]) &
655 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
656
657 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
658 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
659 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
660 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
661 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
664 ATOM_ENCODER_CAP_RECORD *cap_record;
665 u16 caps = 0;
666
667 while (record->ucRecordSize > 0 &&
668 record->ucRecordType > 0 &&
669 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
670 switch (record->ucRecordType) {
671 case ATOM_ENCODER_CAP_RECORD_TYPE:
672 cap_record =(ATOM_ENCODER_CAP_RECORD *)
673 record;
674 caps = le16_to_cpu(cap_record->usEncoderCap);
675 break;
676 }
677 record = (ATOM_COMMON_RECORD_HEADER *)
678 ((char *)record + record->ucRecordSize);
679 }
680 radeon_add_atom_encoder(dev,
681 encoder_obj,
682 le16_to_cpu
683 (path->
684 usDeviceTag),
685 caps);
686 }
687 }
688 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
689 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
690 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
691 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
692 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
693 (ctx->bios + data_offset +
694 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
695 ATOM_I2C_RECORD *i2c_record;
696 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
697 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
698 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
699 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
700 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
701 (ctx->bios + data_offset +
702 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
703 u8 *num_dst_objs = (u8 *)
704 ((u8 *)router_src_dst_table + 1 +
705 (router_src_dst_table->ucNumberOfSrc * 2));
706 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
707 int enum_id;
708
709 router.router_id = router_obj_id;
710 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
711 if (le16_to_cpu(path->usConnObjectId) ==
712 le16_to_cpu(dst_objs[enum_id]))
713 break;
714 }
715
716 while (record->ucRecordSize > 0 &&
717 record->ucRecordType > 0 &&
718 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
719 switch (record->ucRecordType) {
720 case ATOM_I2C_RECORD_TYPE:
721 i2c_record =
722 (ATOM_I2C_RECORD *)
723 record;
724 i2c_config =
725 (ATOM_I2C_ID_CONFIG_ACCESS *)
726 &i2c_record->sucI2cId;
727 router.i2c_info =
728 radeon_lookup_i2c_gpio(rdev,
729 i2c_config->
730 ucAccess);
731 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
732 break;
733 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
734 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
735 record;
736 router.ddc_valid = true;
737 router.ddc_mux_type = ddc_path->ucMuxType;
738 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
739 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
740 break;
741 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
742 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
743 record;
744 router.cd_valid = true;
745 router.cd_mux_type = cd_path->ucMuxType;
746 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
747 router.cd_mux_state = cd_path->ucMuxState[enum_id];
748 break;
749 }
750 record = (ATOM_COMMON_RECORD_HEADER *)
751 ((char *)record + record->ucRecordSize);
752 }
753 }
754 }
755 }
756 }
757
758 /* look up gpio for ddc, hpd */
759 ddc_bus.valid = false;
760 hpd.hpd = RADEON_HPD_NONE;
761 if ((le16_to_cpu(path->usDeviceTag) &
762 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
763 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
764 if (le16_to_cpu(path->usConnObjectId) ==
765 le16_to_cpu(con_obj->asObjects[j].
766 usObjectID)) {
767 ATOM_COMMON_RECORD_HEADER
768 *record =
769 (ATOM_COMMON_RECORD_HEADER
770 *)
771 (ctx->bios + data_offset +
772 le16_to_cpu(con_obj->
773 asObjects[j].
774 usRecordOffset));
775 ATOM_I2C_RECORD *i2c_record;
776 ATOM_HPD_INT_RECORD *hpd_record;
777 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
778
779 while (record->ucRecordSize > 0 &&
780 record->ucRecordType > 0 &&
781 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
782 switch (record->ucRecordType) {
783 case ATOM_I2C_RECORD_TYPE:
784 i2c_record =
785 (ATOM_I2C_RECORD *)
786 record;
787 i2c_config =
788 (ATOM_I2C_ID_CONFIG_ACCESS *)
789 &i2c_record->sucI2cId;
790 ddc_bus = radeon_lookup_i2c_gpio(rdev,
791 i2c_config->
792 ucAccess);
793 break;
794 case ATOM_HPD_INT_RECORD_TYPE:
795 hpd_record =
796 (ATOM_HPD_INT_RECORD *)
797 record;
798 gpio = radeon_lookup_gpio(rdev,
799 hpd_record->ucHPDIntGPIOID);
800 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
801 hpd.plugged_state = hpd_record->ucPlugged_PinState;
802 break;
803 }
804 record =
805 (ATOM_COMMON_RECORD_HEADER
806 *) ((char *)record
807 +
808 record->
809 ucRecordSize);
810 }
811 break;
812 }
813 }
814 }
815
816 /* needed for aux chan transactions */
817 ddc_bus.hpd = hpd.hpd;
818
819 conn_id = le16_to_cpu(path->usConnObjectId);
820
821 if (!radeon_atom_apply_quirks
822 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
823 &ddc_bus, &conn_id, &hpd))
824 continue;
825
826 radeon_add_atom_connector(dev,
827 conn_id,
828 le16_to_cpu(path->
829 usDeviceTag),
830 connector_type, &ddc_bus,
831 igp_lane_info,
832 connector_object_id,
833 &hpd,
834 &router);
835
836 }
837 }
838
839 radeon_link_encoder_connector(dev);
840
841 return true;
842 }
843
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)844 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
845 int connector_type,
846 uint16_t devices)
847 {
848 struct radeon_device *rdev = dev->dev_private;
849
850 if (rdev->flags & RADEON_IS_IGP) {
851 return supported_devices_connector_object_id_convert
852 [connector_type];
853 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
854 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
855 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
856 struct radeon_mode_info *mode_info = &rdev->mode_info;
857 struct atom_context *ctx = mode_info->atom_context;
858 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
859 uint16_t size, data_offset;
860 uint8_t frev, crev;
861 ATOM_XTMDS_INFO *xtmds;
862
863 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
864 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
865
866 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
867 if (connector_type == DRM_MODE_CONNECTOR_DVII)
868 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
869 else
870 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
871 } else {
872 if (connector_type == DRM_MODE_CONNECTOR_DVII)
873 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
874 else
875 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
876 }
877 } else
878 return supported_devices_connector_object_id_convert
879 [connector_type];
880 } else {
881 return supported_devices_connector_object_id_convert
882 [connector_type];
883 }
884 }
885
886 struct bios_connector {
887 bool valid;
888 uint16_t line_mux;
889 uint16_t devices;
890 int connector_type;
891 struct radeon_i2c_bus_rec ddc_bus;
892 struct radeon_hpd hpd;
893 };
894
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)895 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
896 drm_device
897 *dev)
898 {
899 struct radeon_device *rdev = dev->dev_private;
900 struct radeon_mode_info *mode_info = &rdev->mode_info;
901 struct atom_context *ctx = mode_info->atom_context;
902 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
903 uint16_t size, data_offset;
904 uint8_t frev, crev;
905 uint16_t device_support;
906 uint8_t dac;
907 union atom_supported_devices *supported_devices;
908 int i, j, max_device;
909 struct bios_connector *bios_connectors;
910 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
911 struct radeon_router router;
912
913 router.ddc_valid = false;
914 router.cd_valid = false;
915
916 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
917 if (!bios_connectors)
918 return false;
919
920 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
921 &data_offset)) {
922 kfree(bios_connectors);
923 return false;
924 }
925
926 supported_devices =
927 (union atom_supported_devices *)(ctx->bios + data_offset);
928
929 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
930
931 if (frev > 1)
932 max_device = ATOM_MAX_SUPPORTED_DEVICE;
933 else
934 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
935
936 for (i = 0; i < max_device; i++) {
937 ATOM_CONNECTOR_INFO_I2C ci =
938 supported_devices->info.asConnInfo[i];
939
940 bios_connectors[i].valid = false;
941
942 if (!(device_support & (1 << i))) {
943 continue;
944 }
945
946 if (i == ATOM_DEVICE_CV_INDEX) {
947 DRM_DEBUG_KMS("Skipping Component Video\n");
948 continue;
949 }
950
951 bios_connectors[i].connector_type =
952 supported_devices_connector_convert[ci.sucConnectorInfo.
953 sbfAccess.
954 bfConnectorType];
955
956 if (bios_connectors[i].connector_type ==
957 DRM_MODE_CONNECTOR_Unknown)
958 continue;
959
960 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
961
962 bios_connectors[i].line_mux =
963 ci.sucI2cId.ucAccess;
964
965 /* give tv unique connector ids */
966 if (i == ATOM_DEVICE_TV1_INDEX) {
967 bios_connectors[i].ddc_bus.valid = false;
968 bios_connectors[i].line_mux = 50;
969 } else if (i == ATOM_DEVICE_TV2_INDEX) {
970 bios_connectors[i].ddc_bus.valid = false;
971 bios_connectors[i].line_mux = 51;
972 } else if (i == ATOM_DEVICE_CV_INDEX) {
973 bios_connectors[i].ddc_bus.valid = false;
974 bios_connectors[i].line_mux = 52;
975 } else
976 bios_connectors[i].ddc_bus =
977 radeon_lookup_i2c_gpio(rdev,
978 bios_connectors[i].line_mux);
979
980 if ((crev > 1) && (frev > 1)) {
981 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
982 switch (isb) {
983 case 0x4:
984 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
985 break;
986 case 0xa:
987 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
988 break;
989 default:
990 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
991 break;
992 }
993 } else {
994 if (i == ATOM_DEVICE_DFP1_INDEX)
995 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
996 else if (i == ATOM_DEVICE_DFP2_INDEX)
997 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
998 else
999 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1000 }
1001
1002 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1003 * shared with a DVI port, we'll pick up the DVI connector when we
1004 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1005 */
1006 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1007 bios_connectors[i].connector_type =
1008 DRM_MODE_CONNECTOR_VGA;
1009
1010 if (!radeon_atom_apply_quirks
1011 (dev, (1 << i), &bios_connectors[i].connector_type,
1012 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1013 &bios_connectors[i].hpd))
1014 continue;
1015
1016 bios_connectors[i].valid = true;
1017 bios_connectors[i].devices = (1 << i);
1018
1019 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1020 radeon_add_atom_encoder(dev,
1021 radeon_get_encoder_enum(dev,
1022 (1 << i),
1023 dac),
1024 (1 << i),
1025 0);
1026 else
1027 radeon_add_legacy_encoder(dev,
1028 radeon_get_encoder_enum(dev,
1029 (1 << i),
1030 dac),
1031 (1 << i));
1032 }
1033
1034 /* combine shared connectors */
1035 for (i = 0; i < max_device; i++) {
1036 if (bios_connectors[i].valid) {
1037 for (j = 0; j < max_device; j++) {
1038 if (bios_connectors[j].valid && (i != j)) {
1039 if (bios_connectors[i].line_mux ==
1040 bios_connectors[j].line_mux) {
1041 /* make sure not to combine LVDS */
1042 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1043 bios_connectors[i].line_mux = 53;
1044 bios_connectors[i].ddc_bus.valid = false;
1045 continue;
1046 }
1047 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1048 bios_connectors[j].line_mux = 53;
1049 bios_connectors[j].ddc_bus.valid = false;
1050 continue;
1051 }
1052 /* combine analog and digital for DVI-I */
1053 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1054 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1055 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1056 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1057 bios_connectors[i].devices |=
1058 bios_connectors[j].devices;
1059 bios_connectors[i].connector_type =
1060 DRM_MODE_CONNECTOR_DVII;
1061 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1062 bios_connectors[i].hpd =
1063 bios_connectors[j].hpd;
1064 bios_connectors[j].valid = false;
1065 }
1066 }
1067 }
1068 }
1069 }
1070 }
1071
1072 /* add the connectors */
1073 for (i = 0; i < max_device; i++) {
1074 if (bios_connectors[i].valid) {
1075 uint16_t connector_object_id =
1076 atombios_get_connector_object_id(dev,
1077 bios_connectors[i].connector_type,
1078 bios_connectors[i].devices);
1079 radeon_add_atom_connector(dev,
1080 bios_connectors[i].line_mux,
1081 bios_connectors[i].devices,
1082 bios_connectors[i].
1083 connector_type,
1084 &bios_connectors[i].ddc_bus,
1085 0,
1086 connector_object_id,
1087 &bios_connectors[i].hpd,
1088 &router);
1089 }
1090 }
1091
1092 radeon_link_encoder_connector(dev);
1093
1094 kfree(bios_connectors);
1095 return true;
1096 }
1097
1098 union firmware_info {
1099 ATOM_FIRMWARE_INFO info;
1100 ATOM_FIRMWARE_INFO_V1_2 info_12;
1101 ATOM_FIRMWARE_INFO_V1_3 info_13;
1102 ATOM_FIRMWARE_INFO_V1_4 info_14;
1103 ATOM_FIRMWARE_INFO_V2_1 info_21;
1104 ATOM_FIRMWARE_INFO_V2_2 info_22;
1105 };
1106
radeon_atom_get_clock_info(struct drm_device * dev)1107 bool radeon_atom_get_clock_info(struct drm_device *dev)
1108 {
1109 struct radeon_device *rdev = dev->dev_private;
1110 struct radeon_mode_info *mode_info = &rdev->mode_info;
1111 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1112 union firmware_info *firmware_info;
1113 uint8_t frev, crev;
1114 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1115 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1116 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1117 struct radeon_pll *spll = &rdev->clock.spll;
1118 struct radeon_pll *mpll = &rdev->clock.mpll;
1119 uint16_t data_offset;
1120
1121 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1122 &frev, &crev, &data_offset)) {
1123 firmware_info =
1124 (union firmware_info *)(mode_info->atom_context->bios +
1125 data_offset);
1126 /* pixel clocks */
1127 p1pll->reference_freq =
1128 le16_to_cpu(firmware_info->info.usReferenceClock);
1129 p1pll->reference_div = 0;
1130
1131 if ((frev < 2) && (crev < 2))
1132 p1pll->pll_out_min =
1133 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1134 else
1135 p1pll->pll_out_min =
1136 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1137 p1pll->pll_out_max =
1138 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1139
1140 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1141 p1pll->lcd_pll_out_min =
1142 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1143 if (p1pll->lcd_pll_out_min == 0)
1144 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1145 p1pll->lcd_pll_out_max =
1146 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1147 if (p1pll->lcd_pll_out_max == 0)
1148 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1149 } else {
1150 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1151 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1152 }
1153
1154 if (p1pll->pll_out_min == 0) {
1155 if (ASIC_IS_AVIVO(rdev))
1156 p1pll->pll_out_min = 64800;
1157 else
1158 p1pll->pll_out_min = 20000;
1159 }
1160
1161 p1pll->pll_in_min =
1162 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1163 p1pll->pll_in_max =
1164 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1165
1166 *p2pll = *p1pll;
1167
1168 /* system clock */
1169 if (ASIC_IS_DCE4(rdev))
1170 spll->reference_freq =
1171 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1172 else
1173 spll->reference_freq =
1174 le16_to_cpu(firmware_info->info.usReferenceClock);
1175 spll->reference_div = 0;
1176
1177 spll->pll_out_min =
1178 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1179 spll->pll_out_max =
1180 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1181
1182 /* ??? */
1183 if (spll->pll_out_min == 0) {
1184 if (ASIC_IS_AVIVO(rdev))
1185 spll->pll_out_min = 64800;
1186 else
1187 spll->pll_out_min = 20000;
1188 }
1189
1190 spll->pll_in_min =
1191 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1192 spll->pll_in_max =
1193 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1194
1195 /* memory clock */
1196 if (ASIC_IS_DCE4(rdev))
1197 mpll->reference_freq =
1198 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1199 else
1200 mpll->reference_freq =
1201 le16_to_cpu(firmware_info->info.usReferenceClock);
1202 mpll->reference_div = 0;
1203
1204 mpll->pll_out_min =
1205 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1206 mpll->pll_out_max =
1207 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1208
1209 /* ??? */
1210 if (mpll->pll_out_min == 0) {
1211 if (ASIC_IS_AVIVO(rdev))
1212 mpll->pll_out_min = 64800;
1213 else
1214 mpll->pll_out_min = 20000;
1215 }
1216
1217 mpll->pll_in_min =
1218 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1219 mpll->pll_in_max =
1220 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1221
1222 rdev->clock.default_sclk =
1223 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1224 rdev->clock.default_mclk =
1225 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1226
1227 if (ASIC_IS_DCE4(rdev)) {
1228 rdev->clock.default_dispclk =
1229 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1230 if (rdev->clock.default_dispclk == 0) {
1231 if (ASIC_IS_DCE6(rdev))
1232 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1233 else if (ASIC_IS_DCE5(rdev))
1234 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1235 else
1236 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1237 }
1238 /* set a reasonable default for DP */
1239 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1240 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1241 rdev->clock.default_dispclk / 100);
1242 rdev->clock.default_dispclk = 60000;
1243 }
1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1247 }
1248 *dcpll = *p1pll;
1249
1250 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1251 if (rdev->clock.max_pixel_clock == 0)
1252 rdev->clock.max_pixel_clock = 40000;
1253
1254 /* not technically a clock, but... */
1255 rdev->mode_info.firmware_flags =
1256 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1257
1258 return true;
1259 }
1260
1261 return false;
1262 }
1263
1264 union igp_info {
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1269 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1270 };
1271
radeon_atombios_sideport_present(struct radeon_device * rdev)1272 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1273 {
1274 struct radeon_mode_info *mode_info = &rdev->mode_info;
1275 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1276 union igp_info *igp_info;
1277 u8 frev, crev;
1278 u16 data_offset;
1279
1280 /* sideport is AMD only */
1281 if (rdev->family == CHIP_RS600)
1282 return false;
1283
1284 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1285 &frev, &crev, &data_offset)) {
1286 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1287 data_offset);
1288 switch (crev) {
1289 case 1:
1290 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1291 return true;
1292 break;
1293 case 2:
1294 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1295 return true;
1296 break;
1297 default:
1298 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1299 break;
1300 }
1301 }
1302 return false;
1303 }
1304
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1305 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1306 struct radeon_encoder_int_tmds *tmds)
1307 {
1308 struct drm_device *dev = encoder->base.dev;
1309 struct radeon_device *rdev = dev->dev_private;
1310 struct radeon_mode_info *mode_info = &rdev->mode_info;
1311 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1312 uint16_t data_offset;
1313 struct _ATOM_TMDS_INFO *tmds_info;
1314 uint8_t frev, crev;
1315 uint16_t maxfreq;
1316 int i;
1317
1318 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1319 &frev, &crev, &data_offset)) {
1320 tmds_info =
1321 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1322 data_offset);
1323
1324 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1325 for (i = 0; i < 4; i++) {
1326 tmds->tmds_pll[i].freq =
1327 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1328 tmds->tmds_pll[i].value =
1329 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1330 tmds->tmds_pll[i].value |=
1331 (tmds_info->asMiscInfo[i].
1332 ucPLL_VCO_Gain & 0x3f) << 6;
1333 tmds->tmds_pll[i].value |=
1334 (tmds_info->asMiscInfo[i].
1335 ucPLL_DutyCycle & 0xf) << 12;
1336 tmds->tmds_pll[i].value |=
1337 (tmds_info->asMiscInfo[i].
1338 ucPLL_VoltageSwing & 0xf) << 16;
1339
1340 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1341 tmds->tmds_pll[i].freq,
1342 tmds->tmds_pll[i].value);
1343
1344 if (maxfreq == tmds->tmds_pll[i].freq) {
1345 tmds->tmds_pll[i].freq = 0xffffffff;
1346 break;
1347 }
1348 }
1349 return true;
1350 }
1351 return false;
1352 }
1353
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1354 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1355 struct radeon_atom_ss *ss,
1356 int id)
1357 {
1358 struct radeon_mode_info *mode_info = &rdev->mode_info;
1359 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1360 uint16_t data_offset, size;
1361 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1362 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1363 uint8_t frev, crev;
1364 int i, num_indices;
1365
1366 memset(ss, 0, sizeof(struct radeon_atom_ss));
1367 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1368 &frev, &crev, &data_offset)) {
1369 ss_info =
1370 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1371
1372 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1373 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1374 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1375 ((u8 *)&ss_info->asSS_Info[0]);
1376 for (i = 0; i < num_indices; i++) {
1377 if (ss_assign->ucSS_Id == id) {
1378 ss->percentage =
1379 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1380 ss->type = ss_assign->ucSpreadSpectrumType;
1381 ss->step = ss_assign->ucSS_Step;
1382 ss->delay = ss_assign->ucSS_Delay;
1383 ss->range = ss_assign->ucSS_Range;
1384 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1385 return true;
1386 }
1387 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1388 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1389 }
1390 }
1391 return false;
1392 }
1393
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1394 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1395 struct radeon_atom_ss *ss,
1396 int id)
1397 {
1398 struct radeon_mode_info *mode_info = &rdev->mode_info;
1399 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1400 u16 data_offset, size;
1401 union igp_info *igp_info;
1402 u8 frev, crev;
1403 u16 percentage = 0, rate = 0;
1404
1405 /* get any igp specific overrides */
1406 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1407 &frev, &crev, &data_offset)) {
1408 igp_info = (union igp_info *)
1409 (mode_info->atom_context->bios + data_offset);
1410 switch (crev) {
1411 case 6:
1412 switch (id) {
1413 case ASIC_INTERNAL_SS_ON_TMDS:
1414 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1415 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1416 break;
1417 case ASIC_INTERNAL_SS_ON_HDMI:
1418 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1419 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1420 break;
1421 case ASIC_INTERNAL_SS_ON_LVDS:
1422 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1423 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1424 break;
1425 }
1426 break;
1427 case 7:
1428 switch (id) {
1429 case ASIC_INTERNAL_SS_ON_TMDS:
1430 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1431 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1432 break;
1433 case ASIC_INTERNAL_SS_ON_HDMI:
1434 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1435 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1436 break;
1437 case ASIC_INTERNAL_SS_ON_LVDS:
1438 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1439 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1440 break;
1441 }
1442 break;
1443 case 8:
1444 switch (id) {
1445 case ASIC_INTERNAL_SS_ON_TMDS:
1446 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1447 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1448 break;
1449 case ASIC_INTERNAL_SS_ON_HDMI:
1450 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1451 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1452 break;
1453 case ASIC_INTERNAL_SS_ON_LVDS:
1454 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1455 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1456 break;
1457 }
1458 break;
1459 default:
1460 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1461 break;
1462 }
1463 if (percentage)
1464 ss->percentage = percentage;
1465 if (rate)
1466 ss->rate = rate;
1467 }
1468 }
1469
1470 union asic_ss_info {
1471 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1472 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1473 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1474 };
1475
1476 union asic_ss_assignment {
1477 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1478 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1479 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1480 };
1481
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1482 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1483 struct radeon_atom_ss *ss,
1484 int id, u32 clock)
1485 {
1486 struct radeon_mode_info *mode_info = &rdev->mode_info;
1487 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1488 uint16_t data_offset, size;
1489 union asic_ss_info *ss_info;
1490 union asic_ss_assignment *ss_assign;
1491 uint8_t frev, crev;
1492 int i, num_indices;
1493
1494 if (id == ASIC_INTERNAL_MEMORY_SS) {
1495 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1496 return false;
1497 }
1498 if (id == ASIC_INTERNAL_ENGINE_SS) {
1499 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1500 return false;
1501 }
1502
1503 memset(ss, 0, sizeof(struct radeon_atom_ss));
1504 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1505 &frev, &crev, &data_offset)) {
1506
1507 ss_info =
1508 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1509
1510 switch (frev) {
1511 case 1:
1512 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1513 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1514
1515 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1516 for (i = 0; i < num_indices; i++) {
1517 if ((ss_assign->v1.ucClockIndication == id) &&
1518 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1519 ss->percentage =
1520 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1521 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1522 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1523 ss->percentage_divider = 100;
1524 return true;
1525 }
1526 ss_assign = (union asic_ss_assignment *)
1527 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1528 }
1529 break;
1530 case 2:
1531 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1532 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1533 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1534 for (i = 0; i < num_indices; i++) {
1535 if ((ss_assign->v2.ucClockIndication == id) &&
1536 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1537 ss->percentage =
1538 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1539 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1540 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1541 ss->percentage_divider = 100;
1542 if ((crev == 2) &&
1543 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1544 (id == ASIC_INTERNAL_MEMORY_SS)))
1545 ss->rate /= 100;
1546 return true;
1547 }
1548 ss_assign = (union asic_ss_assignment *)
1549 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1550 }
1551 break;
1552 case 3:
1553 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1554 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1555 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1556 for (i = 0; i < num_indices; i++) {
1557 if ((ss_assign->v3.ucClockIndication == id) &&
1558 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1559 ss->percentage =
1560 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1561 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1562 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1563 if (ss_assign->v3.ucSpreadSpectrumMode &
1564 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1565 ss->percentage_divider = 1000;
1566 else
1567 ss->percentage_divider = 100;
1568 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1569 (id == ASIC_INTERNAL_MEMORY_SS))
1570 ss->rate /= 100;
1571 if (rdev->flags & RADEON_IS_IGP)
1572 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1573 return true;
1574 }
1575 ss_assign = (union asic_ss_assignment *)
1576 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1577 }
1578 break;
1579 default:
1580 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1581 break;
1582 }
1583
1584 }
1585 return false;
1586 }
1587
1588 union lvds_info {
1589 struct _ATOM_LVDS_INFO info;
1590 struct _ATOM_LVDS_INFO_V12 info_12;
1591 };
1592
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1593 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1594 radeon_encoder
1595 *encoder)
1596 {
1597 struct drm_device *dev = encoder->base.dev;
1598 struct radeon_device *rdev = dev->dev_private;
1599 struct radeon_mode_info *mode_info = &rdev->mode_info;
1600 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1601 uint16_t data_offset, misc;
1602 union lvds_info *lvds_info;
1603 uint8_t frev, crev;
1604 struct radeon_encoder_atom_dig *lvds = NULL;
1605 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1606
1607 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1608 &frev, &crev, &data_offset)) {
1609 lvds_info =
1610 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1611 lvds =
1612 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1613
1614 if (!lvds)
1615 return NULL;
1616
1617 lvds->native_mode.clock =
1618 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1619 lvds->native_mode.hdisplay =
1620 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1621 lvds->native_mode.vdisplay =
1622 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1623 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1624 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1625 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1626 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1627 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1628 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1629 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1630 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1631 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1632 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1633 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1634 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1635 lvds->panel_pwr_delay =
1636 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1637 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1638
1639 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1640 if (misc & ATOM_VSYNC_POLARITY)
1641 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1642 if (misc & ATOM_HSYNC_POLARITY)
1643 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1644 if (misc & ATOM_COMPOSITESYNC)
1645 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1646 if (misc & ATOM_INTERLACE)
1647 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1648 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1649 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1650
1651 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1652 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1653
1654 /* set crtc values */
1655 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1656
1657 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1658
1659 encoder->native_mode = lvds->native_mode;
1660
1661 if (encoder_enum == 2)
1662 lvds->linkb = true;
1663 else
1664 lvds->linkb = false;
1665
1666 /* parse the lcd record table */
1667 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1668 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1669 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1670 bool bad_record = false;
1671 u8 *record;
1672
1673 if ((frev == 1) && (crev < 2))
1674 /* absolute */
1675 record = (u8 *)(mode_info->atom_context->bios +
1676 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1677 else
1678 /* relative */
1679 record = (u8 *)(mode_info->atom_context->bios +
1680 data_offset +
1681 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1682 while (*record != ATOM_RECORD_END_TYPE) {
1683 switch (*record) {
1684 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1685 record += sizeof(ATOM_PATCH_RECORD_MODE);
1686 break;
1687 case LCD_RTS_RECORD_TYPE:
1688 record += sizeof(ATOM_LCD_RTS_RECORD);
1689 break;
1690 case LCD_CAP_RECORD_TYPE:
1691 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1692 break;
1693 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1694 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1695 if (fake_edid_record->ucFakeEDIDLength) {
1696 struct edid *edid;
1697 int edid_size =
1698 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1699 edid = kmalloc(edid_size, GFP_KERNEL);
1700 if (edid) {
1701 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1702 fake_edid_record->ucFakeEDIDLength);
1703
1704 if (drm_edid_is_valid(edid)) {
1705 rdev->mode_info.bios_hardcoded_edid = edid;
1706 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1707 } else
1708 kfree(edid);
1709 }
1710 }
1711 record += fake_edid_record->ucFakeEDIDLength ?
1712 fake_edid_record->ucFakeEDIDLength + 2 :
1713 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1714 break;
1715 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1716 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1717 lvds->native_mode.width_mm = panel_res_record->usHSize;
1718 lvds->native_mode.height_mm = panel_res_record->usVSize;
1719 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1720 break;
1721 default:
1722 DRM_ERROR("Bad LCD record %d\n", *record);
1723 bad_record = true;
1724 break;
1725 }
1726 if (bad_record)
1727 break;
1728 }
1729 }
1730 }
1731 return lvds;
1732 }
1733
1734 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1735 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1736 {
1737 struct drm_device *dev = encoder->base.dev;
1738 struct radeon_device *rdev = dev->dev_private;
1739 struct radeon_mode_info *mode_info = &rdev->mode_info;
1740 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1741 uint16_t data_offset;
1742 struct _COMPASSIONATE_DATA *dac_info;
1743 uint8_t frev, crev;
1744 uint8_t bg, dac;
1745 struct radeon_encoder_primary_dac *p_dac = NULL;
1746
1747 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1748 &frev, &crev, &data_offset)) {
1749 dac_info = (struct _COMPASSIONATE_DATA *)
1750 (mode_info->atom_context->bios + data_offset);
1751
1752 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1753
1754 if (!p_dac)
1755 return NULL;
1756
1757 bg = dac_info->ucDAC1_BG_Adjustment;
1758 dac = dac_info->ucDAC1_DAC_Adjustment;
1759 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1760
1761 }
1762 return p_dac;
1763 }
1764
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1765 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1766 struct drm_display_mode *mode)
1767 {
1768 struct radeon_mode_info *mode_info = &rdev->mode_info;
1769 ATOM_ANALOG_TV_INFO *tv_info;
1770 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1771 ATOM_DTD_FORMAT *dtd_timings;
1772 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1773 u8 frev, crev;
1774 u16 data_offset, misc;
1775
1776 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1777 &frev, &crev, &data_offset))
1778 return false;
1779
1780 switch (crev) {
1781 case 1:
1782 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1783 if (index >= MAX_SUPPORTED_TV_TIMING)
1784 return false;
1785
1786 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1787 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1788 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1789 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1790 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1791
1792 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1793 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1794 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1795 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1796 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1797
1798 mode->flags = 0;
1799 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1800 if (misc & ATOM_VSYNC_POLARITY)
1801 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1802 if (misc & ATOM_HSYNC_POLARITY)
1803 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1804 if (misc & ATOM_COMPOSITESYNC)
1805 mode->flags |= DRM_MODE_FLAG_CSYNC;
1806 if (misc & ATOM_INTERLACE)
1807 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1808 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1809 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1810
1811 mode->crtc_clock = mode->clock =
1812 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1813
1814 if (index == 1) {
1815 /* PAL timings appear to have wrong values for totals */
1816 mode->crtc_htotal -= 1;
1817 mode->crtc_vtotal -= 1;
1818 }
1819 break;
1820 case 2:
1821 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1822 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1823 return false;
1824
1825 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1826 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1827 le16_to_cpu(dtd_timings->usHBlanking_Time);
1828 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1829 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1830 le16_to_cpu(dtd_timings->usHSyncOffset);
1831 mode->crtc_hsync_end = mode->crtc_hsync_start +
1832 le16_to_cpu(dtd_timings->usHSyncWidth);
1833
1834 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1835 le16_to_cpu(dtd_timings->usVBlanking_Time);
1836 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1837 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1838 le16_to_cpu(dtd_timings->usVSyncOffset);
1839 mode->crtc_vsync_end = mode->crtc_vsync_start +
1840 le16_to_cpu(dtd_timings->usVSyncWidth);
1841
1842 mode->flags = 0;
1843 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1844 if (misc & ATOM_VSYNC_POLARITY)
1845 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1846 if (misc & ATOM_HSYNC_POLARITY)
1847 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1848 if (misc & ATOM_COMPOSITESYNC)
1849 mode->flags |= DRM_MODE_FLAG_CSYNC;
1850 if (misc & ATOM_INTERLACE)
1851 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1852 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1853 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1854
1855 mode->crtc_clock = mode->clock =
1856 le16_to_cpu(dtd_timings->usPixClk) * 10;
1857 break;
1858 }
1859 return true;
1860 }
1861
1862 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1863 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1864 {
1865 struct radeon_mode_info *mode_info = &rdev->mode_info;
1866 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1867 uint16_t data_offset;
1868 uint8_t frev, crev;
1869 struct _ATOM_ANALOG_TV_INFO *tv_info;
1870 enum radeon_tv_std tv_std = TV_STD_NTSC;
1871
1872 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1873 &frev, &crev, &data_offset)) {
1874
1875 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1876 (mode_info->atom_context->bios + data_offset);
1877
1878 switch (tv_info->ucTV_BootUpDefaultStandard) {
1879 case ATOM_TV_NTSC:
1880 tv_std = TV_STD_NTSC;
1881 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1882 break;
1883 case ATOM_TV_NTSCJ:
1884 tv_std = TV_STD_NTSC_J;
1885 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1886 break;
1887 case ATOM_TV_PAL:
1888 tv_std = TV_STD_PAL;
1889 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1890 break;
1891 case ATOM_TV_PALM:
1892 tv_std = TV_STD_PAL_M;
1893 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1894 break;
1895 case ATOM_TV_PALN:
1896 tv_std = TV_STD_PAL_N;
1897 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1898 break;
1899 case ATOM_TV_PALCN:
1900 tv_std = TV_STD_PAL_CN;
1901 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1902 break;
1903 case ATOM_TV_PAL60:
1904 tv_std = TV_STD_PAL_60;
1905 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1906 break;
1907 case ATOM_TV_SECAM:
1908 tv_std = TV_STD_SECAM;
1909 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1910 break;
1911 default:
1912 tv_std = TV_STD_NTSC;
1913 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1914 break;
1915 }
1916 }
1917 return tv_std;
1918 }
1919
1920 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1921 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1922 {
1923 struct drm_device *dev = encoder->base.dev;
1924 struct radeon_device *rdev = dev->dev_private;
1925 struct radeon_mode_info *mode_info = &rdev->mode_info;
1926 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1927 uint16_t data_offset;
1928 struct _COMPASSIONATE_DATA *dac_info;
1929 uint8_t frev, crev;
1930 uint8_t bg, dac;
1931 struct radeon_encoder_tv_dac *tv_dac = NULL;
1932
1933 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1934 &frev, &crev, &data_offset)) {
1935
1936 dac_info = (struct _COMPASSIONATE_DATA *)
1937 (mode_info->atom_context->bios + data_offset);
1938
1939 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1940
1941 if (!tv_dac)
1942 return NULL;
1943
1944 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1945 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1946 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1947
1948 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1949 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1950 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1951
1952 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1953 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1954 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1955
1956 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1957 }
1958 return tv_dac;
1959 }
1960
1961 static const char *thermal_controller_names[] = {
1962 "NONE",
1963 "lm63",
1964 "adm1032",
1965 "adm1030",
1966 "max6649",
1967 "lm63", /* lm64 */
1968 "f75375",
1969 "asc7xxx",
1970 };
1971
1972 static const char *pp_lib_thermal_controller_names[] = {
1973 "NONE",
1974 "lm63",
1975 "adm1032",
1976 "adm1030",
1977 "max6649",
1978 "lm63", /* lm64 */
1979 "f75375",
1980 "RV6xx",
1981 "RV770",
1982 "adt7473",
1983 "NONE",
1984 "External GPIO",
1985 "Evergreen",
1986 "emc2103",
1987 "Sumo",
1988 "Northern Islands",
1989 "Southern Islands",
1990 "lm96163",
1991 "Sea Islands",
1992 };
1993
1994 union power_info {
1995 struct _ATOM_POWERPLAY_INFO info;
1996 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1997 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1998 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1999 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2000 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2001 };
2002
2003 union pplib_clock_info {
2004 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2005 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2006 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2007 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2008 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2009 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2010 };
2011
2012 union pplib_power_state {
2013 struct _ATOM_PPLIB_STATE v1;
2014 struct _ATOM_PPLIB_STATE_V2 v2;
2015 };
2016
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2017 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2018 int state_index,
2019 u32 misc, u32 misc2)
2020 {
2021 rdev->pm.power_state[state_index].misc = misc;
2022 rdev->pm.power_state[state_index].misc2 = misc2;
2023 /* order matters! */
2024 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2025 rdev->pm.power_state[state_index].type =
2026 POWER_STATE_TYPE_POWERSAVE;
2027 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2028 rdev->pm.power_state[state_index].type =
2029 POWER_STATE_TYPE_BATTERY;
2030 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2031 rdev->pm.power_state[state_index].type =
2032 POWER_STATE_TYPE_BATTERY;
2033 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2034 rdev->pm.power_state[state_index].type =
2035 POWER_STATE_TYPE_BALANCED;
2036 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2037 rdev->pm.power_state[state_index].type =
2038 POWER_STATE_TYPE_PERFORMANCE;
2039 rdev->pm.power_state[state_index].flags &=
2040 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2041 }
2042 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2043 rdev->pm.power_state[state_index].type =
2044 POWER_STATE_TYPE_BALANCED;
2045 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2046 rdev->pm.power_state[state_index].type =
2047 POWER_STATE_TYPE_DEFAULT;
2048 rdev->pm.default_power_state_index = state_index;
2049 rdev->pm.power_state[state_index].default_clock_mode =
2050 &rdev->pm.power_state[state_index].clock_info[0];
2051 } else if (state_index == 0) {
2052 rdev->pm.power_state[state_index].clock_info[0].flags |=
2053 RADEON_PM_MODE_NO_DISPLAY;
2054 }
2055 }
2056
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2057 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2058 {
2059 struct radeon_mode_info *mode_info = &rdev->mode_info;
2060 u32 misc, misc2 = 0;
2061 int num_modes = 0, i;
2062 int state_index = 0;
2063 struct radeon_i2c_bus_rec i2c_bus;
2064 union power_info *power_info;
2065 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2066 u16 data_offset;
2067 u8 frev, crev;
2068
2069 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2070 &frev, &crev, &data_offset))
2071 return state_index;
2072 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2073
2074 /* add the i2c bus for thermal/fan chip */
2075 if ((power_info->info.ucOverdriveThermalController > 0) &&
2076 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2077 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2078 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2079 power_info->info.ucOverdriveControllerAddress >> 1);
2080 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2081 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2082 if (rdev->pm.i2c_bus) {
2083 struct i2c_board_info info = { };
2084 const char *name = thermal_controller_names[power_info->info.
2085 ucOverdriveThermalController];
2086 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2087 strlcpy(info.type, name, sizeof(info.type));
2088 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2089 }
2090 }
2091 num_modes = power_info->info.ucNumOfPowerModeEntries;
2092 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2093 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2094 if (num_modes == 0)
2095 return state_index;
2096 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2097 if (!rdev->pm.power_state)
2098 return state_index;
2099 /* last mode is usually default, array is low to high */
2100 for (i = 0; i < num_modes; i++) {
2101 rdev->pm.power_state[state_index].clock_info =
2102 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2103 if (!rdev->pm.power_state[state_index].clock_info)
2104 return state_index;
2105 rdev->pm.power_state[state_index].num_clock_modes = 1;
2106 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2107 switch (frev) {
2108 case 1:
2109 rdev->pm.power_state[state_index].clock_info[0].mclk =
2110 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2111 rdev->pm.power_state[state_index].clock_info[0].sclk =
2112 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2113 /* skip invalid modes */
2114 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2115 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2116 continue;
2117 rdev->pm.power_state[state_index].pcie_lanes =
2118 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2119 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2120 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2121 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2122 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2123 VOLTAGE_GPIO;
2124 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2125 radeon_lookup_gpio(rdev,
2126 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2127 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2128 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2129 true;
2130 else
2131 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2132 false;
2133 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2134 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2135 VOLTAGE_VDDC;
2136 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2137 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2138 }
2139 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2140 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2141 state_index++;
2142 break;
2143 case 2:
2144 rdev->pm.power_state[state_index].clock_info[0].mclk =
2145 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2146 rdev->pm.power_state[state_index].clock_info[0].sclk =
2147 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2148 /* skip invalid modes */
2149 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2150 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2151 continue;
2152 rdev->pm.power_state[state_index].pcie_lanes =
2153 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2154 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2155 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2156 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2157 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2159 VOLTAGE_GPIO;
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2161 radeon_lookup_gpio(rdev,
2162 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2163 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2165 true;
2166 else
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2168 false;
2169 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2171 VOLTAGE_VDDC;
2172 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2173 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2174 }
2175 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2176 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2177 state_index++;
2178 break;
2179 case 3:
2180 rdev->pm.power_state[state_index].clock_info[0].mclk =
2181 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2182 rdev->pm.power_state[state_index].clock_info[0].sclk =
2183 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2184 /* skip invalid modes */
2185 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2186 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2187 continue;
2188 rdev->pm.power_state[state_index].pcie_lanes =
2189 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2190 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2191 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2192 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2193 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2195 VOLTAGE_GPIO;
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2197 radeon_lookup_gpio(rdev,
2198 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2199 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2201 true;
2202 else
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2204 false;
2205 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2206 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2207 VOLTAGE_VDDC;
2208 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2209 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2210 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2211 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2212 true;
2213 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2214 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2215 }
2216 }
2217 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2218 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2219 state_index++;
2220 break;
2221 }
2222 }
2223 /* last mode is usually default */
2224 if (rdev->pm.default_power_state_index == -1) {
2225 rdev->pm.power_state[state_index - 1].type =
2226 POWER_STATE_TYPE_DEFAULT;
2227 rdev->pm.default_power_state_index = state_index - 1;
2228 rdev->pm.power_state[state_index - 1].default_clock_mode =
2229 &rdev->pm.power_state[state_index - 1].clock_info[0];
2230 rdev->pm.power_state[state_index].flags &=
2231 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2232 rdev->pm.power_state[state_index].misc = 0;
2233 rdev->pm.power_state[state_index].misc2 = 0;
2234 }
2235 return state_index;
2236 }
2237
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2238 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2239 ATOM_PPLIB_THERMALCONTROLLER *controller)
2240 {
2241 struct radeon_i2c_bus_rec i2c_bus;
2242
2243 /* add the i2c bus for thermal/fan chip */
2244 if (controller->ucType > 0) {
2245 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2246 DRM_INFO("Internal thermal controller %s fan control\n",
2247 (controller->ucFanParameters &
2248 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2249 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2250 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2251 DRM_INFO("Internal thermal controller %s fan control\n",
2252 (controller->ucFanParameters &
2253 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2254 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2255 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2256 DRM_INFO("Internal thermal controller %s fan control\n",
2257 (controller->ucFanParameters &
2258 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2259 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2260 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2261 DRM_INFO("Internal thermal controller %s fan control\n",
2262 (controller->ucFanParameters &
2263 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2264 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2265 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2266 DRM_INFO("Internal thermal controller %s fan control\n",
2267 (controller->ucFanParameters &
2268 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2269 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2270 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2271 DRM_INFO("Internal thermal controller %s fan control\n",
2272 (controller->ucFanParameters &
2273 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2274 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2275 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2276 DRM_INFO("Internal thermal controller %s fan control\n",
2277 (controller->ucFanParameters &
2278 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2279 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2280 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2281 DRM_INFO("Internal thermal controller %s fan control\n",
2282 (controller->ucFanParameters &
2283 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2284 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2285 } else if (controller->ucType ==
2286 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2287 DRM_INFO("External GPIO thermal controller %s fan control\n",
2288 (controller->ucFanParameters &
2289 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2291 } else if (controller->ucType ==
2292 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2293 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2294 (controller->ucFanParameters &
2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2297 } else if (controller->ucType ==
2298 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2299 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2300 (controller->ucFanParameters &
2301 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2302 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2303 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2304 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2305 pp_lib_thermal_controller_names[controller->ucType],
2306 controller->ucI2cAddress >> 1,
2307 (controller->ucFanParameters &
2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2310 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2311 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2312 if (rdev->pm.i2c_bus) {
2313 struct i2c_board_info info = { };
2314 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2315 info.addr = controller->ucI2cAddress >> 1;
2316 strlcpy(info.type, name, sizeof(info.type));
2317 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2318 }
2319 } else {
2320 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2321 controller->ucType,
2322 controller->ucI2cAddress >> 1,
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 }
2326 }
2327 }
2328
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2329 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2330 u16 *vddc, u16 *vddci, u16 *mvdd)
2331 {
2332 struct radeon_mode_info *mode_info = &rdev->mode_info;
2333 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2334 u8 frev, crev;
2335 u16 data_offset;
2336 union firmware_info *firmware_info;
2337
2338 *vddc = 0;
2339 *vddci = 0;
2340 *mvdd = 0;
2341
2342 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2343 &frev, &crev, &data_offset)) {
2344 firmware_info =
2345 (union firmware_info *)(mode_info->atom_context->bios +
2346 data_offset);
2347 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2348 if ((frev == 2) && (crev >= 2)) {
2349 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2350 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2351 }
2352 }
2353 }
2354
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2355 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2356 int state_index, int mode_index,
2357 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2358 {
2359 int j;
2360 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2361 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2362 u16 vddc, vddci, mvdd;
2363
2364 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2365
2366 rdev->pm.power_state[state_index].misc = misc;
2367 rdev->pm.power_state[state_index].misc2 = misc2;
2368 rdev->pm.power_state[state_index].pcie_lanes =
2369 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2370 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2371 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2372 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2373 rdev->pm.power_state[state_index].type =
2374 POWER_STATE_TYPE_BATTERY;
2375 break;
2376 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2377 rdev->pm.power_state[state_index].type =
2378 POWER_STATE_TYPE_BALANCED;
2379 break;
2380 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2381 rdev->pm.power_state[state_index].type =
2382 POWER_STATE_TYPE_PERFORMANCE;
2383 break;
2384 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2385 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2386 rdev->pm.power_state[state_index].type =
2387 POWER_STATE_TYPE_PERFORMANCE;
2388 break;
2389 }
2390 rdev->pm.power_state[state_index].flags = 0;
2391 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2392 rdev->pm.power_state[state_index].flags |=
2393 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2394 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2395 rdev->pm.power_state[state_index].type =
2396 POWER_STATE_TYPE_DEFAULT;
2397 rdev->pm.default_power_state_index = state_index;
2398 rdev->pm.power_state[state_index].default_clock_mode =
2399 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2400 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2401 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2402 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2403 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2404 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2405 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2406 } else {
2407 u16 max_vddci = 0;
2408
2409 if (ASIC_IS_DCE4(rdev))
2410 radeon_atom_get_max_voltage(rdev,
2411 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2412 &max_vddci);
2413 /* patch the table values with the default sclk/mclk from firmware info */
2414 for (j = 0; j < mode_index; j++) {
2415 rdev->pm.power_state[state_index].clock_info[j].mclk =
2416 rdev->clock.default_mclk;
2417 rdev->pm.power_state[state_index].clock_info[j].sclk =
2418 rdev->clock.default_sclk;
2419 if (vddc)
2420 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2421 vddc;
2422 if (max_vddci)
2423 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2424 max_vddci;
2425 }
2426 }
2427 }
2428 }
2429
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2430 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2431 int state_index, int mode_index,
2432 union pplib_clock_info *clock_info)
2433 {
2434 u32 sclk, mclk;
2435 u16 vddc;
2436
2437 if (rdev->flags & RADEON_IS_IGP) {
2438 if (rdev->family >= CHIP_PALM) {
2439 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2440 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2441 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2442 } else {
2443 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2444 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2445 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2446 }
2447 } else if (rdev->family >= CHIP_BONAIRE) {
2448 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2449 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2450 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2451 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2452 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2453 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2454 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2455 VOLTAGE_NONE;
2456 } else if (rdev->family >= CHIP_TAHITI) {
2457 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2458 sclk |= clock_info->si.ucEngineClockHigh << 16;
2459 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2460 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2461 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2462 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2463 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2464 VOLTAGE_SW;
2465 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2466 le16_to_cpu(clock_info->si.usVDDC);
2467 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2468 le16_to_cpu(clock_info->si.usVDDCI);
2469 } else if (rdev->family >= CHIP_CEDAR) {
2470 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2471 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2472 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2473 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2474 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2475 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2476 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2477 VOLTAGE_SW;
2478 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2479 le16_to_cpu(clock_info->evergreen.usVDDC);
2480 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2481 le16_to_cpu(clock_info->evergreen.usVDDCI);
2482 } else {
2483 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2484 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2485 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2486 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2487 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2489 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2490 VOLTAGE_SW;
2491 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2492 le16_to_cpu(clock_info->r600.usVDDC);
2493 }
2494
2495 /* patch up vddc if necessary */
2496 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2497 case ATOM_VIRTUAL_VOLTAGE_ID0:
2498 case ATOM_VIRTUAL_VOLTAGE_ID1:
2499 case ATOM_VIRTUAL_VOLTAGE_ID2:
2500 case ATOM_VIRTUAL_VOLTAGE_ID3:
2501 case ATOM_VIRTUAL_VOLTAGE_ID4:
2502 case ATOM_VIRTUAL_VOLTAGE_ID5:
2503 case ATOM_VIRTUAL_VOLTAGE_ID6:
2504 case ATOM_VIRTUAL_VOLTAGE_ID7:
2505 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2507 &vddc) == 0)
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2509 break;
2510 default:
2511 break;
2512 }
2513
2514 if (rdev->flags & RADEON_IS_IGP) {
2515 /* skip invalid modes */
2516 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2517 return false;
2518 } else {
2519 /* skip invalid modes */
2520 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2521 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2522 return false;
2523 }
2524 return true;
2525 }
2526
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2527 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2528 {
2529 struct radeon_mode_info *mode_info = &rdev->mode_info;
2530 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2531 union pplib_power_state *power_state;
2532 int i, j;
2533 int state_index = 0, mode_index = 0;
2534 union pplib_clock_info *clock_info;
2535 bool valid;
2536 union power_info *power_info;
2537 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2538 u16 data_offset;
2539 u8 frev, crev;
2540
2541 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2542 &frev, &crev, &data_offset))
2543 return state_index;
2544 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2545
2546 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2547 if (power_info->pplib.ucNumStates == 0)
2548 return state_index;
2549 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2550 power_info->pplib.ucNumStates, GFP_KERNEL);
2551 if (!rdev->pm.power_state)
2552 return state_index;
2553 /* first mode is usually default, followed by low to high */
2554 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2555 mode_index = 0;
2556 power_state = (union pplib_power_state *)
2557 (mode_info->atom_context->bios + data_offset +
2558 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2559 i * power_info->pplib.ucStateEntrySize);
2560 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2561 (mode_info->atom_context->bios + data_offset +
2562 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2563 (power_state->v1.ucNonClockStateIndex *
2564 power_info->pplib.ucNonClockSize));
2565 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2566 ((power_info->pplib.ucStateEntrySize - 1) ?
2567 (power_info->pplib.ucStateEntrySize - 1) : 1),
2568 GFP_KERNEL);
2569 if (!rdev->pm.power_state[i].clock_info)
2570 return state_index;
2571 if (power_info->pplib.ucStateEntrySize - 1) {
2572 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2573 clock_info = (union pplib_clock_info *)
2574 (mode_info->atom_context->bios + data_offset +
2575 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2576 (power_state->v1.ucClockStateIndices[j] *
2577 power_info->pplib.ucClockInfoSize));
2578 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2579 state_index, mode_index,
2580 clock_info);
2581 if (valid)
2582 mode_index++;
2583 }
2584 } else {
2585 rdev->pm.power_state[state_index].clock_info[0].mclk =
2586 rdev->clock.default_mclk;
2587 rdev->pm.power_state[state_index].clock_info[0].sclk =
2588 rdev->clock.default_sclk;
2589 mode_index++;
2590 }
2591 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2592 if (mode_index) {
2593 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2594 non_clock_info);
2595 state_index++;
2596 }
2597 }
2598 /* if multiple clock modes, mark the lowest as no display */
2599 for (i = 0; i < state_index; i++) {
2600 if (rdev->pm.power_state[i].num_clock_modes > 1)
2601 rdev->pm.power_state[i].clock_info[0].flags |=
2602 RADEON_PM_MODE_NO_DISPLAY;
2603 }
2604 /* first mode is usually default */
2605 if (rdev->pm.default_power_state_index == -1) {
2606 rdev->pm.power_state[0].type =
2607 POWER_STATE_TYPE_DEFAULT;
2608 rdev->pm.default_power_state_index = 0;
2609 rdev->pm.power_state[0].default_clock_mode =
2610 &rdev->pm.power_state[0].clock_info[0];
2611 }
2612 return state_index;
2613 }
2614
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2615 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2616 {
2617 struct radeon_mode_info *mode_info = &rdev->mode_info;
2618 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2619 union pplib_power_state *power_state;
2620 int i, j, non_clock_array_index, clock_array_index;
2621 int state_index = 0, mode_index = 0;
2622 union pplib_clock_info *clock_info;
2623 struct _StateArray *state_array;
2624 struct _ClockInfoArray *clock_info_array;
2625 struct _NonClockInfoArray *non_clock_info_array;
2626 bool valid;
2627 union power_info *power_info;
2628 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2629 u16 data_offset;
2630 u8 frev, crev;
2631 u8 *power_state_offset;
2632
2633 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2634 &frev, &crev, &data_offset))
2635 return state_index;
2636 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2637
2638 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2639 state_array = (struct _StateArray *)
2640 (mode_info->atom_context->bios + data_offset +
2641 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2642 clock_info_array = (struct _ClockInfoArray *)
2643 (mode_info->atom_context->bios + data_offset +
2644 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2645 non_clock_info_array = (struct _NonClockInfoArray *)
2646 (mode_info->atom_context->bios + data_offset +
2647 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2648 if (state_array->ucNumEntries == 0)
2649 return state_index;
2650 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2651 state_array->ucNumEntries, GFP_KERNEL);
2652 if (!rdev->pm.power_state)
2653 return state_index;
2654 power_state_offset = (u8 *)state_array->states;
2655 for (i = 0; i < state_array->ucNumEntries; i++) {
2656 mode_index = 0;
2657 power_state = (union pplib_power_state *)power_state_offset;
2658 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2659 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2660 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2661 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2662 (power_state->v2.ucNumDPMLevels ?
2663 power_state->v2.ucNumDPMLevels : 1),
2664 GFP_KERNEL);
2665 if (!rdev->pm.power_state[i].clock_info)
2666 return state_index;
2667 if (power_state->v2.ucNumDPMLevels) {
2668 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2669 clock_array_index = power_state->v2.clockInfoIndex[j];
2670 clock_info = (union pplib_clock_info *)
2671 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2672 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2673 state_index, mode_index,
2674 clock_info);
2675 if (valid)
2676 mode_index++;
2677 }
2678 } else {
2679 rdev->pm.power_state[state_index].clock_info[0].mclk =
2680 rdev->clock.default_mclk;
2681 rdev->pm.power_state[state_index].clock_info[0].sclk =
2682 rdev->clock.default_sclk;
2683 mode_index++;
2684 }
2685 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2686 if (mode_index) {
2687 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2688 non_clock_info);
2689 state_index++;
2690 }
2691 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2692 }
2693 /* if multiple clock modes, mark the lowest as no display */
2694 for (i = 0; i < state_index; i++) {
2695 if (rdev->pm.power_state[i].num_clock_modes > 1)
2696 rdev->pm.power_state[i].clock_info[0].flags |=
2697 RADEON_PM_MODE_NO_DISPLAY;
2698 }
2699 /* first mode is usually default */
2700 if (rdev->pm.default_power_state_index == -1) {
2701 rdev->pm.power_state[0].type =
2702 POWER_STATE_TYPE_DEFAULT;
2703 rdev->pm.default_power_state_index = 0;
2704 rdev->pm.power_state[0].default_clock_mode =
2705 &rdev->pm.power_state[0].clock_info[0];
2706 }
2707 return state_index;
2708 }
2709
radeon_atombios_get_power_modes(struct radeon_device * rdev)2710 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2711 {
2712 struct radeon_mode_info *mode_info = &rdev->mode_info;
2713 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2714 u16 data_offset;
2715 u8 frev, crev;
2716 int state_index = 0;
2717
2718 rdev->pm.default_power_state_index = -1;
2719
2720 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2721 &frev, &crev, &data_offset)) {
2722 switch (frev) {
2723 case 1:
2724 case 2:
2725 case 3:
2726 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2727 break;
2728 case 4:
2729 case 5:
2730 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2731 break;
2732 case 6:
2733 state_index = radeon_atombios_parse_power_table_6(rdev);
2734 break;
2735 default:
2736 break;
2737 }
2738 }
2739
2740 if (state_index == 0) {
2741 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2742 if (rdev->pm.power_state) {
2743 rdev->pm.power_state[0].clock_info =
2744 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2745 if (rdev->pm.power_state[0].clock_info) {
2746 /* add the default mode */
2747 rdev->pm.power_state[state_index].type =
2748 POWER_STATE_TYPE_DEFAULT;
2749 rdev->pm.power_state[state_index].num_clock_modes = 1;
2750 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2751 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2752 rdev->pm.power_state[state_index].default_clock_mode =
2753 &rdev->pm.power_state[state_index].clock_info[0];
2754 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2755 rdev->pm.power_state[state_index].pcie_lanes = 16;
2756 rdev->pm.default_power_state_index = state_index;
2757 rdev->pm.power_state[state_index].flags = 0;
2758 state_index++;
2759 }
2760 }
2761 }
2762
2763 rdev->pm.num_power_states = state_index;
2764
2765 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2766 rdev->pm.current_clock_mode_index = 0;
2767 if (rdev->pm.default_power_state_index >= 0)
2768 rdev->pm.current_vddc =
2769 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2770 else
2771 rdev->pm.current_vddc = 0;
2772 }
2773
2774 union get_clock_dividers {
2775 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2776 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2777 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2778 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2779 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2780 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2781 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2782 };
2783
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2784 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2785 u8 clock_type,
2786 u32 clock,
2787 bool strobe_mode,
2788 struct atom_clock_dividers *dividers)
2789 {
2790 union get_clock_dividers args;
2791 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2792 u8 frev, crev;
2793
2794 memset(&args, 0, sizeof(args));
2795 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2796
2797 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2798 return -EINVAL;
2799
2800 switch (crev) {
2801 case 1:
2802 /* r4xx, r5xx */
2803 args.v1.ucAction = clock_type;
2804 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2805
2806 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2807
2808 dividers->post_div = args.v1.ucPostDiv;
2809 dividers->fb_div = args.v1.ucFbDiv;
2810 dividers->enable_post_div = true;
2811 break;
2812 case 2:
2813 case 3:
2814 case 5:
2815 /* r6xx, r7xx, evergreen, ni, si */
2816 if (rdev->family <= CHIP_RV770) {
2817 args.v2.ucAction = clock_type;
2818 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2819
2820 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2821
2822 dividers->post_div = args.v2.ucPostDiv;
2823 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2824 dividers->ref_div = args.v2.ucAction;
2825 if (rdev->family == CHIP_RV770) {
2826 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2827 true : false;
2828 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2829 } else
2830 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2831 } else {
2832 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2833 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2834
2835 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2836
2837 dividers->post_div = args.v3.ucPostDiv;
2838 dividers->enable_post_div = (args.v3.ucCntlFlag &
2839 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2840 dividers->enable_dithen = (args.v3.ucCntlFlag &
2841 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2842 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2843 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2844 dividers->ref_div = args.v3.ucRefDiv;
2845 dividers->vco_mode = (args.v3.ucCntlFlag &
2846 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2847 } else {
2848 /* for SI we use ComputeMemoryClockParam for memory plls */
2849 if (rdev->family >= CHIP_TAHITI)
2850 return -EINVAL;
2851 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2852 if (strobe_mode)
2853 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2854
2855 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2856
2857 dividers->post_div = args.v5.ucPostDiv;
2858 dividers->enable_post_div = (args.v5.ucCntlFlag &
2859 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2860 dividers->enable_dithen = (args.v5.ucCntlFlag &
2861 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2862 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2863 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2864 dividers->ref_div = args.v5.ucRefDiv;
2865 dividers->vco_mode = (args.v5.ucCntlFlag &
2866 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2867 }
2868 }
2869 break;
2870 case 4:
2871 /* fusion */
2872 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2873
2874 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2875
2876 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2877 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2878 break;
2879 case 6:
2880 /* CI */
2881 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2882 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2883 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2884
2885 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2886
2887 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2888 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2889 dividers->ref_div = args.v6_out.ucPllRefDiv;
2890 dividers->post_div = args.v6_out.ucPllPostDiv;
2891 dividers->flags = args.v6_out.ucPllCntlFlag;
2892 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2893 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2894 break;
2895 default:
2896 return -EINVAL;
2897 }
2898 return 0;
2899 }
2900
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2901 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2902 u32 clock,
2903 bool strobe_mode,
2904 struct atom_mpll_param *mpll_param)
2905 {
2906 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2907 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2908 u8 frev, crev;
2909
2910 memset(&args, 0, sizeof(args));
2911 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2912
2913 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2914 return -EINVAL;
2915
2916 switch (frev) {
2917 case 2:
2918 switch (crev) {
2919 case 1:
2920 /* SI */
2921 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2922 args.ucInputFlag = 0;
2923 if (strobe_mode)
2924 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2925
2926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2927
2928 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2929 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2930 mpll_param->post_div = args.ucPostDiv;
2931 mpll_param->dll_speed = args.ucDllSpeed;
2932 mpll_param->bwcntl = args.ucBWCntl;
2933 mpll_param->vco_mode =
2934 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2935 mpll_param->yclk_sel =
2936 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2937 mpll_param->qdr =
2938 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2939 mpll_param->half_rate =
2940 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2941 break;
2942 default:
2943 return -EINVAL;
2944 }
2945 break;
2946 default:
2947 return -EINVAL;
2948 }
2949 return 0;
2950 }
2951
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2952 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2953 {
2954 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2955 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2956
2957 args.ucEnable = enable;
2958
2959 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2960 }
2961
radeon_atom_get_engine_clock(struct radeon_device * rdev)2962 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2963 {
2964 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2965 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2966
2967 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2968 return le32_to_cpu(args.ulReturnEngineClock);
2969 }
2970
radeon_atom_get_memory_clock(struct radeon_device * rdev)2971 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2972 {
2973 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2974 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2975
2976 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2977 return le32_to_cpu(args.ulReturnMemoryClock);
2978 }
2979
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)2980 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2981 uint32_t eng_clock)
2982 {
2983 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2984 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2985
2986 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2987
2988 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2989 }
2990
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)2991 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2992 uint32_t mem_clock)
2993 {
2994 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2995 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2996
2997 if (rdev->flags & RADEON_IS_IGP)
2998 return;
2999
3000 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3001
3002 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3003 }
3004
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3005 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3006 u32 eng_clock, u32 mem_clock)
3007 {
3008 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3009 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3010 u32 tmp;
3011
3012 memset(&args, 0, sizeof(args));
3013
3014 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3015 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3016
3017 args.ulTargetEngineClock = cpu_to_le32(tmp);
3018 if (mem_clock)
3019 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3020
3021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3022 }
3023
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3024 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3025 u32 mem_clock)
3026 {
3027 u32 args;
3028 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3029
3030 args = cpu_to_le32(mem_clock); /* 10 khz */
3031
3032 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3033 }
3034
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3035 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3036 u32 mem_clock)
3037 {
3038 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3039 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3040 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3041
3042 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3043
3044 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3045 }
3046
3047 union set_voltage {
3048 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3049 struct _SET_VOLTAGE_PARAMETERS v1;
3050 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3051 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3052 };
3053
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3054 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3055 {
3056 union set_voltage args;
3057 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3058 u8 frev, crev, volt_index = voltage_level;
3059
3060 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3061 return;
3062
3063 /* 0xff01 is a flag rather then an actual voltage */
3064 if (voltage_level == 0xff01)
3065 return;
3066
3067 switch (crev) {
3068 case 1:
3069 args.v1.ucVoltageType = voltage_type;
3070 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3071 args.v1.ucVoltageIndex = volt_index;
3072 break;
3073 case 2:
3074 args.v2.ucVoltageType = voltage_type;
3075 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3076 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3077 break;
3078 case 3:
3079 args.v3.ucVoltageType = voltage_type;
3080 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3081 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3082 break;
3083 default:
3084 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3085 return;
3086 }
3087
3088 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3089 }
3090
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3091 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3092 u16 voltage_id, u16 *voltage)
3093 {
3094 union set_voltage args;
3095 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3096 u8 frev, crev;
3097
3098 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3099 return -EINVAL;
3100
3101 switch (crev) {
3102 case 1:
3103 return -EINVAL;
3104 case 2:
3105 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3106 args.v2.ucVoltageMode = 0;
3107 args.v2.usVoltageLevel = 0;
3108
3109 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3110
3111 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3112 break;
3113 case 3:
3114 args.v3.ucVoltageType = voltage_type;
3115 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3116 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3117
3118 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3119
3120 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3121 break;
3122 default:
3123 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3124 return -EINVAL;
3125 }
3126
3127 return 0;
3128 }
3129
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3130 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3131 u16 *voltage,
3132 u16 leakage_idx)
3133 {
3134 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3135 }
3136
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3137 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3138 u16 *leakage_id)
3139 {
3140 union set_voltage args;
3141 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3142 u8 frev, crev;
3143
3144 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3145 return -EINVAL;
3146
3147 switch (crev) {
3148 case 3:
3149 case 4:
3150 args.v3.ucVoltageType = 0;
3151 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3152 args.v3.usVoltageLevel = 0;
3153
3154 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3155
3156 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3157 break;
3158 default:
3159 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3160 return -EINVAL;
3161 }
3162
3163 return 0;
3164 }
3165
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3166 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3167 u16 *vddc, u16 *vddci,
3168 u16 virtual_voltage_id,
3169 u16 vbios_voltage_id)
3170 {
3171 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3172 u8 frev, crev;
3173 u16 data_offset, size;
3174 int i, j;
3175 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3176 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3177
3178 *vddc = 0;
3179 *vddci = 0;
3180
3181 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3182 &frev, &crev, &data_offset))
3183 return -EINVAL;
3184
3185 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3186 (rdev->mode_info.atom_context->bios + data_offset);
3187
3188 switch (frev) {
3189 case 1:
3190 return -EINVAL;
3191 case 2:
3192 switch (crev) {
3193 case 1:
3194 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3195 return -EINVAL;
3196 leakage_bin = (u16 *)
3197 (rdev->mode_info.atom_context->bios + data_offset +
3198 le16_to_cpu(profile->usLeakageBinArrayOffset));
3199 vddc_id_buf = (u16 *)
3200 (rdev->mode_info.atom_context->bios + data_offset +
3201 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3202 vddc_buf = (u16 *)
3203 (rdev->mode_info.atom_context->bios + data_offset +
3204 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3205 vddci_id_buf = (u16 *)
3206 (rdev->mode_info.atom_context->bios + data_offset +
3207 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3208 vddci_buf = (u16 *)
3209 (rdev->mode_info.atom_context->bios + data_offset +
3210 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3211
3212 if (profile->ucElbVDDC_Num > 0) {
3213 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3214 if (vddc_id_buf[i] == virtual_voltage_id) {
3215 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3216 if (vbios_voltage_id <= leakage_bin[j]) {
3217 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3218 break;
3219 }
3220 }
3221 break;
3222 }
3223 }
3224 }
3225 if (profile->ucElbVDDCI_Num > 0) {
3226 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3227 if (vddci_id_buf[i] == virtual_voltage_id) {
3228 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3229 if (vbios_voltage_id <= leakage_bin[j]) {
3230 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3231 break;
3232 }
3233 }
3234 break;
3235 }
3236 }
3237 }
3238 break;
3239 default:
3240 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3241 return -EINVAL;
3242 }
3243 break;
3244 default:
3245 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3246 return -EINVAL;
3247 }
3248
3249 return 0;
3250 }
3251
3252 union get_voltage_info {
3253 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3254 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3255 };
3256
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3257 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3258 u16 virtual_voltage_id,
3259 u16 *voltage)
3260 {
3261 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3262 u32 entry_id;
3263 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3264 union get_voltage_info args;
3265
3266 for (entry_id = 0; entry_id < count; entry_id++) {
3267 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3268 virtual_voltage_id)
3269 break;
3270 }
3271
3272 if (entry_id >= count)
3273 return -EINVAL;
3274
3275 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3276 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3277 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3278 args.in.ulSCLKFreq =
3279 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3280
3281 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3282
3283 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3284
3285 return 0;
3286 }
3287
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3288 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3289 u16 voltage_level, u8 voltage_type,
3290 u32 *gpio_value, u32 *gpio_mask)
3291 {
3292 union set_voltage args;
3293 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3294 u8 frev, crev;
3295
3296 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3297 return -EINVAL;
3298
3299 switch (crev) {
3300 case 1:
3301 return -EINVAL;
3302 case 2:
3303 args.v2.ucVoltageType = voltage_type;
3304 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3305 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3306
3307 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3308
3309 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3310
3311 args.v2.ucVoltageType = voltage_type;
3312 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3313 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3314
3315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3316
3317 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3318 break;
3319 default:
3320 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3321 return -EINVAL;
3322 }
3323
3324 return 0;
3325 }
3326
3327 union voltage_object_info {
3328 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3329 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3330 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3331 };
3332
3333 union voltage_object {
3334 struct _ATOM_VOLTAGE_OBJECT v1;
3335 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3336 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3337 };
3338
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3339 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3340 u8 voltage_type)
3341 {
3342 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3343 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3344 u8 *start = (u8 *)v1;
3345
3346 while (offset < size) {
3347 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3348 if (vo->ucVoltageType == voltage_type)
3349 return vo;
3350 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3351 vo->asFormula.ucNumOfVoltageEntries;
3352 }
3353 return NULL;
3354 }
3355
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3356 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3357 u8 voltage_type)
3358 {
3359 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3360 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3361 u8 *start = (u8*)v2;
3362
3363 while (offset < size) {
3364 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3365 if (vo->ucVoltageType == voltage_type)
3366 return vo;
3367 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3368 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3369 }
3370 return NULL;
3371 }
3372
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3373 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3374 u8 voltage_type, u8 voltage_mode)
3375 {
3376 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3377 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3378 u8 *start = (u8*)v3;
3379
3380 while (offset < size) {
3381 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3382 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3383 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3384 return vo;
3385 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3386 }
3387 return NULL;
3388 }
3389
3390 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3391 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3392 u8 voltage_type, u8 voltage_mode)
3393 {
3394 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3395 u8 frev, crev;
3396 u16 data_offset, size;
3397 union voltage_object_info *voltage_info;
3398 union voltage_object *voltage_object = NULL;
3399
3400 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3401 &frev, &crev, &data_offset)) {
3402 voltage_info = (union voltage_object_info *)
3403 (rdev->mode_info.atom_context->bios + data_offset);
3404
3405 switch (frev) {
3406 case 1:
3407 case 2:
3408 switch (crev) {
3409 case 1:
3410 voltage_object = (union voltage_object *)
3411 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3412 if (voltage_object &&
3413 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3414 return true;
3415 break;
3416 case 2:
3417 voltage_object = (union voltage_object *)
3418 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3419 if (voltage_object &&
3420 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3421 return true;
3422 break;
3423 default:
3424 DRM_ERROR("unknown voltage object table\n");
3425 return false;
3426 }
3427 break;
3428 case 3:
3429 switch (crev) {
3430 case 1:
3431 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3432 voltage_type, voltage_mode))
3433 return true;
3434 break;
3435 default:
3436 DRM_ERROR("unknown voltage object table\n");
3437 return false;
3438 }
3439 break;
3440 default:
3441 DRM_ERROR("unknown voltage object table\n");
3442 return false;
3443 }
3444
3445 }
3446 return false;
3447 }
3448
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3449 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3450 u8 voltage_type,
3451 u8 *svd_gpio_id, u8 *svc_gpio_id)
3452 {
3453 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3454 u8 frev, crev;
3455 u16 data_offset, size;
3456 union voltage_object_info *voltage_info;
3457 union voltage_object *voltage_object = NULL;
3458
3459 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3460 &frev, &crev, &data_offset)) {
3461 voltage_info = (union voltage_object_info *)
3462 (rdev->mode_info.atom_context->bios + data_offset);
3463
3464 switch (frev) {
3465 case 3:
3466 switch (crev) {
3467 case 1:
3468 voltage_object = (union voltage_object *)
3469 atom_lookup_voltage_object_v3(&voltage_info->v3,
3470 voltage_type,
3471 VOLTAGE_OBJ_SVID2);
3472 if (voltage_object) {
3473 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3474 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3475 } else {
3476 return -EINVAL;
3477 }
3478 break;
3479 default:
3480 DRM_ERROR("unknown voltage object table\n");
3481 return -EINVAL;
3482 }
3483 break;
3484 default:
3485 DRM_ERROR("unknown voltage object table\n");
3486 return -EINVAL;
3487 }
3488
3489 }
3490 return 0;
3491 }
3492
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3493 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3494 u8 voltage_type, u16 *max_voltage)
3495 {
3496 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3497 u8 frev, crev;
3498 u16 data_offset, size;
3499 union voltage_object_info *voltage_info;
3500 union voltage_object *voltage_object = NULL;
3501
3502 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3503 &frev, &crev, &data_offset)) {
3504 voltage_info = (union voltage_object_info *)
3505 (rdev->mode_info.atom_context->bios + data_offset);
3506
3507 switch (crev) {
3508 case 1:
3509 voltage_object = (union voltage_object *)
3510 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3511 if (voltage_object) {
3512 ATOM_VOLTAGE_FORMULA *formula =
3513 &voltage_object->v1.asFormula;
3514 if (formula->ucFlag & 1)
3515 *max_voltage =
3516 le16_to_cpu(formula->usVoltageBaseLevel) +
3517 formula->ucNumOfVoltageEntries / 2 *
3518 le16_to_cpu(formula->usVoltageStep);
3519 else
3520 *max_voltage =
3521 le16_to_cpu(formula->usVoltageBaseLevel) +
3522 (formula->ucNumOfVoltageEntries - 1) *
3523 le16_to_cpu(formula->usVoltageStep);
3524 return 0;
3525 }
3526 break;
3527 case 2:
3528 voltage_object = (union voltage_object *)
3529 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3530 if (voltage_object) {
3531 ATOM_VOLTAGE_FORMULA_V2 *formula =
3532 &voltage_object->v2.asFormula;
3533 if (formula->ucNumOfVoltageEntries) {
3534 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3535 ((u8 *)&formula->asVIDAdjustEntries[0] +
3536 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3537 *max_voltage =
3538 le16_to_cpu(lut->usVoltageValue);
3539 return 0;
3540 }
3541 }
3542 break;
3543 default:
3544 DRM_ERROR("unknown voltage object table\n");
3545 return -EINVAL;
3546 }
3547
3548 }
3549 return -EINVAL;
3550 }
3551
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3552 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3553 u8 voltage_type, u16 *min_voltage)
3554 {
3555 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3556 u8 frev, crev;
3557 u16 data_offset, size;
3558 union voltage_object_info *voltage_info;
3559 union voltage_object *voltage_object = NULL;
3560
3561 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3562 &frev, &crev, &data_offset)) {
3563 voltage_info = (union voltage_object_info *)
3564 (rdev->mode_info.atom_context->bios + data_offset);
3565
3566 switch (crev) {
3567 case 1:
3568 voltage_object = (union voltage_object *)
3569 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3570 if (voltage_object) {
3571 ATOM_VOLTAGE_FORMULA *formula =
3572 &voltage_object->v1.asFormula;
3573 *min_voltage =
3574 le16_to_cpu(formula->usVoltageBaseLevel);
3575 return 0;
3576 }
3577 break;
3578 case 2:
3579 voltage_object = (union voltage_object *)
3580 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3581 if (voltage_object) {
3582 ATOM_VOLTAGE_FORMULA_V2 *formula =
3583 &voltage_object->v2.asFormula;
3584 if (formula->ucNumOfVoltageEntries) {
3585 *min_voltage =
3586 le16_to_cpu(formula->asVIDAdjustEntries[
3587 0
3588 ].usVoltageValue);
3589 return 0;
3590 }
3591 }
3592 break;
3593 default:
3594 DRM_ERROR("unknown voltage object table\n");
3595 return -EINVAL;
3596 }
3597
3598 }
3599 return -EINVAL;
3600 }
3601
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3602 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3603 u8 voltage_type, u16 *voltage_step)
3604 {
3605 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3606 u8 frev, crev;
3607 u16 data_offset, size;
3608 union voltage_object_info *voltage_info;
3609 union voltage_object *voltage_object = NULL;
3610
3611 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3612 &frev, &crev, &data_offset)) {
3613 voltage_info = (union voltage_object_info *)
3614 (rdev->mode_info.atom_context->bios + data_offset);
3615
3616 switch (crev) {
3617 case 1:
3618 voltage_object = (union voltage_object *)
3619 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3620 if (voltage_object) {
3621 ATOM_VOLTAGE_FORMULA *formula =
3622 &voltage_object->v1.asFormula;
3623 if (formula->ucFlag & 1)
3624 *voltage_step =
3625 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3626 else
3627 *voltage_step =
3628 le16_to_cpu(formula->usVoltageStep);
3629 return 0;
3630 }
3631 break;
3632 case 2:
3633 return -EINVAL;
3634 default:
3635 DRM_ERROR("unknown voltage object table\n");
3636 return -EINVAL;
3637 }
3638
3639 }
3640 return -EINVAL;
3641 }
3642
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3643 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3644 u8 voltage_type,
3645 u16 nominal_voltage,
3646 u16 *true_voltage)
3647 {
3648 u16 min_voltage, max_voltage, voltage_step;
3649
3650 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3651 return -EINVAL;
3652 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3653 return -EINVAL;
3654 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3655 return -EINVAL;
3656
3657 if (nominal_voltage <= min_voltage)
3658 *true_voltage = min_voltage;
3659 else if (nominal_voltage >= max_voltage)
3660 *true_voltage = max_voltage;
3661 else
3662 *true_voltage = min_voltage +
3663 ((nominal_voltage - min_voltage) / voltage_step) *
3664 voltage_step;
3665
3666 return 0;
3667 }
3668
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3669 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3670 u8 voltage_type, u8 voltage_mode,
3671 struct atom_voltage_table *voltage_table)
3672 {
3673 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3674 u8 frev, crev;
3675 u16 data_offset, size;
3676 int i, ret;
3677 union voltage_object_info *voltage_info;
3678 union voltage_object *voltage_object = NULL;
3679
3680 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3681 &frev, &crev, &data_offset)) {
3682 voltage_info = (union voltage_object_info *)
3683 (rdev->mode_info.atom_context->bios + data_offset);
3684
3685 switch (frev) {
3686 case 1:
3687 case 2:
3688 switch (crev) {
3689 case 1:
3690 DRM_ERROR("old table version %d, %d\n", frev, crev);
3691 return -EINVAL;
3692 case 2:
3693 voltage_object = (union voltage_object *)
3694 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3695 if (voltage_object) {
3696 ATOM_VOLTAGE_FORMULA_V2 *formula =
3697 &voltage_object->v2.asFormula;
3698 VOLTAGE_LUT_ENTRY *lut;
3699 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3700 return -EINVAL;
3701 lut = &formula->asVIDAdjustEntries[0];
3702 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3703 voltage_table->entries[i].value =
3704 le16_to_cpu(lut->usVoltageValue);
3705 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3706 voltage_table->entries[i].value,
3707 voltage_type,
3708 &voltage_table->entries[i].smio_low,
3709 &voltage_table->mask_low);
3710 if (ret)
3711 return ret;
3712 lut = (VOLTAGE_LUT_ENTRY *)
3713 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3714 }
3715 voltage_table->count = formula->ucNumOfVoltageEntries;
3716 return 0;
3717 }
3718 break;
3719 default:
3720 DRM_ERROR("unknown voltage object table\n");
3721 return -EINVAL;
3722 }
3723 break;
3724 case 3:
3725 switch (crev) {
3726 case 1:
3727 voltage_object = (union voltage_object *)
3728 atom_lookup_voltage_object_v3(&voltage_info->v3,
3729 voltage_type, voltage_mode);
3730 if (voltage_object) {
3731 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3732 &voltage_object->v3.asGpioVoltageObj;
3733 VOLTAGE_LUT_ENTRY_V2 *lut;
3734 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3735 return -EINVAL;
3736 lut = &gpio->asVolGpioLut[0];
3737 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3738 voltage_table->entries[i].value =
3739 le16_to_cpu(lut->usVoltageValue);
3740 voltage_table->entries[i].smio_low =
3741 le32_to_cpu(lut->ulVoltageId);
3742 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3743 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3744 }
3745 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3746 voltage_table->count = gpio->ucGpioEntryNum;
3747 voltage_table->phase_delay = gpio->ucPhaseDelay;
3748 return 0;
3749 }
3750 break;
3751 default:
3752 DRM_ERROR("unknown voltage object table\n");
3753 return -EINVAL;
3754 }
3755 break;
3756 default:
3757 DRM_ERROR("unknown voltage object table\n");
3758 return -EINVAL;
3759 }
3760 }
3761 return -EINVAL;
3762 }
3763
3764 union vram_info {
3765 struct _ATOM_VRAM_INFO_V3 v1_3;
3766 struct _ATOM_VRAM_INFO_V4 v1_4;
3767 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3768 };
3769
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3770 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3771 u8 module_index, struct atom_memory_info *mem_info)
3772 {
3773 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3774 u8 frev, crev, i;
3775 u16 data_offset, size;
3776 union vram_info *vram_info;
3777
3778 memset(mem_info, 0, sizeof(struct atom_memory_info));
3779
3780 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3781 &frev, &crev, &data_offset)) {
3782 vram_info = (union vram_info *)
3783 (rdev->mode_info.atom_context->bios + data_offset);
3784 switch (frev) {
3785 case 1:
3786 switch (crev) {
3787 case 3:
3788 /* r6xx */
3789 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3790 ATOM_VRAM_MODULE_V3 *vram_module =
3791 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3792
3793 for (i = 0; i < module_index; i++) {
3794 if (le16_to_cpu(vram_module->usSize) == 0)
3795 return -EINVAL;
3796 vram_module = (ATOM_VRAM_MODULE_V3 *)
3797 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3798 }
3799 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3800 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3801 } else
3802 return -EINVAL;
3803 break;
3804 case 4:
3805 /* r7xx, evergreen */
3806 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3807 ATOM_VRAM_MODULE_V4 *vram_module =
3808 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3809
3810 for (i = 0; i < module_index; i++) {
3811 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3812 return -EINVAL;
3813 vram_module = (ATOM_VRAM_MODULE_V4 *)
3814 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3815 }
3816 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3817 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3818 } else
3819 return -EINVAL;
3820 break;
3821 default:
3822 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3823 return -EINVAL;
3824 }
3825 break;
3826 case 2:
3827 switch (crev) {
3828 case 1:
3829 /* ni */
3830 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3831 ATOM_VRAM_MODULE_V7 *vram_module =
3832 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3833
3834 for (i = 0; i < module_index; i++) {
3835 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3836 return -EINVAL;
3837 vram_module = (ATOM_VRAM_MODULE_V7 *)
3838 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3839 }
3840 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3841 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3842 } else
3843 return -EINVAL;
3844 break;
3845 default:
3846 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3847 return -EINVAL;
3848 }
3849 break;
3850 default:
3851 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3852 return -EINVAL;
3853 }
3854 return 0;
3855 }
3856 return -EINVAL;
3857 }
3858
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3859 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3860 bool gddr5, u8 module_index,
3861 struct atom_memory_clock_range_table *mclk_range_table)
3862 {
3863 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3864 u8 frev, crev, i;
3865 u16 data_offset, size;
3866 union vram_info *vram_info;
3867 u32 mem_timing_size = gddr5 ?
3868 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3869
3870 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3871
3872 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3873 &frev, &crev, &data_offset)) {
3874 vram_info = (union vram_info *)
3875 (rdev->mode_info.atom_context->bios + data_offset);
3876 switch (frev) {
3877 case 1:
3878 switch (crev) {
3879 case 3:
3880 DRM_ERROR("old table version %d, %d\n", frev, crev);
3881 return -EINVAL;
3882 case 4:
3883 /* r7xx, evergreen */
3884 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3885 ATOM_VRAM_MODULE_V4 *vram_module =
3886 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3887 ATOM_MEMORY_TIMING_FORMAT *format;
3888
3889 for (i = 0; i < module_index; i++) {
3890 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3891 return -EINVAL;
3892 vram_module = (ATOM_VRAM_MODULE_V4 *)
3893 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3894 }
3895 mclk_range_table->num_entries = (u8)
3896 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3897 mem_timing_size);
3898 format = &vram_module->asMemTiming[0];
3899 for (i = 0; i < mclk_range_table->num_entries; i++) {
3900 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3901 format = (ATOM_MEMORY_TIMING_FORMAT *)
3902 ((u8 *)format + mem_timing_size);
3903 }
3904 } else
3905 return -EINVAL;
3906 break;
3907 default:
3908 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3909 return -EINVAL;
3910 }
3911 break;
3912 case 2:
3913 DRM_ERROR("new table version %d, %d\n", frev, crev);
3914 return -EINVAL;
3915 default:
3916 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3917 return -EINVAL;
3918 }
3919 return 0;
3920 }
3921 return -EINVAL;
3922 }
3923
3924 #define MEM_ID_MASK 0xff000000
3925 #define MEM_ID_SHIFT 24
3926 #define CLOCK_RANGE_MASK 0x00ffffff
3927 #define CLOCK_RANGE_SHIFT 0
3928 #define LOW_NIBBLE_MASK 0xf
3929 #define DATA_EQU_PREV 0
3930 #define DATA_FROM_TABLE 4
3931
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3932 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3933 u8 module_index,
3934 struct atom_mc_reg_table *reg_table)
3935 {
3936 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3937 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3938 u32 i = 0, j;
3939 u16 data_offset, size;
3940 union vram_info *vram_info;
3941
3942 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3943
3944 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3945 &frev, &crev, &data_offset)) {
3946 vram_info = (union vram_info *)
3947 (rdev->mode_info.atom_context->bios + data_offset);
3948 switch (frev) {
3949 case 1:
3950 DRM_ERROR("old table version %d, %d\n", frev, crev);
3951 return -EINVAL;
3952 case 2:
3953 switch (crev) {
3954 case 1:
3955 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3956 ATOM_INIT_REG_BLOCK *reg_block =
3957 (ATOM_INIT_REG_BLOCK *)
3958 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3959 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3960 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3961 ((u8 *)reg_block + (2 * sizeof(u16)) +
3962 le16_to_cpu(reg_block->usRegIndexTblSize));
3963 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
3964 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3965 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3966 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3967 return -EINVAL;
3968 while (i < num_entries) {
3969 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3970 break;
3971 reg_table->mc_reg_address[i].s1 =
3972 (u16)(le16_to_cpu(format->usRegIndex));
3973 reg_table->mc_reg_address[i].pre_reg_data =
3974 (u8)(format->ucPreRegDataLength);
3975 i++;
3976 format = (ATOM_INIT_REG_INDEX_FORMAT *)
3977 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3978 }
3979 reg_table->last = i;
3980 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
3981 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3982 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
3983 >> MEM_ID_SHIFT);
3984 if (module_index == t_mem_id) {
3985 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3986 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
3987 >> CLOCK_RANGE_SHIFT);
3988 for (i = 0, j = 1; i < reg_table->last; i++) {
3989 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3990 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3991 (u32)le32_to_cpu(*((u32 *)reg_data + j));
3992 j++;
3993 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3994 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3995 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3996 }
3997 }
3998 num_ranges++;
3999 }
4000 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4001 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4002 }
4003 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4004 return -EINVAL;
4005 reg_table->num_entries = num_ranges;
4006 } else
4007 return -EINVAL;
4008 break;
4009 default:
4010 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4011 return -EINVAL;
4012 }
4013 break;
4014 default:
4015 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4016 return -EINVAL;
4017 }
4018 return 0;
4019 }
4020 return -EINVAL;
4021 }
4022
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4023 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4024 {
4025 struct radeon_device *rdev = dev->dev_private;
4026 uint32_t bios_2_scratch, bios_6_scratch;
4027
4028 if (rdev->family >= CHIP_R600) {
4029 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4030 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4031 } else {
4032 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4033 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4034 }
4035
4036 /* let the bios control the backlight */
4037 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4038
4039 /* tell the bios not to handle mode switching */
4040 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4041
4042 /* clear the vbios dpms state */
4043 if (ASIC_IS_DCE4(rdev))
4044 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4045
4046 if (rdev->family >= CHIP_R600) {
4047 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4048 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4049 } else {
4050 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4051 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4052 }
4053
4054 }
4055
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4056 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4057 {
4058 uint32_t scratch_reg;
4059 int i;
4060
4061 if (rdev->family >= CHIP_R600)
4062 scratch_reg = R600_BIOS_0_SCRATCH;
4063 else
4064 scratch_reg = RADEON_BIOS_0_SCRATCH;
4065
4066 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4067 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4068 }
4069
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4070 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4071 {
4072 uint32_t scratch_reg;
4073 int i;
4074
4075 if (rdev->family >= CHIP_R600)
4076 scratch_reg = R600_BIOS_0_SCRATCH;
4077 else
4078 scratch_reg = RADEON_BIOS_0_SCRATCH;
4079
4080 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4081 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4082 }
4083
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4084 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4085 {
4086 struct drm_device *dev = encoder->dev;
4087 struct radeon_device *rdev = dev->dev_private;
4088 uint32_t bios_6_scratch;
4089
4090 if (rdev->family >= CHIP_R600)
4091 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4092 else
4093 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4094
4095 if (lock) {
4096 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4097 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4098 } else {
4099 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4100 bios_6_scratch |= ATOM_S6_ACC_MODE;
4101 }
4102
4103 if (rdev->family >= CHIP_R600)
4104 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4105 else
4106 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4107 }
4108
4109 /* at some point we may want to break this out into individual functions */
4110 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4111 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4112 struct drm_encoder *encoder,
4113 bool connected)
4114 {
4115 struct drm_device *dev = connector->dev;
4116 struct radeon_device *rdev = dev->dev_private;
4117 struct radeon_connector *radeon_connector =
4118 to_radeon_connector(connector);
4119 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4120 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4121
4122 if (rdev->family >= CHIP_R600) {
4123 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4124 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4125 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4126 } else {
4127 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4128 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4129 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4130 }
4131
4132 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4133 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4134 if (connected) {
4135 DRM_DEBUG_KMS("TV1 connected\n");
4136 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4137 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4138 } else {
4139 DRM_DEBUG_KMS("TV1 disconnected\n");
4140 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4141 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4142 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4143 }
4144 }
4145 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4146 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4147 if (connected) {
4148 DRM_DEBUG_KMS("CV connected\n");
4149 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4150 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4151 } else {
4152 DRM_DEBUG_KMS("CV disconnected\n");
4153 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4154 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4155 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4156 }
4157 }
4158 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4159 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4160 if (connected) {
4161 DRM_DEBUG_KMS("LCD1 connected\n");
4162 bios_0_scratch |= ATOM_S0_LCD1;
4163 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4164 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4165 } else {
4166 DRM_DEBUG_KMS("LCD1 disconnected\n");
4167 bios_0_scratch &= ~ATOM_S0_LCD1;
4168 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4169 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4170 }
4171 }
4172 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4173 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4174 if (connected) {
4175 DRM_DEBUG_KMS("CRT1 connected\n");
4176 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4177 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4178 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4179 } else {
4180 DRM_DEBUG_KMS("CRT1 disconnected\n");
4181 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4182 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4183 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4184 }
4185 }
4186 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4187 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4188 if (connected) {
4189 DRM_DEBUG_KMS("CRT2 connected\n");
4190 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4191 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4192 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4193 } else {
4194 DRM_DEBUG_KMS("CRT2 disconnected\n");
4195 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4196 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4197 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4198 }
4199 }
4200 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4201 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4202 if (connected) {
4203 DRM_DEBUG_KMS("DFP1 connected\n");
4204 bios_0_scratch |= ATOM_S0_DFP1;
4205 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4206 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4207 } else {
4208 DRM_DEBUG_KMS("DFP1 disconnected\n");
4209 bios_0_scratch &= ~ATOM_S0_DFP1;
4210 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4211 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4212 }
4213 }
4214 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4215 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4216 if (connected) {
4217 DRM_DEBUG_KMS("DFP2 connected\n");
4218 bios_0_scratch |= ATOM_S0_DFP2;
4219 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4220 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4221 } else {
4222 DRM_DEBUG_KMS("DFP2 disconnected\n");
4223 bios_0_scratch &= ~ATOM_S0_DFP2;
4224 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4225 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4226 }
4227 }
4228 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4229 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4230 if (connected) {
4231 DRM_DEBUG_KMS("DFP3 connected\n");
4232 bios_0_scratch |= ATOM_S0_DFP3;
4233 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4234 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4235 } else {
4236 DRM_DEBUG_KMS("DFP3 disconnected\n");
4237 bios_0_scratch &= ~ATOM_S0_DFP3;
4238 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4239 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4240 }
4241 }
4242 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4243 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4244 if (connected) {
4245 DRM_DEBUG_KMS("DFP4 connected\n");
4246 bios_0_scratch |= ATOM_S0_DFP4;
4247 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4248 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4249 } else {
4250 DRM_DEBUG_KMS("DFP4 disconnected\n");
4251 bios_0_scratch &= ~ATOM_S0_DFP4;
4252 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4253 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4254 }
4255 }
4256 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4257 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4258 if (connected) {
4259 DRM_DEBUG_KMS("DFP5 connected\n");
4260 bios_0_scratch |= ATOM_S0_DFP5;
4261 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4262 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4263 } else {
4264 DRM_DEBUG_KMS("DFP5 disconnected\n");
4265 bios_0_scratch &= ~ATOM_S0_DFP5;
4266 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4267 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4268 }
4269 }
4270 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4271 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4272 if (connected) {
4273 DRM_DEBUG_KMS("DFP6 connected\n");
4274 bios_0_scratch |= ATOM_S0_DFP6;
4275 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4276 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4277 } else {
4278 DRM_DEBUG_KMS("DFP6 disconnected\n");
4279 bios_0_scratch &= ~ATOM_S0_DFP6;
4280 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4281 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4282 }
4283 }
4284
4285 if (rdev->family >= CHIP_R600) {
4286 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4287 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4288 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4289 } else {
4290 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4291 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4292 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4293 }
4294 }
4295
4296 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4297 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4298 {
4299 struct drm_device *dev = encoder->dev;
4300 struct radeon_device *rdev = dev->dev_private;
4301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4302 uint32_t bios_3_scratch;
4303
4304 if (ASIC_IS_DCE4(rdev))
4305 return;
4306
4307 if (rdev->family >= CHIP_R600)
4308 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4309 else
4310 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4311
4312 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4313 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4314 bios_3_scratch |= (crtc << 18);
4315 }
4316 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4317 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4318 bios_3_scratch |= (crtc << 24);
4319 }
4320 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4321 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4322 bios_3_scratch |= (crtc << 16);
4323 }
4324 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4325 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4326 bios_3_scratch |= (crtc << 20);
4327 }
4328 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4329 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4330 bios_3_scratch |= (crtc << 17);
4331 }
4332 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4333 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4334 bios_3_scratch |= (crtc << 19);
4335 }
4336 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4337 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4338 bios_3_scratch |= (crtc << 23);
4339 }
4340 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4341 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4342 bios_3_scratch |= (crtc << 25);
4343 }
4344
4345 if (rdev->family >= CHIP_R600)
4346 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4347 else
4348 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4349 }
4350
4351 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4352 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4353 {
4354 struct drm_device *dev = encoder->dev;
4355 struct radeon_device *rdev = dev->dev_private;
4356 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4357 uint32_t bios_2_scratch;
4358
4359 if (ASIC_IS_DCE4(rdev))
4360 return;
4361
4362 if (rdev->family >= CHIP_R600)
4363 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4364 else
4365 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4366
4367 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4368 if (on)
4369 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4370 else
4371 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4374 if (on)
4375 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4376 else
4377 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4378 }
4379 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4380 if (on)
4381 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4382 else
4383 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4384 }
4385 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4386 if (on)
4387 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4388 else
4389 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4390 }
4391 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4392 if (on)
4393 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4394 else
4395 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4396 }
4397 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4398 if (on)
4399 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4400 else
4401 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4402 }
4403 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4404 if (on)
4405 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4406 else
4407 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4408 }
4409 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4410 if (on)
4411 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4412 else
4413 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4414 }
4415 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4416 if (on)
4417 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4418 else
4419 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4420 }
4421 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4422 if (on)
4423 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4424 else
4425 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4426 }
4427
4428 if (rdev->family >= CHIP_R600)
4429 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4430 else
4431 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4432 }
4433