| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 301 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
304 if ((rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
342 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_set_timing() local
379 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
380 val &= ~(1 << mclk->clken_bit); in mmc_clk_set_timing()
381 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
383 val = readl_relaxed(mclk->sam_reg); in mmc_clk_set_timing()
384 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
385 writel_relaxed(val, mclk->sam_reg); in mmc_clk_set_timing()
387 val = readl_relaxed(mclk->drv_reg); in mmc_clk_set_timing()
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| /drivers/gpu/drm/radeon/ |
| D | btc_dpm.c | 1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1255 (btc_blacklist_clocks[i].mclk == *mclk)) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1284 (pl->mclk + in btc_adjust_clock_combinations()
1288 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
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| D | rv730_dpm.c | 121 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
186 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_mclk_value()
187 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
188 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_mclk_value()
191 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_mclk_value()
192 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
193 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
297 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
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| D | rv740_dpm.c | 189 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
272 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
273 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
274 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
279 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
280 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv740_populate_mclk_value()
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| D | rv770_dpm.c | 386 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
471 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
472 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
473 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
474 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
476 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
477 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
590 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in rv770_populate_mvdd_value() argument
601 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
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| D | cypress_dpm.c | 423 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings() argument
430 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
432 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); in cypress_get_strobe_mode_settings()
475 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value() argument
597 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
598 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
599 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
600 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
602 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
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| D | ni_dpm.c | 791 u32 mclk; in ni_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].mclk); in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
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| D | si_dpm.c | 2941 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3035 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3036 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3060 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3061 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3064 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3065 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3068 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3069 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3080 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
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| D | ci_dpm.c | 761 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
790 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
791 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
800 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
803 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
810 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
811 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
815 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
821 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) in ci_apply_state_adjust_rules()
822 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; in ci_apply_state_adjust_rules()
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| D | rv770_dpm.h | 143 u32 mclk; member
184 LPRV7XX_SMC_MCLK_VALUE mclk);
205 RV7XX_SMC_MCLK_VALUE *mclk);
219 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
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| /drivers/media/dvb-frontends/ |
| D | stv0900_sw.c | 56 max_carrier /= intp->mclk / 1000; in stv0900_check_signal_presence()
83 max_carrier /= intp->mclk / 1000; in stv0900_get_sw_loop_params()
89 freq_inc /= intp->mclk >> 10; in stv0900_get_sw_loop_params()
149 max_carrier /= intp->mclk / 1000; in stv0900_search_carr_sw_loop()
309 u32 mclk, in stv0900_get_symbol_rate() argument
324 intval1 = (mclk) >> 16; in stv0900_get_symbol_rate()
327 rem1 = (mclk) % 0x10000; in stv0900_get_symbol_rate()
337 u32 mclk, u32 srate, in stv0900_set_symbol_rate() argument
342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, in stv0900_set_symbol_rate()
347 symb /= (mclk >> 12); in stv0900_set_symbol_rate()
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| D | stv6110.c | 42 u32 mclk; member
225 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3); in stv6110_init()
254 freq = divider * (priv->mclk / 1000); in stv6110_get_frequency()
273 frequency, priv->mclk); in stv6110_set_frequency()
278 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3); in stv6110_set_frequency()
314 p_calc = (priv->mclk / 100000); in stv6110_set_frequency()
319 p_calc_opt = (priv->mclk / 100000); in stv6110_set_frequency()
323 ref = priv->mclk / ((1 << (r_div_opt + 1)) * (1 << (p + 1))); in stv6110_set_frequency()
353 vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1)))); in stv6110_set_frequency()
441 priv->mclk = config->mclk; in stv6110_attach()
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| D | m88rs2000.c | 116 u32 mclk; in m88rs2000_get_mclk() local
126 mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28; in m88rs2000_get_mclk()
128 return mclk; in m88rs2000_get_mclk()
134 u32 mclk; in m88rs2000_set_carrieroffset() local
139 mclk = m88rs2000_get_mclk(fe); in m88rs2000_set_carrieroffset()
140 if (!mclk) in m88rs2000_set_carrieroffset()
143 tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk; in m88rs2000_set_carrieroffset()
164 u32 mclk; in m88rs2000_set_symbolrate() local
170 mclk = m88rs2000_get_mclk(fe); in m88rs2000_set_symbolrate()
171 if (!mclk) in m88rs2000_set_symbolrate()
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| D | stv090x.c | 871 sym /= (state->internal->mclk >> 12); in stv090x_set_srate()
874 sym /= (state->internal->mclk >> 10); in stv090x_set_srate()
877 sym /= (state->internal->mclk >> 7); in stv090x_set_srate()
898 sym /= (state->internal->mclk >> 12); in stv090x_set_max_srate()
901 sym /= (state->internal->mclk >> 10); in stv090x_set_max_srate()
904 sym /= (state->internal->mclk >> 7); in stv090x_set_max_srate()
932 sym /= (state->internal->mclk >> 12); in stv090x_set_min_srate()
935 sym /= (state->internal->mclk >> 10); in stv090x_set_min_srate()
938 sym /= (state->internal->mclk >> 7); in stv090x_set_min_srate()
1468 freq_abs /= (state->internal->mclk / 1000); in stv090x_start_search()
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| /drivers/gpu/drm/nouveau/core/subdev/fb/ |
| D | ramnva3.c | 81 struct nva3_clock_info mclk; in nva3_ram_calc() local
132 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); in nva3_ram_calc()
153 if (mclk.pll) { in nva3_ram_calc()
155 ram_wr32(fuc, 0x004004, mclk.pll); in nva3_ram_calc()
165 if (mclk.clk) in nva3_ram_calc()
166 ssel |= mclk.clk; in nva3_ram_calc()
193 if (!(ctrl & 0x00000008) && mclk.pll) { in nva3_ram_calc()
198 ram_wr32(fuc, 0x004004, mclk.pll); in nva3_ram_calc()
204 if (!mclk.pll) { in nva3_ram_calc()
205 ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk); in nva3_ram_calc()
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| /drivers/spi/ |
| D | spi-sun6i.c | 85 struct clk *mclk; member
220 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
222 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
223 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
322 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
340 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
353 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
412 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
413 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
415 ret = PTR_ERR(sspi->mclk); in sun6i_spi_probe()
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| D | spi-sun4i.c | 80 struct clk *mclk; member
235 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
237 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun4i_spi_transfer_one()
238 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
339 ret = clk_prepare_enable(sspi->mclk); in sun4i_spi_runtime_resume()
361 clk_disable_unprepare(sspi->mclk); in sun4i_spi_runtime_suspend()
420 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun4i_spi_probe()
421 if (IS_ERR(sspi->mclk)) { in sun4i_spi_probe()
423 ret = PTR_ERR(sspi->mclk); in sun4i_spi_probe()
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| /drivers/mfd/ |
| D | sm501.c | 392 unsigned long mclk; member
408 unsigned long mclk, in sm501_calc_clock() argument
423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; in sm501_calc_clock()
431 clock->mclk = mclk; in sm501_calc_clock()
453 unsigned long mclk; in sm501_calc_pll() local
464 mclk = (24000000UL * m / n) >> k; in sm501_calc_pll()
467 mclk, &best_diff)) { in sm501_calc_pll()
477 return clock->mclk / (clock->divider << clock->shift); in sm501_calc_pll()
491 unsigned long mclk; in sm501_select_clock() local
495 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { in sm501_select_clock()
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| /drivers/staging/iio/frequency/ |
| D | ad9832.c | 25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9832_calc_freqreg() argument
29 do_div(freqreg, mclk); in ad9832_calc_freqreg()
38 if (fout > (st->mclk / 2)) in ad9832_write_frequency()
41 regval = ad9832_calc_freqreg(st->mclk, fout); in ad9832_write_frequency()
230 st->mclk = pdata->mclk; in ad9832_probe()
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| D | ad9834.h | 56 unsigned int mclk; member
92 unsigned int mclk; member
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| D | ad9834.c | 28 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9834_calc_freqreg() argument
32 do_div(freqreg, mclk); in ad9834_calc_freqreg()
41 if (fout > (st->mclk / 2)) in ad9834_write_frequency()
44 regval = ad9834_calc_freqreg(st->mclk, fout); in ad9834_write_frequency()
345 st->mclk = pdata->mclk; in ad9834_probe()
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| D | ad9832.h | 80 unsigned long mclk; member
117 unsigned long mclk; member
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| /drivers/clk/ |
| D | clk-u300.c | 952 struct clk_mclk *mclk = to_mclk(hw); in mclk_clk_prepare() local
956 if (!mclk->is_mspro) { in mclk_clk_prepare()
1118 struct clk_mclk *mclk; in mclk_clk_register() local
1121 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL); in mclk_clk_register()
1122 if (!mclk) { in mclk_clk_register()
1132 mclk->hw.init = &init; in mclk_clk_register()
1133 mclk->is_mspro = is_mspro; in mclk_clk_register()
1135 clk = clk_register(dev, &mclk->hw); in mclk_clk_register()
1137 kfree(mclk); in mclk_clk_register()
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| /drivers/mmc/host/ |
| D | mmci.c | 324 host->cclk = host->mclk; in mmci_set_clkreg()
325 } else if (desired >= host->mclk) { in mmci_set_clkreg()
329 host->cclk = host->mclk; in mmci_set_clkreg()
337 clk = DIV_ROUND_UP(host->mclk, desired) - 2; in mmci_set_clkreg()
340 host->cclk = host->mclk / (clk + 2); in mmci_set_clkreg()
346 clk = host->mclk / (2 * desired) - 1; in mmci_set_clkreg()
349 host->cclk = host->mclk / (2 * (clk + 1)); in mmci_set_clkreg()
830 (host->size <= 8 && host->mclk > 50000000))) in mmci_start_data()
1404 host->mclk = clk_get_rate(host->clk); in mmci_set_ios()
1562 host->mclk = clk_get_rate(host->clk); in mmci_probe()
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| /drivers/media/platform/soc_camera/ |
| D | pxa_camera.c | 216 unsigned long mclk; member
852 unsigned long mclk = pcdev->mclk; in mclk_get_divisor() local
861 if (mclk > lcdclk / 4) { in mclk_get_divisor()
862 mclk = lcdclk / 4; in mclk_get_divisor()
863 dev_warn(dev, "Limiting master clock to %lu\n", mclk); in mclk_get_divisor()
867 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; in mclk_get_divisor()
871 pcdev->mclk = lcdclk / (2 * (div + 1)); in mclk_get_divisor()
874 lcdclk, mclk, div); in mclk_get_divisor()
910 recalculate_fifo_timeout(pcdev, pcdev->mclk); in pxa_camera_activate()
1346 .master_clock = pcdev->mclk, in pxa_camera_set_crop()
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