/drivers/gpu/drm/msm/mdp/mdp4/ |
D | mdp4_kms.c | 27 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_hw_init() local 28 struct drm_device *dev = mdp4_kms->dev; in mdp4_hw_init() 35 mdp4_enable(mdp4_kms); in mdp4_hw_init() 36 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); in mdp4_hw_init() 37 mdp4_disable(mdp4_kms); in mdp4_hw_init() 51 mdp4_kms->rev = minor; in mdp4_hw_init() 53 if (mdp4_kms->dsi_pll_vdda) { in mdp4_hw_init() 54 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) { in mdp4_hw_init() 55 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda, in mdp4_hw_init() 65 if (mdp4_kms->dsi_pll_vddio) { in mdp4_hw_init() [all …]
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D | mdp4_lcdc_encoder.c | 35 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms() 111 struct mdp4_kms *mdp4_kms = get_kms(encoder); in setup_phy() local 129 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy() 134 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy() 138 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), in setup_phy() 143 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), in setup_phy() 147 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), in setup_phy() 152 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), in setup_phy() 156 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), in setup_phy() 161 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), in setup_phy() [all …]
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D | mdp4_crtc.c | 82 static struct mdp4_kms *get_kms(struct drm_crtc *crtc) in get_kms() 99 struct mdp4_kms *mdp4_kms = get_kms(crtc); in crtc_flush() local 113 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush() 210 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); in unref_cursor_worker() local 212 msm_gem_put_iova(val, mdp4_kms->id); in unref_cursor_worker() 230 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_dpms() local 237 mdp4_enable(mdp4_kms); in mdp4_crtc_dpms() 238 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); in mdp4_crtc_dpms() 240 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); in mdp4_crtc_dpms() 241 mdp4_disable(mdp4_kms); in mdp4_crtc_dpms() [all …]
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D | mdp4_irq.c | 34 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_preinstall() local 35 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall() 41 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq_postinstall() local 42 struct mdp_irq *error_handler = &mdp4_kms->error_handler; in mdp4_irq_postinstall() 55 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_uninstall() local 56 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_uninstall() 62 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq() local 63 struct drm_device *dev = mdp4_kms->dev; in mdp4_irq() 68 status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS); in mdp4_irq() 69 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); in mdp4_irq()
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D | mdp4_dtv_encoder.c | 35 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms() 101 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_dpms() local 128 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); in mdp4_dtv_encoder_dpms() 130 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); in mdp4_dtv_encoder_dpms() 140 mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); in mdp4_dtv_encoder_dpms() 164 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_mode_set() local 201 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set() 204 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set() 205 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set() 206 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set() [all …]
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D | mdp4_plane.c | 34 static struct mdp4_kms *get_kms(struct drm_plane *plane) in get_kms() 105 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_set_scanout() local 109 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), in mdp4_plane_set_scanout() 113 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), in mdp4_plane_set_scanout() 117 msm_gem_get_iova(msm_framebuffer_bo(fb, 0), mdp4_kms->id, &iova); in mdp4_plane_set_scanout() 118 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), iova); in mdp4_plane_set_scanout() 133 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_mode_set() local 160 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe), in mdp4_plane_mode_set() 164 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe), in mdp4_plane_mode_set() 168 mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe), in mdp4_plane_mode_set() [all …]
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D | mdp4_lvds_pll.c | 30 static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll) in get_kms() 71 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_enable() local 80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable() 83 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable() 85 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable() 88 while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED)) in mpd4_lvds_pll_enable() 97 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_disable() local 101 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable() 102 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
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D | mdp4_kms.h | 28 struct mdp4_kms { struct 62 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) argument 70 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() argument 72 msm_writel(data, mdp4_kms->mmio + reg); in mdp4_write() 75 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) in mdp4_read() argument 77 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read() 174 int mdp4_disable(struct mdp4_kms *mdp4_kms); 175 int mdp4_enable(struct mdp4_kms *mdp4_kms);
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/drivers/gpu/drm/msm/ |
D | Makefile | 25 mdp/mdp4/mdp4_kms.o \
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