1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __MDP4_KMS_H__
19 #define __MDP4_KMS_H__
20
21 #include "msm_drv.h"
22 #include "msm_kms.h"
23 #include "mdp/mdp_kms.h"
24 #include "mdp4.xml.h"
25
26 #include "drm_panel.h"
27
28 struct mdp4_kms {
29 struct mdp_kms base;
30
31 struct drm_device *dev;
32
33 int rev;
34
35 /* Shadow value for MDP4_LAYERMIXER_IN_CFG.. since setup for all
36 * crtcs/encoders is in one shared register, we need to update it
37 * via read/modify/write. But to avoid getting confused by power-
38 * on-default values after resume, use this shadow value instead:
39 */
40 uint32_t mixer_cfg;
41
42 /* mapper-id used to request GEM buffer mapped for scanout: */
43 int id;
44
45 void __iomem *mmio;
46
47 struct regulator *dsi_pll_vdda;
48 struct regulator *dsi_pll_vddio;
49 struct regulator *vdd;
50
51 struct clk *clk;
52 struct clk *pclk;
53 struct clk *lut_clk;
54 struct clk *axi_clk;
55
56 struct mdp_irq error_handler;
57
58 /* empty/blank cursor bo to use when cursor is "disabled" */
59 struct drm_gem_object *blank_cursor_bo;
60 uint32_t blank_cursor_iova;
61 };
62 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
63
64 /* platform config data (ie. from DT, or pdata) */
65 struct mdp4_platform_config {
66 struct iommu_domain *iommu;
67 uint32_t max_clk;
68 };
69
mdp4_write(struct mdp4_kms * mdp4_kms,u32 reg,u32 data)70 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
71 {
72 msm_writel(data, mdp4_kms->mmio + reg);
73 }
74
mdp4_read(struct mdp4_kms * mdp4_kms,u32 reg)75 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
76 {
77 return msm_readl(mdp4_kms->mmio + reg);
78 }
79
pipe2flush(enum mdp4_pipe pipe)80 static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
81 {
82 switch (pipe) {
83 case VG1: return MDP4_OVERLAY_FLUSH_VG1;
84 case VG2: return MDP4_OVERLAY_FLUSH_VG2;
85 case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
86 case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
87 default: return 0;
88 }
89 }
90
ovlp2flush(int ovlp)91 static inline uint32_t ovlp2flush(int ovlp)
92 {
93 switch (ovlp) {
94 case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
95 case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
96 default: return 0;
97 }
98 }
99
dma2irq(enum mdp4_dma dma)100 static inline uint32_t dma2irq(enum mdp4_dma dma)
101 {
102 switch (dma) {
103 case DMA_P: return MDP4_IRQ_DMA_P_DONE;
104 case DMA_S: return MDP4_IRQ_DMA_S_DONE;
105 case DMA_E: return MDP4_IRQ_DMA_E_DONE;
106 default: return 0;
107 }
108 }
109
dma2err(enum mdp4_dma dma)110 static inline uint32_t dma2err(enum mdp4_dma dma)
111 {
112 switch (dma) {
113 case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
114 case DMA_S: return 0; // ???
115 case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
116 default: return 0;
117 }
118 }
119
mixercfg(uint32_t mixer_cfg,int mixer,enum mdp4_pipe pipe,enum mdp_mixer_stage_id stage)120 static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
121 enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
122 {
123 switch (pipe) {
124 case VG1:
125 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
126 MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
127 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
128 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
129 break;
130 case VG2:
131 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
132 MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
133 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
134 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
135 break;
136 case RGB1:
137 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
138 MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
139 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
140 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
141 break;
142 case RGB2:
143 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
144 MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
145 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
146 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
147 break;
148 case RGB3:
149 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
150 MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
151 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
152 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
153 break;
154 case VG3:
155 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
156 MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
157 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
158 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
159 break;
160 case VG4:
161 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
162 MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
163 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
164 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
165 break;
166 default:
167 WARN_ON("invalid pipe");
168 break;
169 }
170
171 return mixer_cfg;
172 }
173
174 int mdp4_disable(struct mdp4_kms *mdp4_kms);
175 int mdp4_enable(struct mdp4_kms *mdp4_kms);
176
177 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
178 void mdp4_irq_preinstall(struct msm_kms *kms);
179 int mdp4_irq_postinstall(struct msm_kms *kms);
180 void mdp4_irq_uninstall(struct msm_kms *kms);
181 irqreturn_t mdp4_irq(struct msm_kms *kms);
182 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
183 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
184
185 static inline
mdp4_get_formats(enum mdp4_pipe pipe_id,uint32_t * pixel_formats,uint32_t max_formats)186 uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
187 uint32_t max_formats)
188 {
189 /* TODO when we have YUV, we need to filter supported formats
190 * based on pipe_id..
191 */
192 return mdp_get_formats(pixel_formats, max_formats);
193 }
194
195 void mdp4_plane_install_properties(struct drm_plane *plane,
196 struct drm_mode_object *obj);
197 void mdp4_plane_set_scanout(struct drm_plane *plane,
198 struct drm_framebuffer *fb);
199 int mdp4_plane_mode_set(struct drm_plane *plane,
200 struct drm_crtc *crtc, struct drm_framebuffer *fb,
201 int crtc_x, int crtc_y,
202 unsigned int crtc_w, unsigned int crtc_h,
203 uint32_t src_x, uint32_t src_y,
204 uint32_t src_w, uint32_t src_h);
205 enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
206 struct drm_plane *mdp4_plane_init(struct drm_device *dev,
207 enum mdp4_pipe pipe_id, bool private_plane);
208
209 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
210 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
211 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
212 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
213 void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
214 void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
215 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
216 struct drm_plane *plane, int id, int ovlp_id,
217 enum mdp4_dma dma_id);
218
219 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
220 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
221
222 long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
223 struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
224 struct drm_panel *panel);
225
226 struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
227 struct drm_panel *panel, struct drm_encoder *encoder);
228
229 #ifdef CONFIG_COMMON_CLK
230 struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
231 #else
mpd4_lvds_pll_init(struct drm_device * dev)232 static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
233 {
234 return ERR_PTR(-ENODEV);
235 }
236 #endif
237
238 #ifdef CONFIG_MSM_BUS_SCALING
match_dev_name(struct device * dev,void * data)239 static inline int match_dev_name(struct device *dev, void *data)
240 {
241 return !strcmp(dev_name(dev), data);
242 }
243 /* bus scaling data is associated with extra pointless platform devices,
244 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
245 * to find their pdata to make the bus-scaling stuff work.
246 */
mdp4_find_pdata(const char * devname)247 static inline void *mdp4_find_pdata(const char *devname)
248 {
249 struct device *dev;
250 dev = bus_find_device(&platform_bus_type, NULL,
251 (void *)devname, match_dev_name);
252 return dev ? dev->platform_data : NULL;
253 }
254 #endif
255
256 #endif /* __MDP4_KMS_H__ */
257