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Searched refs:mtr (Results 1 – 5 of 5) sorted by relevance

/drivers/edac/
Di7300_edac.c107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ member
174 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) argument
175 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) argument
176 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
177 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) argument
178 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) argument
179 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
181 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
182 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
183 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument
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Di5400_edac.c285 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) argument
286 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) argument
287 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) argument
288 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
289 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument
290 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) argument
291 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument
292 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
293 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
294 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
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Di5000_edac.c279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) argument
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) argument
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) argument
282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) argument
284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument
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Dsb_edac.c189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) argument
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) argument
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) argument
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) argument
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) argument
515 static inline int numrank(enum type type, u32 mtr) in numrank() argument
517 int ranks = (1 << RANK_CNT_BITS(mtr)); in numrank()
525 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); in numrank()
532 static inline int numrow(u32 mtr) in numrow() argument
534 int rows = (RANK_WIDTH_BITS(mtr) + 12); in numrow()
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Di5100_edac.c344 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; member
671 if (!priv->mtr[chan][chan_rank].present) in i5100_npages()
676 priv->mtr[chan][chan_rank].numcol + in i5100_npages()
677 priv->mtr[chan][chan_rank].numrow + in i5100_npages()
678 priv->mtr[chan][chan_rank].numbank; in i5100_npages()
702 priv->mtr[i][j].present = i5100_mtr_present(w); in i5100_init_mtr()
703 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); in i5100_init_mtr()
704 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); in i5100_init_mtr()
705 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); in i5100_init_mtr()
706 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); in i5100_init_mtr()
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