1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
11 */
12
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
25 #include <asm/mce.h>
26
27 #include "edac_core.h"
28
29 /* Static vars */
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
32 static int probed;
33
34 /*
35 * Alter this version for the module when modifications are made
36 */
37 #define SBRIDGE_REVISION " Ver: 1.1.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
39
40 /*
41 * Debug macros
42 */
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49 /*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59 };
60
61 static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66 };
67
68 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
69 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
70 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
71 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
72 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
73
get_dram_attr(u32 reg)74 static char *get_dram_attr(u32 reg)
75 {
76 switch(DRAM_ATTR(reg)) {
77 case 0:
78 return "DRAM";
79 case 1:
80 return "MMCFG";
81 case 2:
82 return "NXM";
83 default:
84 return "unknown";
85 }
86 }
87
88 static const u32 sbridge_interleave_list[] = {
89 0x84, 0x8c, 0x94, 0x9c, 0xa4,
90 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
91 };
92
93 static const u32 ibridge_interleave_list[] = {
94 0x64, 0x6c, 0x74, 0x7c, 0x84,
95 0x8c, 0x94, 0x9c, 0xa4, 0xac,
96 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
97 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
98 };
99
100 struct interleave_pkg {
101 unsigned char start;
102 unsigned char end;
103 };
104
105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
106 { 0, 2 },
107 { 3, 5 },
108 { 8, 10 },
109 { 11, 13 },
110 { 16, 18 },
111 { 19, 21 },
112 { 24, 26 },
113 { 27, 29 },
114 };
115
116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
117 { 0, 3 },
118 { 4, 7 },
119 { 8, 11 },
120 { 12, 15 },
121 { 16, 19 },
122 { 20, 23 },
123 { 24, 27 },
124 { 28, 31 },
125 };
126
sad_pkg(const struct interleave_pkg * table,u32 reg,int interleave)127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
128 int interleave)
129 {
130 return GET_BITFIELD(reg, table[interleave].start,
131 table[interleave].end);
132 }
133
134 /* Devices 12 Function 7 */
135
136 #define TOLM 0x80
137 #define TOHM 0x84
138 #define HASWELL_TOLM 0xd0
139 #define HASWELL_TOHM_0 0xd4
140 #define HASWELL_TOHM_1 0xd8
141
142 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
143 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
144
145 /* Device 13 Function 6 */
146
147 #define SAD_TARGET 0xf0
148
149 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
150
151 #define SAD_CONTROL 0xf4
152
153 /* Device 14 function 0 */
154
155 static const u32 tad_dram_rule[] = {
156 0x40, 0x44, 0x48, 0x4c,
157 0x50, 0x54, 0x58, 0x5c,
158 0x60, 0x64, 0x68, 0x6c,
159 };
160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
161
162 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
163 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
164 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
165 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
166 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
167 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
168 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
169
170 /* Device 15, function 0 */
171
172 #define MCMTR 0x7c
173
174 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
175 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
176 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
177
178 /* Device 15, function 1 */
179
180 #define RASENABLES 0xac
181 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
182
183 /* Device 15, functions 2-5 */
184
185 static const int mtr_regs[] = {
186 0x80, 0x84, 0x88,
187 };
188
189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
194
195 static const u32 tad_ch_nilv_offset[] = {
196 0x90, 0x94, 0x98, 0x9c,
197 0xa0, 0xa4, 0xa8, 0xac,
198 0xb0, 0xb4, 0xb8, 0xbc,
199 };
200 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
201 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
202
203 static const u32 rir_way_limit[] = {
204 0x108, 0x10c, 0x110, 0x114, 0x118,
205 };
206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
207
208 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
209 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
210
211 #define MAX_RIR_WAY 8
212
213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
214 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
215 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
216 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
217 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
218 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
219 };
220
221 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
222 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
223
224 /* Device 16, functions 2-7 */
225
226 /*
227 * FIXME: Implement the error count reads directly
228 */
229
230 static const u32 correrrcnt[] = {
231 0x104, 0x108, 0x10c, 0x110,
232 };
233
234 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
235 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
236 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
237 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
238
239 static const u32 correrrthrsld[] = {
240 0x11c, 0x120, 0x124, 0x128,
241 };
242
243 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
244 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
245
246
247 /* Device 17, function 0 */
248
249 #define SB_RANK_CFG_A 0x0328
250
251 #define IB_RANK_CFG_A 0x0320
252
253 /*
254 * sbridge structs
255 */
256
257 #define NUM_CHANNELS 4
258 #define MAX_DIMMS 3 /* Max DIMMS per channel */
259 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
260
261 enum type {
262 SANDY_BRIDGE,
263 IVY_BRIDGE,
264 HASWELL,
265 };
266
267 struct sbridge_pvt;
268 struct sbridge_info {
269 enum type type;
270 u32 mcmtr;
271 u32 rankcfgr;
272 u64 (*get_tolm)(struct sbridge_pvt *pvt);
273 u64 (*get_tohm)(struct sbridge_pvt *pvt);
274 u64 (*rir_limit)(u32 reg);
275 const u32 *dram_rule;
276 const u32 *interleave_list;
277 const struct interleave_pkg *interleave_pkg;
278 u8 max_sad;
279 u8 max_interleave;
280 u8 (*get_node_id)(struct sbridge_pvt *pvt);
281 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
282 struct pci_dev *pci_vtd;
283 };
284
285 struct sbridge_channel {
286 u32 ranks;
287 u32 dimms;
288 };
289
290 struct pci_id_descr {
291 int dev_id;
292 int optional;
293 };
294
295 struct pci_id_table {
296 const struct pci_id_descr *descr;
297 int n_devs;
298 };
299
300 struct sbridge_dev {
301 struct list_head list;
302 u8 bus, mc;
303 u8 node_id, source_id;
304 struct pci_dev **pdev;
305 int n_devs;
306 struct mem_ctl_info *mci;
307 };
308
309 struct sbridge_pvt {
310 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
311 struct pci_dev *pci_sad0, *pci_sad1;
312 struct pci_dev *pci_ha0, *pci_ha1;
313 struct pci_dev *pci_br0, *pci_br1;
314 struct pci_dev *pci_ha1_ta;
315 struct pci_dev *pci_tad[NUM_CHANNELS];
316
317 struct sbridge_dev *sbridge_dev;
318
319 struct sbridge_info info;
320 struct sbridge_channel channel[NUM_CHANNELS];
321
322 /* Memory type detection */
323 bool is_mirrored, is_lockstep, is_close_pg;
324
325 /* Fifo double buffers */
326 struct mce mce_entry[MCE_LOG_LEN];
327 struct mce mce_outentry[MCE_LOG_LEN];
328
329 /* Fifo in/out counters */
330 unsigned mce_in, mce_out;
331
332 /* Count indicator to show errors not got */
333 unsigned mce_overrun;
334
335 /* Memory description */
336 u64 tolm, tohm;
337 };
338
339 #define PCI_DESCR(device_id, opt) \
340 .dev_id = (device_id), \
341 .optional = opt
342
343 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
344 /* Processor Home Agent */
345 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
346
347 /* Memory controller */
348 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
349 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
350 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
351 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
352 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
353 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
354 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
355
356 /* System Address Decoder */
357 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
358 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
359
360 /* Broadcast Registers */
361 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
362 };
363
364 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
365 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
366 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
367 {0,} /* 0 terminated list. */
368 };
369
370 /* This changes depending if 1HA or 2HA:
371 * 1HA:
372 * 0x0eb8 (17.0) is DDRIO0
373 * 2HA:
374 * 0x0ebc (17.4) is DDRIO0
375 */
376 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
377 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
378
379 /* pci ids */
380 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
381 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
382 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
383 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
384 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
395
396 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
397 /* Processor Home Agent */
398 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
399
400 /* Memory controller */
401 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
402 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
403 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
404 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
407
408 /* System Address Decoder */
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
410
411 /* Broadcast Registers */
412 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
414
415 /* Optional, mode 2HA */
416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
417 #if 0
418 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
420 #endif
421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
423
424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
425 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
426 };
427
428 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
429 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
430 {0,} /* 0 terminated list. */
431 };
432
433 /* Haswell support */
434 /* EN processor:
435 * - 1 IMC
436 * - 3 DDR3 channels, 2 DPC per channel
437 * EP processor:
438 * - 1 or 2 IMC
439 * - 4 DDR4 channels, 3 DPC per channel
440 * EP 4S processor:
441 * - 2 IMC
442 * - 4 DDR4 channels, 3 DPC per channel
443 * EX processor:
444 * - 2 IMC
445 * - each IMC interfaces with a SMI 2 channel
446 * - each SMI channel interfaces with a scalable memory buffer
447 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
448 */
449 #define HASWELL_DDRCRCLKCONTROLS 0xa10
450 #define HASWELL_HASYSDEFEATURE2 0x84
451 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
452 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
453 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
454 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
455 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
456 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
457 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
458 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
459 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
469 static const struct pci_id_descr pci_dev_descr_haswell[] = {
470 /* first item must be the HA */
471 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
472
473 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
474 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
475
476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
477
478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
479 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
480 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
484
485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
486
487 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
493 };
494
495 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
496 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
497 {0,} /* 0 terminated list. */
498 };
499
500 /*
501 * pci_device_id table for which devices we are looking for
502 */
503 static const struct pci_device_id sbridge_pci_tbl[] = {
504 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
505 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
506 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
507 {0,} /* 0 terminated list. */
508 };
509
510
511 /****************************************************************************
512 Ancillary status routines
513 ****************************************************************************/
514
numrank(enum type type,u32 mtr)515 static inline int numrank(enum type type, u32 mtr)
516 {
517 int ranks = (1 << RANK_CNT_BITS(mtr));
518 int max = 4;
519
520 if (type == HASWELL)
521 max = 8;
522
523 if (ranks > max) {
524 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
525 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
526 return -EINVAL;
527 }
528
529 return ranks;
530 }
531
numrow(u32 mtr)532 static inline int numrow(u32 mtr)
533 {
534 int rows = (RANK_WIDTH_BITS(mtr) + 12);
535
536 if (rows < 13 || rows > 18) {
537 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
538 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
539 return -EINVAL;
540 }
541
542 return 1 << rows;
543 }
544
numcol(u32 mtr)545 static inline int numcol(u32 mtr)
546 {
547 int cols = (COL_WIDTH_BITS(mtr) + 10);
548
549 if (cols > 12) {
550 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
551 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
552 return -EINVAL;
553 }
554
555 return 1 << cols;
556 }
557
get_sbridge_dev(u8 bus)558 static struct sbridge_dev *get_sbridge_dev(u8 bus)
559 {
560 struct sbridge_dev *sbridge_dev;
561
562 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
563 if (sbridge_dev->bus == bus)
564 return sbridge_dev;
565 }
566
567 return NULL;
568 }
569
alloc_sbridge_dev(u8 bus,const struct pci_id_table * table)570 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
571 const struct pci_id_table *table)
572 {
573 struct sbridge_dev *sbridge_dev;
574
575 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
576 if (!sbridge_dev)
577 return NULL;
578
579 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
580 GFP_KERNEL);
581 if (!sbridge_dev->pdev) {
582 kfree(sbridge_dev);
583 return NULL;
584 }
585
586 sbridge_dev->bus = bus;
587 sbridge_dev->n_devs = table->n_devs;
588 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
589
590 return sbridge_dev;
591 }
592
free_sbridge_dev(struct sbridge_dev * sbridge_dev)593 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
594 {
595 list_del(&sbridge_dev->list);
596 kfree(sbridge_dev->pdev);
597 kfree(sbridge_dev);
598 }
599
sbridge_get_tolm(struct sbridge_pvt * pvt)600 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
601 {
602 u32 reg;
603
604 /* Address range is 32:28 */
605 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
606 return GET_TOLM(reg);
607 }
608
sbridge_get_tohm(struct sbridge_pvt * pvt)609 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
610 {
611 u32 reg;
612
613 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
614 return GET_TOHM(reg);
615 }
616
ibridge_get_tolm(struct sbridge_pvt * pvt)617 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
618 {
619 u32 reg;
620
621 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
622
623 return GET_TOLM(reg);
624 }
625
ibridge_get_tohm(struct sbridge_pvt * pvt)626 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
627 {
628 u32 reg;
629
630 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
631
632 return GET_TOHM(reg);
633 }
634
rir_limit(u32 reg)635 static u64 rir_limit(u32 reg)
636 {
637 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
638 }
639
get_memory_type(struct sbridge_pvt * pvt)640 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
641 {
642 u32 reg;
643 enum mem_type mtype;
644
645 if (pvt->pci_ddrio) {
646 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
647 ®);
648 if (GET_BITFIELD(reg, 11, 11))
649 /* FIXME: Can also be LRDIMM */
650 mtype = MEM_RDDR3;
651 else
652 mtype = MEM_DDR3;
653 } else
654 mtype = MEM_UNKNOWN;
655
656 return mtype;
657 }
658
haswell_get_memory_type(struct sbridge_pvt * pvt)659 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
660 {
661 u32 reg;
662 bool registered = false;
663 enum mem_type mtype = MEM_UNKNOWN;
664
665 if (!pvt->pci_ddrio)
666 goto out;
667
668 pci_read_config_dword(pvt->pci_ddrio,
669 HASWELL_DDRCRCLKCONTROLS, ®);
670 /* Is_Rdimm */
671 if (GET_BITFIELD(reg, 16, 16))
672 registered = true;
673
674 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
675 if (GET_BITFIELD(reg, 14, 14)) {
676 if (registered)
677 mtype = MEM_RDDR4;
678 else
679 mtype = MEM_DDR4;
680 } else {
681 if (registered)
682 mtype = MEM_RDDR3;
683 else
684 mtype = MEM_DDR3;
685 }
686
687 out:
688 return mtype;
689 }
690
get_node_id(struct sbridge_pvt * pvt)691 static u8 get_node_id(struct sbridge_pvt *pvt)
692 {
693 u32 reg;
694 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
695 return GET_BITFIELD(reg, 0, 2);
696 }
697
haswell_get_node_id(struct sbridge_pvt * pvt)698 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
699 {
700 u32 reg;
701
702 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
703 return GET_BITFIELD(reg, 0, 3);
704 }
705
haswell_get_tolm(struct sbridge_pvt * pvt)706 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
707 {
708 u32 reg;
709
710 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
711 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
712 }
713
haswell_get_tohm(struct sbridge_pvt * pvt)714 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
715 {
716 u64 rc;
717 u32 reg;
718
719 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
720 rc = GET_BITFIELD(reg, 26, 31);
721 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
722 rc = ((reg << 6) | rc) << 26;
723
724 return rc | 0x1ffffff;
725 }
726
haswell_rir_limit(u32 reg)727 static u64 haswell_rir_limit(u32 reg)
728 {
729 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
730 }
731
sad_pkg_socket(u8 pkg)732 static inline u8 sad_pkg_socket(u8 pkg)
733 {
734 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
735 return ((pkg >> 3) << 2) | (pkg & 0x3);
736 }
737
sad_pkg_ha(u8 pkg)738 static inline u8 sad_pkg_ha(u8 pkg)
739 {
740 return (pkg >> 2) & 0x1;
741 }
742
743 /****************************************************************************
744 Memory check routines
745 ****************************************************************************/
get_pdev_same_bus(u8 bus,u32 id)746 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
747 {
748 struct pci_dev *pdev = NULL;
749
750 do {
751 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
752 if (pdev && pdev->bus->number == bus)
753 break;
754 } while (pdev);
755
756 return pdev;
757 }
758
759 /**
760 * check_if_ecc_is_active() - Checks if ECC is active
761 * @bus: Device bus
762 * @type: Memory controller type
763 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
764 * disabled
765 */
check_if_ecc_is_active(const u8 bus,enum type type)766 static int check_if_ecc_is_active(const u8 bus, enum type type)
767 {
768 struct pci_dev *pdev = NULL;
769 u32 mcmtr, id;
770
771 if (type == IVY_BRIDGE)
772 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
773 else if (type == HASWELL)
774 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
775 else
776 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
777
778 pdev = get_pdev_same_bus(bus, id);
779 if (!pdev) {
780 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
781 "%04x:%04x! on bus %02d\n",
782 PCI_VENDOR_ID_INTEL, id, bus);
783 return -ENODEV;
784 }
785
786 pci_read_config_dword(pdev, MCMTR, &mcmtr);
787 if (!IS_ECC_ENABLED(mcmtr)) {
788 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
789 return -ENODEV;
790 }
791 return 0;
792 }
793
get_dimm_config(struct mem_ctl_info * mci)794 static int get_dimm_config(struct mem_ctl_info *mci)
795 {
796 struct sbridge_pvt *pvt = mci->pvt_info;
797 struct dimm_info *dimm;
798 unsigned i, j, banks, ranks, rows, cols, npages;
799 u64 size;
800 u32 reg;
801 enum edac_type mode;
802 enum mem_type mtype;
803
804 if (pvt->info.type == HASWELL)
805 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
806 else
807 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
808
809 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
810
811 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
812 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
813 pvt->sbridge_dev->mc,
814 pvt->sbridge_dev->node_id,
815 pvt->sbridge_dev->source_id);
816
817 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
818 if (IS_MIRROR_ENABLED(reg)) {
819 edac_dbg(0, "Memory mirror is enabled\n");
820 pvt->is_mirrored = true;
821 } else {
822 edac_dbg(0, "Memory mirror is disabled\n");
823 pvt->is_mirrored = false;
824 }
825
826 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
827 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
828 edac_dbg(0, "Lockstep is enabled\n");
829 mode = EDAC_S8ECD8ED;
830 pvt->is_lockstep = true;
831 } else {
832 edac_dbg(0, "Lockstep is disabled\n");
833 mode = EDAC_S4ECD4ED;
834 pvt->is_lockstep = false;
835 }
836 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
837 edac_dbg(0, "address map is on closed page mode\n");
838 pvt->is_close_pg = true;
839 } else {
840 edac_dbg(0, "address map is on open page mode\n");
841 pvt->is_close_pg = false;
842 }
843
844 mtype = pvt->info.get_memory_type(pvt);
845 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
846 edac_dbg(0, "Memory is registered\n");
847 else if (mtype == MEM_UNKNOWN)
848 edac_dbg(0, "Cannot determine memory type\n");
849 else
850 edac_dbg(0, "Memory is unregistered\n");
851
852 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
853 banks = 16;
854 else
855 banks = 8;
856
857 for (i = 0; i < NUM_CHANNELS; i++) {
858 u32 mtr;
859
860 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
861 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
862 i, j, 0);
863 pci_read_config_dword(pvt->pci_tad[i],
864 mtr_regs[j], &mtr);
865 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
866 if (IS_DIMM_PRESENT(mtr)) {
867 pvt->channel[i].dimms++;
868
869 ranks = numrank(pvt->info.type, mtr);
870 rows = numrow(mtr);
871 cols = numcol(mtr);
872
873 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
874 npages = MiB_TO_PAGES(size);
875
876 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
877 pvt->sbridge_dev->mc, i, j,
878 size, npages,
879 banks, ranks, rows, cols);
880
881 dimm->nr_pages = npages;
882 dimm->grain = 32;
883 switch (banks) {
884 case 16:
885 dimm->dtype = DEV_X16;
886 break;
887 case 8:
888 dimm->dtype = DEV_X8;
889 break;
890 case 4:
891 dimm->dtype = DEV_X4;
892 break;
893 }
894 dimm->mtype = mtype;
895 dimm->edac_mode = mode;
896 snprintf(dimm->label, sizeof(dimm->label),
897 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
898 pvt->sbridge_dev->source_id, i, j);
899 }
900 }
901 }
902
903 return 0;
904 }
905
get_memory_layout(const struct mem_ctl_info * mci)906 static void get_memory_layout(const struct mem_ctl_info *mci)
907 {
908 struct sbridge_pvt *pvt = mci->pvt_info;
909 int i, j, k, n_sads, n_tads, sad_interl;
910 u32 reg;
911 u64 limit, prv = 0;
912 u64 tmp_mb;
913 u32 gb, mb;
914 u32 rir_way;
915
916 /*
917 * Step 1) Get TOLM/TOHM ranges
918 */
919
920 pvt->tolm = pvt->info.get_tolm(pvt);
921 tmp_mb = (1 + pvt->tolm) >> 20;
922
923 gb = div_u64_rem(tmp_mb, 1024, &mb);
924 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
925 gb, (mb*1000)/1024, (u64)pvt->tolm);
926
927 /* Address range is already 45:25 */
928 pvt->tohm = pvt->info.get_tohm(pvt);
929 tmp_mb = (1 + pvt->tohm) >> 20;
930
931 gb = div_u64_rem(tmp_mb, 1024, &mb);
932 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
933 gb, (mb*1000)/1024, (u64)pvt->tohm);
934
935 /*
936 * Step 2) Get SAD range and SAD Interleave list
937 * TAD registers contain the interleave wayness. However, it
938 * seems simpler to just discover it indirectly, with the
939 * algorithm bellow.
940 */
941 prv = 0;
942 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
943 /* SAD_LIMIT Address range is 45:26 */
944 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
945 ®);
946 limit = SAD_LIMIT(reg);
947
948 if (!DRAM_RULE_ENABLE(reg))
949 continue;
950
951 if (limit <= prv)
952 break;
953
954 tmp_mb = (limit + 1) >> 20;
955 gb = div_u64_rem(tmp_mb, 1024, &mb);
956 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
957 n_sads,
958 get_dram_attr(reg),
959 gb, (mb*1000)/1024,
960 ((u64)tmp_mb) << 20L,
961 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
962 reg);
963 prv = limit;
964
965 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
966 ®);
967 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
968 for (j = 0; j < 8; j++) {
969 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
970 if (j > 0 && sad_interl == pkg)
971 break;
972
973 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
974 n_sads, j, pkg);
975 }
976 }
977
978 /*
979 * Step 3) Get TAD range
980 */
981 prv = 0;
982 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
983 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
984 ®);
985 limit = TAD_LIMIT(reg);
986 if (limit <= prv)
987 break;
988 tmp_mb = (limit + 1) >> 20;
989
990 gb = div_u64_rem(tmp_mb, 1024, &mb);
991 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
992 n_tads, gb, (mb*1000)/1024,
993 ((u64)tmp_mb) << 20L,
994 (u32)(1 << TAD_SOCK(reg)),
995 (u32)TAD_CH(reg) + 1,
996 (u32)TAD_TGT0(reg),
997 (u32)TAD_TGT1(reg),
998 (u32)TAD_TGT2(reg),
999 (u32)TAD_TGT3(reg),
1000 reg);
1001 prv = limit;
1002 }
1003
1004 /*
1005 * Step 4) Get TAD offsets, per each channel
1006 */
1007 for (i = 0; i < NUM_CHANNELS; i++) {
1008 if (!pvt->channel[i].dimms)
1009 continue;
1010 for (j = 0; j < n_tads; j++) {
1011 pci_read_config_dword(pvt->pci_tad[i],
1012 tad_ch_nilv_offset[j],
1013 ®);
1014 tmp_mb = TAD_OFFSET(reg) >> 20;
1015 gb = div_u64_rem(tmp_mb, 1024, &mb);
1016 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1017 i, j,
1018 gb, (mb*1000)/1024,
1019 ((u64)tmp_mb) << 20L,
1020 reg);
1021 }
1022 }
1023
1024 /*
1025 * Step 6) Get RIR Wayness/Limit, per each channel
1026 */
1027 for (i = 0; i < NUM_CHANNELS; i++) {
1028 if (!pvt->channel[i].dimms)
1029 continue;
1030 for (j = 0; j < MAX_RIR_RANGES; j++) {
1031 pci_read_config_dword(pvt->pci_tad[i],
1032 rir_way_limit[j],
1033 ®);
1034
1035 if (!IS_RIR_VALID(reg))
1036 continue;
1037
1038 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1039 rir_way = 1 << RIR_WAY(reg);
1040 gb = div_u64_rem(tmp_mb, 1024, &mb);
1041 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1042 i, j,
1043 gb, (mb*1000)/1024,
1044 ((u64)tmp_mb) << 20L,
1045 rir_way,
1046 reg);
1047
1048 for (k = 0; k < rir_way; k++) {
1049 pci_read_config_dword(pvt->pci_tad[i],
1050 rir_offset[j][k],
1051 ®);
1052 tmp_mb = RIR_OFFSET(reg) << 6;
1053
1054 gb = div_u64_rem(tmp_mb, 1024, &mb);
1055 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1056 i, j, k,
1057 gb, (mb*1000)/1024,
1058 ((u64)tmp_mb) << 20L,
1059 (u32)RIR_RNK_TGT(reg),
1060 reg);
1061 }
1062 }
1063 }
1064 }
1065
get_mci_for_node_id(u8 node_id)1066 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1067 {
1068 struct sbridge_dev *sbridge_dev;
1069
1070 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1071 if (sbridge_dev->node_id == node_id)
1072 return sbridge_dev->mci;
1073 }
1074 return NULL;
1075 }
1076
get_memory_error_data(struct mem_ctl_info * mci,u64 addr,u8 * socket,long * channel_mask,u8 * rank,char ** area_type,char * msg)1077 static int get_memory_error_data(struct mem_ctl_info *mci,
1078 u64 addr,
1079 u8 *socket,
1080 long *channel_mask,
1081 u8 *rank,
1082 char **area_type, char *msg)
1083 {
1084 struct mem_ctl_info *new_mci;
1085 struct sbridge_pvt *pvt = mci->pvt_info;
1086 struct pci_dev *pci_ha;
1087 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1088 int sad_interl, idx, base_ch;
1089 int interleave_mode, shiftup = 0;
1090 unsigned sad_interleave[pvt->info.max_interleave];
1091 u32 reg, dram_rule;
1092 u8 ch_way, sck_way, pkg, sad_ha = 0;
1093 u32 tad_offset;
1094 u32 rir_way;
1095 u32 mb, gb;
1096 u64 ch_addr, offset, limit = 0, prv = 0;
1097
1098
1099 /*
1100 * Step 0) Check if the address is at special memory ranges
1101 * The check bellow is probably enough to fill all cases where
1102 * the error is not inside a memory, except for the legacy
1103 * range (e. g. VGA addresses). It is unlikely, however, that the
1104 * memory controller would generate an error on that range.
1105 */
1106 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1107 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1108 return -EINVAL;
1109 }
1110 if (addr >= (u64)pvt->tohm) {
1111 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1112 return -EINVAL;
1113 }
1114
1115 /*
1116 * Step 1) Get socket
1117 */
1118 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1119 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1120 ®);
1121
1122 if (!DRAM_RULE_ENABLE(reg))
1123 continue;
1124
1125 limit = SAD_LIMIT(reg);
1126 if (limit <= prv) {
1127 sprintf(msg, "Can't discover the memory socket");
1128 return -EINVAL;
1129 }
1130 if (addr <= limit)
1131 break;
1132 prv = limit;
1133 }
1134 if (n_sads == pvt->info.max_sad) {
1135 sprintf(msg, "Can't discover the memory socket");
1136 return -EINVAL;
1137 }
1138 dram_rule = reg;
1139 *area_type = get_dram_attr(dram_rule);
1140 interleave_mode = INTERLEAVE_MODE(dram_rule);
1141
1142 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1143 ®);
1144
1145 if (pvt->info.type == SANDY_BRIDGE) {
1146 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1147 for (sad_way = 0; sad_way < 8; sad_way++) {
1148 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1149 if (sad_way > 0 && sad_interl == pkg)
1150 break;
1151 sad_interleave[sad_way] = pkg;
1152 edac_dbg(0, "SAD interleave #%d: %d\n",
1153 sad_way, sad_interleave[sad_way]);
1154 }
1155 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1156 pvt->sbridge_dev->mc,
1157 n_sads,
1158 addr,
1159 limit,
1160 sad_way + 7,
1161 !interleave_mode ? "" : "XOR[18:16]");
1162 if (interleave_mode)
1163 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1164 else
1165 idx = (addr >> 6) & 7;
1166 switch (sad_way) {
1167 case 1:
1168 idx = 0;
1169 break;
1170 case 2:
1171 idx = idx & 1;
1172 break;
1173 case 4:
1174 idx = idx & 3;
1175 break;
1176 case 8:
1177 break;
1178 default:
1179 sprintf(msg, "Can't discover socket interleave");
1180 return -EINVAL;
1181 }
1182 *socket = sad_interleave[idx];
1183 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1184 idx, sad_way, *socket);
1185 } else if (pvt->info.type == HASWELL) {
1186 int bits, a7mode = A7MODE(dram_rule);
1187
1188 if (a7mode) {
1189 /* A7 mode swaps P9 with P6 */
1190 bits = GET_BITFIELD(addr, 7, 8) << 1;
1191 bits |= GET_BITFIELD(addr, 9, 9);
1192 } else
1193 bits = GET_BITFIELD(addr, 7, 9);
1194
1195 if (interleave_mode) {
1196 /* interleave mode will XOR {8,7,6} with {18,17,16} */
1197 idx = GET_BITFIELD(addr, 16, 18);
1198 idx ^= bits;
1199 } else
1200 idx = bits;
1201
1202 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1203 *socket = sad_pkg_socket(pkg);
1204 sad_ha = sad_pkg_ha(pkg);
1205
1206 if (a7mode) {
1207 /* MCChanShiftUpEnable */
1208 pci_read_config_dword(pvt->pci_ha0,
1209 HASWELL_HASYSDEFEATURE2, ®);
1210 shiftup = GET_BITFIELD(reg, 22, 22);
1211 }
1212
1213 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1214 idx, *socket, sad_ha, shiftup);
1215 } else {
1216 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1217 idx = (addr >> 6) & 7;
1218 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1219 *socket = sad_pkg_socket(pkg);
1220 sad_ha = sad_pkg_ha(pkg);
1221 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1222 idx, *socket, sad_ha);
1223 }
1224
1225 /*
1226 * Move to the proper node structure, in order to access the
1227 * right PCI registers
1228 */
1229 new_mci = get_mci_for_node_id(*socket);
1230 if (!new_mci) {
1231 sprintf(msg, "Struct for socket #%u wasn't initialized",
1232 *socket);
1233 return -EINVAL;
1234 }
1235 mci = new_mci;
1236 pvt = mci->pvt_info;
1237
1238 /*
1239 * Step 2) Get memory channel
1240 */
1241 prv = 0;
1242 if (pvt->info.type == SANDY_BRIDGE)
1243 pci_ha = pvt->pci_ha0;
1244 else {
1245 if (sad_ha)
1246 pci_ha = pvt->pci_ha1;
1247 else
1248 pci_ha = pvt->pci_ha0;
1249 }
1250 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1251 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
1252 limit = TAD_LIMIT(reg);
1253 if (limit <= prv) {
1254 sprintf(msg, "Can't discover the memory channel");
1255 return -EINVAL;
1256 }
1257 if (addr <= limit)
1258 break;
1259 prv = limit;
1260 }
1261 if (n_tads == MAX_TAD) {
1262 sprintf(msg, "Can't discover the memory channel");
1263 return -EINVAL;
1264 }
1265
1266 ch_way = TAD_CH(reg) + 1;
1267 sck_way = TAD_SOCK(reg);
1268
1269 if (ch_way == 3)
1270 idx = addr >> 6;
1271 else
1272 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1273 idx = idx % ch_way;
1274
1275 /*
1276 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1277 */
1278 switch (idx) {
1279 case 0:
1280 base_ch = TAD_TGT0(reg);
1281 break;
1282 case 1:
1283 base_ch = TAD_TGT1(reg);
1284 break;
1285 case 2:
1286 base_ch = TAD_TGT2(reg);
1287 break;
1288 case 3:
1289 base_ch = TAD_TGT3(reg);
1290 break;
1291 default:
1292 sprintf(msg, "Can't discover the TAD target");
1293 return -EINVAL;
1294 }
1295 *channel_mask = 1 << base_ch;
1296
1297 pci_read_config_dword(pvt->pci_tad[base_ch],
1298 tad_ch_nilv_offset[n_tads],
1299 &tad_offset);
1300
1301 if (pvt->is_mirrored) {
1302 *channel_mask |= 1 << ((base_ch + 2) % 4);
1303 switch(ch_way) {
1304 case 2:
1305 case 4:
1306 sck_xch = (1 << sck_way) * (ch_way >> 1);
1307 break;
1308 default:
1309 sprintf(msg, "Invalid mirror set. Can't decode addr");
1310 return -EINVAL;
1311 }
1312 } else
1313 sck_xch = (1 << sck_way) * ch_way;
1314
1315 if (pvt->is_lockstep)
1316 *channel_mask |= 1 << ((base_ch + 1) % 4);
1317
1318 offset = TAD_OFFSET(tad_offset);
1319
1320 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1321 n_tads,
1322 addr,
1323 limit,
1324 sck_way,
1325 ch_way,
1326 offset,
1327 idx,
1328 base_ch,
1329 *channel_mask);
1330
1331 /* Calculate channel address */
1332 /* Remove the TAD offset */
1333
1334 if (offset > addr) {
1335 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1336 offset, addr);
1337 return -EINVAL;
1338 }
1339
1340 ch_addr = addr - offset;
1341 ch_addr >>= (6 + shiftup);
1342 ch_addr /= sck_xch;
1343 ch_addr <<= (6 + shiftup);
1344 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
1345
1346 /*
1347 * Step 3) Decode rank
1348 */
1349 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1350 pci_read_config_dword(pvt->pci_tad[base_ch],
1351 rir_way_limit[n_rir],
1352 ®);
1353
1354 if (!IS_RIR_VALID(reg))
1355 continue;
1356
1357 limit = pvt->info.rir_limit(reg);
1358 gb = div_u64_rem(limit >> 20, 1024, &mb);
1359 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1360 n_rir,
1361 gb, (mb*1000)/1024,
1362 limit,
1363 1 << RIR_WAY(reg));
1364 if (ch_addr <= limit)
1365 break;
1366 }
1367 if (n_rir == MAX_RIR_RANGES) {
1368 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1369 ch_addr);
1370 return -EINVAL;
1371 }
1372 rir_way = RIR_WAY(reg);
1373
1374 if (pvt->is_close_pg)
1375 idx = (ch_addr >> 6);
1376 else
1377 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1378 idx %= 1 << rir_way;
1379
1380 pci_read_config_dword(pvt->pci_tad[base_ch],
1381 rir_offset[n_rir][idx],
1382 ®);
1383 *rank = RIR_RNK_TGT(reg);
1384
1385 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1386 n_rir,
1387 ch_addr,
1388 limit,
1389 rir_way,
1390 idx);
1391
1392 return 0;
1393 }
1394
1395 /****************************************************************************
1396 Device initialization routines: put/get, init/exit
1397 ****************************************************************************/
1398
1399 /*
1400 * sbridge_put_all_devices 'put' all the devices that we have
1401 * reserved via 'get'
1402 */
sbridge_put_devices(struct sbridge_dev * sbridge_dev)1403 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1404 {
1405 int i;
1406
1407 edac_dbg(0, "\n");
1408 for (i = 0; i < sbridge_dev->n_devs; i++) {
1409 struct pci_dev *pdev = sbridge_dev->pdev[i];
1410 if (!pdev)
1411 continue;
1412 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1413 pdev->bus->number,
1414 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1415 pci_dev_put(pdev);
1416 }
1417 }
1418
sbridge_put_all_devices(void)1419 static void sbridge_put_all_devices(void)
1420 {
1421 struct sbridge_dev *sbridge_dev, *tmp;
1422
1423 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1424 sbridge_put_devices(sbridge_dev);
1425 free_sbridge_dev(sbridge_dev);
1426 }
1427 }
1428
sbridge_get_onedevice(struct pci_dev ** prev,u8 * num_mc,const struct pci_id_table * table,const unsigned devno)1429 static int sbridge_get_onedevice(struct pci_dev **prev,
1430 u8 *num_mc,
1431 const struct pci_id_table *table,
1432 const unsigned devno)
1433 {
1434 struct sbridge_dev *sbridge_dev;
1435 const struct pci_id_descr *dev_descr = &table->descr[devno];
1436 struct pci_dev *pdev = NULL;
1437 u8 bus = 0;
1438
1439 sbridge_printk(KERN_DEBUG,
1440 "Seeking for: PCI ID %04x:%04x\n",
1441 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1442
1443 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1444 dev_descr->dev_id, *prev);
1445
1446 if (!pdev) {
1447 if (*prev) {
1448 *prev = pdev;
1449 return 0;
1450 }
1451
1452 if (dev_descr->optional)
1453 return 0;
1454
1455 /* if the HA wasn't found */
1456 if (devno == 0)
1457 return -ENODEV;
1458
1459 sbridge_printk(KERN_INFO,
1460 "Device not found: %04x:%04x\n",
1461 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1462
1463 /* End of list, leave */
1464 return -ENODEV;
1465 }
1466 bus = pdev->bus->number;
1467
1468 sbridge_dev = get_sbridge_dev(bus);
1469 if (!sbridge_dev) {
1470 sbridge_dev = alloc_sbridge_dev(bus, table);
1471 if (!sbridge_dev) {
1472 pci_dev_put(pdev);
1473 return -ENOMEM;
1474 }
1475 (*num_mc)++;
1476 }
1477
1478 if (sbridge_dev->pdev[devno]) {
1479 sbridge_printk(KERN_ERR,
1480 "Duplicated device for %04x:%04x\n",
1481 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1482 pci_dev_put(pdev);
1483 return -ENODEV;
1484 }
1485
1486 sbridge_dev->pdev[devno] = pdev;
1487
1488 /* Be sure that the device is enabled */
1489 if (unlikely(pci_enable_device(pdev) < 0)) {
1490 sbridge_printk(KERN_ERR,
1491 "Couldn't enable %04x:%04x\n",
1492 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1493 return -ENODEV;
1494 }
1495
1496 edac_dbg(0, "Detected %04x:%04x\n",
1497 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1498
1499 /*
1500 * As stated on drivers/pci/search.c, the reference count for
1501 * @from is always decremented if it is not %NULL. So, as we need
1502 * to get all devices up to null, we need to do a get for the device
1503 */
1504 pci_dev_get(pdev);
1505
1506 *prev = pdev;
1507
1508 return 0;
1509 }
1510
1511 /*
1512 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1513 * devices we want to reference for this driver.
1514 * @num_mc: pointer to the memory controllers count, to be incremented in case
1515 * of success.
1516 * @table: model specific table
1517 *
1518 * returns 0 in case of success or error code
1519 */
sbridge_get_all_devices(u8 * num_mc,const struct pci_id_table * table)1520 static int sbridge_get_all_devices(u8 *num_mc,
1521 const struct pci_id_table *table)
1522 {
1523 int i, rc;
1524 struct pci_dev *pdev = NULL;
1525
1526 while (table && table->descr) {
1527 for (i = 0; i < table->n_devs; i++) {
1528 pdev = NULL;
1529 do {
1530 rc = sbridge_get_onedevice(&pdev, num_mc,
1531 table, i);
1532 if (rc < 0) {
1533 if (i == 0) {
1534 i = table->n_devs;
1535 break;
1536 }
1537 sbridge_put_all_devices();
1538 return -ENODEV;
1539 }
1540 } while (pdev);
1541 }
1542 table++;
1543 }
1544
1545 return 0;
1546 }
1547
sbridge_mci_bind_devs(struct mem_ctl_info * mci,struct sbridge_dev * sbridge_dev)1548 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1549 struct sbridge_dev *sbridge_dev)
1550 {
1551 struct sbridge_pvt *pvt = mci->pvt_info;
1552 struct pci_dev *pdev;
1553 int i;
1554
1555 for (i = 0; i < sbridge_dev->n_devs; i++) {
1556 pdev = sbridge_dev->pdev[i];
1557 if (!pdev)
1558 continue;
1559
1560 switch (pdev->device) {
1561 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1562 pvt->pci_sad0 = pdev;
1563 break;
1564 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1565 pvt->pci_sad1 = pdev;
1566 break;
1567 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1568 pvt->pci_br0 = pdev;
1569 break;
1570 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1571 pvt->pci_ha0 = pdev;
1572 break;
1573 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1574 pvt->pci_ta = pdev;
1575 break;
1576 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1577 pvt->pci_ras = pdev;
1578 break;
1579 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1580 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1581 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1582 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1583 {
1584 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1585 pvt->pci_tad[id] = pdev;
1586 }
1587 break;
1588 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1589 pvt->pci_ddrio = pdev;
1590 break;
1591 default:
1592 goto error;
1593 }
1594
1595 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1596 pdev->vendor, pdev->device,
1597 sbridge_dev->bus,
1598 pdev);
1599 }
1600
1601 /* Check if everything were registered */
1602 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1603 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1604 goto enodev;
1605
1606 for (i = 0; i < NUM_CHANNELS; i++) {
1607 if (!pvt->pci_tad[i])
1608 goto enodev;
1609 }
1610 return 0;
1611
1612 enodev:
1613 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1614 return -ENODEV;
1615
1616 error:
1617 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1618 PCI_VENDOR_ID_INTEL, pdev->device);
1619 return -EINVAL;
1620 }
1621
ibridge_mci_bind_devs(struct mem_ctl_info * mci,struct sbridge_dev * sbridge_dev)1622 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1623 struct sbridge_dev *sbridge_dev)
1624 {
1625 struct sbridge_pvt *pvt = mci->pvt_info;
1626 struct pci_dev *pdev, *tmp;
1627 int i;
1628 bool mode_2ha = false;
1629
1630 tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1631 PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL);
1632 if (tmp) {
1633 mode_2ha = true;
1634 pci_dev_put(tmp);
1635 }
1636
1637 for (i = 0; i < sbridge_dev->n_devs; i++) {
1638 pdev = sbridge_dev->pdev[i];
1639 if (!pdev)
1640 continue;
1641
1642 switch (pdev->device) {
1643 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1644 pvt->pci_ha0 = pdev;
1645 break;
1646 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1647 pvt->pci_ta = pdev;
1648 break;
1649 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1650 pvt->pci_ras = pdev;
1651 break;
1652 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1653 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1654 /* if we have 2 HAs active, channels 2 and 3
1655 * are in other device */
1656 if (mode_2ha)
1657 break;
1658 /* fall through */
1659 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1660 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1661 {
1662 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1663 pvt->pci_tad[id] = pdev;
1664 }
1665 break;
1666 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1667 pvt->pci_ddrio = pdev;
1668 break;
1669 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1670 if (!mode_2ha)
1671 pvt->pci_ddrio = pdev;
1672 break;
1673 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1674 pvt->pci_sad0 = pdev;
1675 break;
1676 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1677 pvt->pci_br0 = pdev;
1678 break;
1679 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1680 pvt->pci_br1 = pdev;
1681 break;
1682 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1683 pvt->pci_ha1 = pdev;
1684 break;
1685 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1686 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1687 {
1688 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2;
1689
1690 /* we shouldn't have this device if we have just one
1691 * HA present */
1692 WARN_ON(!mode_2ha);
1693 pvt->pci_tad[id] = pdev;
1694 }
1695 break;
1696 default:
1697 goto error;
1698 }
1699
1700 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1701 sbridge_dev->bus,
1702 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1703 pdev);
1704 }
1705
1706 /* Check if everything were registered */
1707 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1708 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1709 !pvt->pci_ta)
1710 goto enodev;
1711
1712 for (i = 0; i < NUM_CHANNELS; i++) {
1713 if (!pvt->pci_tad[i])
1714 goto enodev;
1715 }
1716 return 0;
1717
1718 enodev:
1719 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1720 return -ENODEV;
1721
1722 error:
1723 sbridge_printk(KERN_ERR,
1724 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1725 pdev->device);
1726 return -EINVAL;
1727 }
1728
haswell_mci_bind_devs(struct mem_ctl_info * mci,struct sbridge_dev * sbridge_dev)1729 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1730 struct sbridge_dev *sbridge_dev)
1731 {
1732 struct sbridge_pvt *pvt = mci->pvt_info;
1733 struct pci_dev *pdev, *tmp;
1734 int i;
1735 bool mode_2ha = false;
1736
1737 tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1738 PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL);
1739 if (tmp) {
1740 mode_2ha = true;
1741 pci_dev_put(tmp);
1742 }
1743
1744 /* there's only one device per system; not tied to any bus */
1745 if (pvt->info.pci_vtd == NULL)
1746 /* result will be checked later */
1747 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1748 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1749 NULL);
1750
1751 for (i = 0; i < sbridge_dev->n_devs; i++) {
1752 pdev = sbridge_dev->pdev[i];
1753 if (!pdev)
1754 continue;
1755
1756 switch (pdev->device) {
1757 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1758 pvt->pci_sad0 = pdev;
1759 break;
1760 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1761 pvt->pci_sad1 = pdev;
1762 break;
1763 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1764 pvt->pci_ha0 = pdev;
1765 break;
1766 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1767 pvt->pci_ta = pdev;
1768 break;
1769 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1770 pvt->pci_ras = pdev;
1771 break;
1772 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1773 pvt->pci_tad[0] = pdev;
1774 break;
1775 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1776 pvt->pci_tad[1] = pdev;
1777 break;
1778 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1779 if (!mode_2ha)
1780 pvt->pci_tad[2] = pdev;
1781 break;
1782 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1783 if (!mode_2ha)
1784 pvt->pci_tad[3] = pdev;
1785 break;
1786 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1787 pvt->pci_ddrio = pdev;
1788 break;
1789 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1790 pvt->pci_ha1 = pdev;
1791 break;
1792 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1793 pvt->pci_ha1_ta = pdev;
1794 break;
1795 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1796 if (mode_2ha)
1797 pvt->pci_tad[2] = pdev;
1798 break;
1799 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1800 if (mode_2ha)
1801 pvt->pci_tad[3] = pdev;
1802 break;
1803 default:
1804 break;
1805 }
1806
1807 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1808 sbridge_dev->bus,
1809 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1810 pdev);
1811 }
1812
1813 /* Check if everything were registered */
1814 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1815 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1816 goto enodev;
1817
1818 for (i = 0; i < NUM_CHANNELS; i++) {
1819 if (!pvt->pci_tad[i])
1820 goto enodev;
1821 }
1822 return 0;
1823
1824 enodev:
1825 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1826 return -ENODEV;
1827 }
1828
1829 /****************************************************************************
1830 Error check routines
1831 ****************************************************************************/
1832
1833 /*
1834 * While Sandy Bridge has error count registers, SMI BIOS read values from
1835 * and resets the counters. So, they are not reliable for the OS to read
1836 * from them. So, we have no option but to just trust on whatever MCE is
1837 * telling us about the errors.
1838 */
sbridge_mce_output_error(struct mem_ctl_info * mci,const struct mce * m)1839 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1840 const struct mce *m)
1841 {
1842 struct mem_ctl_info *new_mci;
1843 struct sbridge_pvt *pvt = mci->pvt_info;
1844 enum hw_event_mc_err_type tp_event;
1845 char *type, *optype, msg[256];
1846 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1847 bool overflow = GET_BITFIELD(m->status, 62, 62);
1848 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1849 bool recoverable;
1850 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1851 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1852 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1853 u32 channel = GET_BITFIELD(m->status, 0, 3);
1854 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1855 long channel_mask, first_channel;
1856 u8 rank, socket;
1857 int rc, dimm;
1858 char *area_type = NULL;
1859
1860 if (pvt->info.type == IVY_BRIDGE)
1861 recoverable = true;
1862 else
1863 recoverable = GET_BITFIELD(m->status, 56, 56);
1864
1865 if (uncorrected_error) {
1866 if (ripv) {
1867 type = "FATAL";
1868 tp_event = HW_EVENT_ERR_FATAL;
1869 } else {
1870 type = "NON_FATAL";
1871 tp_event = HW_EVENT_ERR_UNCORRECTED;
1872 }
1873 } else {
1874 type = "CORRECTED";
1875 tp_event = HW_EVENT_ERR_CORRECTED;
1876 }
1877
1878 /*
1879 * According with Table 15-9 of the Intel Architecture spec vol 3A,
1880 * memory errors should fit in this mask:
1881 * 000f 0000 1mmm cccc (binary)
1882 * where:
1883 * f = Correction Report Filtering Bit. If 1, subsequent errors
1884 * won't be shown
1885 * mmm = error type
1886 * cccc = channel
1887 * If the mask doesn't match, report an error to the parsing logic
1888 */
1889 if (! ((errcode & 0xef80) == 0x80)) {
1890 optype = "Can't parse: it is not a mem";
1891 } else {
1892 switch (optypenum) {
1893 case 0:
1894 optype = "generic undef request error";
1895 break;
1896 case 1:
1897 optype = "memory read error";
1898 break;
1899 case 2:
1900 optype = "memory write error";
1901 break;
1902 case 3:
1903 optype = "addr/cmd error";
1904 break;
1905 case 4:
1906 optype = "memory scrubbing error";
1907 break;
1908 default:
1909 optype = "reserved";
1910 break;
1911 }
1912 }
1913
1914 /* Only decode errors with an valid address (ADDRV) */
1915 if (!GET_BITFIELD(m->status, 58, 58))
1916 return;
1917
1918 rc = get_memory_error_data(mci, m->addr, &socket,
1919 &channel_mask, &rank, &area_type, msg);
1920 if (rc < 0)
1921 goto err_parsing;
1922 new_mci = get_mci_for_node_id(socket);
1923 if (!new_mci) {
1924 strcpy(msg, "Error: socket got corrupted!");
1925 goto err_parsing;
1926 }
1927 mci = new_mci;
1928 pvt = mci->pvt_info;
1929
1930 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1931
1932 if (rank < 4)
1933 dimm = 0;
1934 else if (rank < 8)
1935 dimm = 1;
1936 else
1937 dimm = 2;
1938
1939
1940 /*
1941 * FIXME: On some memory configurations (mirror, lockstep), the
1942 * Memory Controller can't point the error to a single DIMM. The
1943 * EDAC core should be handling the channel mask, in order to point
1944 * to the group of dimm's where the error may be happening.
1945 */
1946 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
1947 channel = first_channel;
1948
1949 snprintf(msg, sizeof(msg),
1950 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
1951 overflow ? " OVERFLOW" : "",
1952 (uncorrected_error && recoverable) ? " recoverable" : "",
1953 area_type,
1954 mscod, errcode,
1955 socket,
1956 channel_mask,
1957 rank);
1958
1959 edac_dbg(0, "%s\n", msg);
1960
1961 /* FIXME: need support for channel mask */
1962
1963 if (channel == CHANNEL_UNSPECIFIED)
1964 channel = -1;
1965
1966 /* Call the helper to output message */
1967 edac_mc_handle_error(tp_event, mci, core_err_cnt,
1968 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1969 channel, dimm, -1,
1970 optype, msg);
1971 return;
1972 err_parsing:
1973 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
1974 -1, -1, -1,
1975 msg, "");
1976
1977 }
1978
1979 /*
1980 * sbridge_check_error Retrieve and process errors reported by the
1981 * hardware. Called by the Core module.
1982 */
sbridge_check_error(struct mem_ctl_info * mci)1983 static void sbridge_check_error(struct mem_ctl_info *mci)
1984 {
1985 struct sbridge_pvt *pvt = mci->pvt_info;
1986 int i;
1987 unsigned count = 0;
1988 struct mce *m;
1989
1990 /*
1991 * MCE first step: Copy all mce errors into a temporary buffer
1992 * We use a double buffering here, to reduce the risk of
1993 * loosing an error.
1994 */
1995 smp_rmb();
1996 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1997 % MCE_LOG_LEN;
1998 if (!count)
1999 return;
2000
2001 m = pvt->mce_outentry;
2002 if (pvt->mce_in + count > MCE_LOG_LEN) {
2003 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2004
2005 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2006 smp_wmb();
2007 pvt->mce_in = 0;
2008 count -= l;
2009 m += l;
2010 }
2011 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2012 smp_wmb();
2013 pvt->mce_in += count;
2014
2015 smp_rmb();
2016 if (pvt->mce_overrun) {
2017 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2018 pvt->mce_overrun);
2019 smp_wmb();
2020 pvt->mce_overrun = 0;
2021 }
2022
2023 /*
2024 * MCE second step: parse errors and display
2025 */
2026 for (i = 0; i < count; i++)
2027 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2028 }
2029
2030 /*
2031 * sbridge_mce_check_error Replicates mcelog routine to get errors
2032 * This routine simply queues mcelog errors, and
2033 * return. The error itself should be handled later
2034 * by sbridge_check_error.
2035 * WARNING: As this routine should be called at NMI time, extra care should
2036 * be taken to avoid deadlocks, and to be as fast as possible.
2037 */
sbridge_mce_check_error(struct notifier_block * nb,unsigned long val,void * data)2038 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2039 void *data)
2040 {
2041 struct mce *mce = (struct mce *)data;
2042 struct mem_ctl_info *mci;
2043 struct sbridge_pvt *pvt;
2044 char *type;
2045
2046 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2047 return NOTIFY_DONE;
2048
2049 mci = get_mci_for_node_id(mce->socketid);
2050 if (!mci)
2051 return NOTIFY_DONE;
2052 pvt = mci->pvt_info;
2053
2054 /*
2055 * Just let mcelog handle it if the error is
2056 * outside the memory controller. A memory error
2057 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2058 * bit 12 has an special meaning.
2059 */
2060 if ((mce->status & 0xefff) >> 7 != 1)
2061 return NOTIFY_DONE;
2062
2063 if (mce->mcgstatus & MCG_STATUS_MCIP)
2064 type = "Exception";
2065 else
2066 type = "Event";
2067
2068 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2069
2070 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2071 "Bank %d: %016Lx\n", mce->extcpu, type,
2072 mce->mcgstatus, mce->bank, mce->status);
2073 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2074 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2075 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2076
2077 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2078 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2079 mce->time, mce->socketid, mce->apicid);
2080
2081 smp_rmb();
2082 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2083 smp_wmb();
2084 pvt->mce_overrun++;
2085 return NOTIFY_DONE;
2086 }
2087
2088 /* Copy memory error at the ringbuffer */
2089 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2090 smp_wmb();
2091 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2092
2093 /* Handle fatal errors immediately */
2094 if (mce->mcgstatus & 1)
2095 sbridge_check_error(mci);
2096
2097 /* Advice mcelog that the error were handled */
2098 return NOTIFY_STOP;
2099 }
2100
2101 static struct notifier_block sbridge_mce_dec = {
2102 .notifier_call = sbridge_mce_check_error,
2103 };
2104
2105 /****************************************************************************
2106 EDAC register/unregister logic
2107 ****************************************************************************/
2108
sbridge_unregister_mci(struct sbridge_dev * sbridge_dev)2109 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2110 {
2111 struct mem_ctl_info *mci = sbridge_dev->mci;
2112 struct sbridge_pvt *pvt;
2113
2114 if (unlikely(!mci || !mci->pvt_info)) {
2115 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2116
2117 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2118 return;
2119 }
2120
2121 pvt = mci->pvt_info;
2122
2123 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2124 mci, &sbridge_dev->pdev[0]->dev);
2125
2126 /* Remove MC sysfs nodes */
2127 edac_mc_del_mc(mci->pdev);
2128
2129 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2130 kfree(mci->ctl_name);
2131 edac_mc_free(mci);
2132 sbridge_dev->mci = NULL;
2133 }
2134
sbridge_register_mci(struct sbridge_dev * sbridge_dev,enum type type)2135 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2136 {
2137 struct mem_ctl_info *mci;
2138 struct edac_mc_layer layers[2];
2139 struct sbridge_pvt *pvt;
2140 struct pci_dev *pdev = sbridge_dev->pdev[0];
2141 int rc;
2142
2143 /* Check the number of active and not disabled channels */
2144 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2145 if (unlikely(rc < 0))
2146 return rc;
2147
2148 /* allocate a new MC control structure */
2149 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2150 layers[0].size = NUM_CHANNELS;
2151 layers[0].is_virt_csrow = false;
2152 layers[1].type = EDAC_MC_LAYER_SLOT;
2153 layers[1].size = MAX_DIMMS;
2154 layers[1].is_virt_csrow = true;
2155 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2156 sizeof(*pvt));
2157
2158 if (unlikely(!mci))
2159 return -ENOMEM;
2160
2161 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2162 mci, &pdev->dev);
2163
2164 pvt = mci->pvt_info;
2165 memset(pvt, 0, sizeof(*pvt));
2166
2167 /* Associate sbridge_dev and mci for future usage */
2168 pvt->sbridge_dev = sbridge_dev;
2169 sbridge_dev->mci = mci;
2170
2171 mci->mtype_cap = MEM_FLAG_DDR3;
2172 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2173 mci->edac_cap = EDAC_FLAG_NONE;
2174 mci->mod_name = "sbridge_edac.c";
2175 mci->mod_ver = SBRIDGE_REVISION;
2176 mci->dev_name = pci_name(pdev);
2177 mci->ctl_page_to_phys = NULL;
2178
2179 /* Set the function pointer to an actual operation function */
2180 mci->edac_check = sbridge_check_error;
2181
2182 pvt->info.type = type;
2183 switch (type) {
2184 case IVY_BRIDGE:
2185 pvt->info.rankcfgr = IB_RANK_CFG_A;
2186 pvt->info.get_tolm = ibridge_get_tolm;
2187 pvt->info.get_tohm = ibridge_get_tohm;
2188 pvt->info.dram_rule = ibridge_dram_rule;
2189 pvt->info.get_memory_type = get_memory_type;
2190 pvt->info.get_node_id = get_node_id;
2191 pvt->info.rir_limit = rir_limit;
2192 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2193 pvt->info.interleave_list = ibridge_interleave_list;
2194 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2195 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2196 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2197
2198 /* Store pci devices at mci for faster access */
2199 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2200 if (unlikely(rc < 0))
2201 goto fail0;
2202 break;
2203 case SANDY_BRIDGE:
2204 pvt->info.rankcfgr = SB_RANK_CFG_A;
2205 pvt->info.get_tolm = sbridge_get_tolm;
2206 pvt->info.get_tohm = sbridge_get_tohm;
2207 pvt->info.dram_rule = sbridge_dram_rule;
2208 pvt->info.get_memory_type = get_memory_type;
2209 pvt->info.get_node_id = get_node_id;
2210 pvt->info.rir_limit = rir_limit;
2211 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2212 pvt->info.interleave_list = sbridge_interleave_list;
2213 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2214 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2215 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2216
2217 /* Store pci devices at mci for faster access */
2218 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2219 if (unlikely(rc < 0))
2220 goto fail0;
2221 break;
2222 case HASWELL:
2223 /* rankcfgr isn't used */
2224 pvt->info.get_tolm = haswell_get_tolm;
2225 pvt->info.get_tohm = haswell_get_tohm;
2226 pvt->info.dram_rule = ibridge_dram_rule;
2227 pvt->info.get_memory_type = haswell_get_memory_type;
2228 pvt->info.get_node_id = haswell_get_node_id;
2229 pvt->info.rir_limit = haswell_rir_limit;
2230 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2231 pvt->info.interleave_list = ibridge_interleave_list;
2232 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2233 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2234 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2235
2236 /* Store pci devices at mci for faster access */
2237 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2238 if (unlikely(rc < 0))
2239 goto fail0;
2240 break;
2241 }
2242
2243 /* Get dimm basic config and the memory layout */
2244 get_dimm_config(mci);
2245 get_memory_layout(mci);
2246
2247 /* record ptr to the generic device */
2248 mci->pdev = &pdev->dev;
2249
2250 /* add this new MC control structure to EDAC's list of MCs */
2251 if (unlikely(edac_mc_add_mc(mci))) {
2252 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2253 rc = -EINVAL;
2254 goto fail0;
2255 }
2256
2257 return 0;
2258
2259 fail0:
2260 kfree(mci->ctl_name);
2261 edac_mc_free(mci);
2262 sbridge_dev->mci = NULL;
2263 return rc;
2264 }
2265
2266 /*
2267 * sbridge_probe Probe for ONE instance of device to see if it is
2268 * present.
2269 * return:
2270 * 0 for FOUND a device
2271 * < 0 for error code
2272 */
2273
sbridge_probe(struct pci_dev * pdev,const struct pci_device_id * id)2274 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2275 {
2276 int rc = -ENODEV;
2277 u8 mc, num_mc = 0;
2278 struct sbridge_dev *sbridge_dev;
2279 enum type type = SANDY_BRIDGE;
2280
2281 /* get the pci devices we want to reserve for our use */
2282 mutex_lock(&sbridge_edac_lock);
2283
2284 /*
2285 * All memory controllers are allocated at the first pass.
2286 */
2287 if (unlikely(probed >= 1)) {
2288 mutex_unlock(&sbridge_edac_lock);
2289 return -ENODEV;
2290 }
2291 probed++;
2292
2293 switch (pdev->device) {
2294 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2295 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2296 type = IVY_BRIDGE;
2297 break;
2298 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2299 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2300 type = SANDY_BRIDGE;
2301 break;
2302 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2303 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2304 type = HASWELL;
2305 break;
2306 }
2307 if (unlikely(rc < 0)) {
2308 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2309 goto fail0;
2310 }
2311
2312 mc = 0;
2313
2314 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2315 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2316 mc, mc + 1, num_mc);
2317
2318 sbridge_dev->mc = mc++;
2319 rc = sbridge_register_mci(sbridge_dev, type);
2320 if (unlikely(rc < 0))
2321 goto fail1;
2322 }
2323
2324 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2325
2326 mutex_unlock(&sbridge_edac_lock);
2327 return 0;
2328
2329 fail1:
2330 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2331 sbridge_unregister_mci(sbridge_dev);
2332
2333 sbridge_put_all_devices();
2334 fail0:
2335 mutex_unlock(&sbridge_edac_lock);
2336 return rc;
2337 }
2338
2339 /*
2340 * sbridge_remove destructor for one instance of device
2341 *
2342 */
sbridge_remove(struct pci_dev * pdev)2343 static void sbridge_remove(struct pci_dev *pdev)
2344 {
2345 struct sbridge_dev *sbridge_dev;
2346
2347 edac_dbg(0, "\n");
2348
2349 /*
2350 * we have a trouble here: pdev value for removal will be wrong, since
2351 * it will point to the X58 register used to detect that the machine
2352 * is a Nehalem or upper design. However, due to the way several PCI
2353 * devices are grouped together to provide MC functionality, we need
2354 * to use a different method for releasing the devices
2355 */
2356
2357 mutex_lock(&sbridge_edac_lock);
2358
2359 if (unlikely(!probed)) {
2360 mutex_unlock(&sbridge_edac_lock);
2361 return;
2362 }
2363
2364 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2365 sbridge_unregister_mci(sbridge_dev);
2366
2367 /* Release PCI resources */
2368 sbridge_put_all_devices();
2369
2370 probed--;
2371
2372 mutex_unlock(&sbridge_edac_lock);
2373 }
2374
2375 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2376
2377 /*
2378 * sbridge_driver pci_driver structure for this module
2379 *
2380 */
2381 static struct pci_driver sbridge_driver = {
2382 .name = "sbridge_edac",
2383 .probe = sbridge_probe,
2384 .remove = sbridge_remove,
2385 .id_table = sbridge_pci_tbl,
2386 };
2387
2388 /*
2389 * sbridge_init Module entry function
2390 * Try to initialize this module for its devices
2391 */
sbridge_init(void)2392 static int __init sbridge_init(void)
2393 {
2394 int pci_rc;
2395
2396 edac_dbg(2, "\n");
2397
2398 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2399 opstate_init();
2400
2401 pci_rc = pci_register_driver(&sbridge_driver);
2402 if (pci_rc >= 0) {
2403 mce_register_decode_chain(&sbridge_mce_dec);
2404 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2405 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2406 return 0;
2407 }
2408
2409 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2410 pci_rc);
2411
2412 return pci_rc;
2413 }
2414
2415 /*
2416 * sbridge_exit() Module exit function
2417 * Unregister the driver
2418 */
sbridge_exit(void)2419 static void __exit sbridge_exit(void)
2420 {
2421 edac_dbg(2, "\n");
2422 pci_unregister_driver(&sbridge_driver);
2423 mce_unregister_decode_chain(&sbridge_mce_dec);
2424 }
2425
2426 module_init(sbridge_init);
2427 module_exit(sbridge_exit);
2428
2429 module_param(edac_op_state, int, 0444);
2430 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2431
2432 MODULE_LICENSE("GPL");
2433 MODULE_AUTHOR("Mauro Carvalho Chehab");
2434 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2435 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2436 SBRIDGE_REVISION);
2437