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Searched refs:pfb (Results 1 – 25 of 50) sorted by relevance

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/drivers/gpu/drm/nouveau/core/subdev/fb/
Dbase.c63 struct nouveau_fb *pfb = (void *)object; in _nouveau_fb_fini() local
66 ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); in _nouveau_fb_fini()
70 return nouveau_subdev_fini(&pfb->base, suspend); in _nouveau_fb_fini()
76 struct nouveau_fb *pfb = (void *)object; in _nouveau_fb_init() local
79 ret = nouveau_subdev_init(&pfb->base); in _nouveau_fb_init()
83 ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); in _nouveau_fb_init()
87 for (i = 0; i < pfb->tile.regions; i++) in _nouveau_fb_init()
88 pfb->tile.prog(pfb, i, &pfb->tile.region[i]); in _nouveau_fb_init()
96 struct nouveau_fb *pfb = (void *)object; in _nouveau_fb_dtor() local
99 for (i = 0; i < pfb->tile.regions; i++) in _nouveau_fb_dtor()
[all …]
Dramnv40.c38 nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) in nv40_ram_calc() argument
40 struct nouveau_bios *bios = nouveau_bios(pfb); in nv40_ram_calc()
41 struct nv40_ram *ram = (void *)pfb->ram; in nv40_ram_calc()
48 nv_error(pfb, "mclk pll data not found\n"); in nv40_ram_calc()
52 ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq, in nv40_ram_calc()
71 nv40_ram_prog(struct nouveau_fb *pfb) in nv40_ram_prog() argument
73 struct nouveau_bios *bios = nouveau_bios(pfb); in nv40_ram_prog()
74 struct nv40_ram *ram = (void *)pfb->ram; in nv40_ram_prog()
82 u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
85 if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) { in nv40_ram_prog()
[all …]
Dramnv50.c66 nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) in nv50_ram_calc() argument
68 struct nouveau_bios *bios = nouveau_bios(pfb); in nv50_ram_calc()
69 struct nv50_ram *ram = (void *)pfb->ram; in nv50_ram_calc()
88 nv_error(pfb, "invalid/missing perftab entry\n"); in nv50_ram_calc()
94 strap = nvbios_ramcfg_index(nv_subdev(pfb)); in nv50_ram_calc()
96 nv_error(pfb, "invalid ramcfg strap\n"); in nv50_ram_calc()
108 nv_error(pfb, "invalid/missing timing entry " in nv50_ram_calc()
117 ret = ram_init(hwsq, nv_subdev(pfb)); in nv50_ram_calc()
138 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, in nv50_ram_calc()
208 nv50_ram_prog(struct nouveau_fb *pfb) in nv50_ram_prog() argument
[all …]
Dramnvc0.c114 struct nouveau_fb *pfb = nouveau_fb(ram); in nvc0_ram_train() local
115 u32 part = nv_rd32(pfb, 0x022438), i; in nvc0_ram_train()
116 u32 mask = nv_rd32(pfb, 0x022554); in nvc0_ram_train()
130 nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) in nvc0_ram_calc() argument
132 struct nouveau_clock *clk = nouveau_clock(pfb); in nvc0_ram_calc()
133 struct nouveau_bios *bios = nouveau_bios(pfb); in nvc0_ram_calc()
134 struct nvc0_ram *ram = (void *)pfb->ram; in nvc0_ram_calc()
151 nv_error(pfb, "invalid/missing rammap entry\n"); in nvc0_ram_calc()
156 strap = nvbios_ramcfg_index(nv_subdev(pfb)); in nvc0_ram_calc()
158 nv_error(pfb, "invalid ramcfg strap\n"); in nvc0_ram_calc()
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Dnv20.c30 nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, in nv20_fb_tile_init() argument
37 pfb->tile.comp(pfb, i, size, flags, tile); in nv20_fb_tile_init()
43 nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, in nv20_fb_tile_comp() argument
47 u32 tags = round_up(tiles / pfb->ram->parts, 0x40); in nv20_fb_tile_comp()
48 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
60 nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv20_fb_tile_fini() argument
66 nouveau_mm_free(&pfb->tags, &tile->tag); in nv20_fb_tile_fini()
70 nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv20_fb_tile_prog() argument
72 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); in nv20_fb_tile_prog()
73 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); in nv20_fb_tile_prog()
[all …]
Dramnva3.c76 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) in nva3_ram_calc() argument
78 struct nouveau_bios *bios = nouveau_bios(pfb); in nva3_ram_calc()
79 struct nva3_ram *ram = (void *)pfb->ram; in nva3_ram_calc()
103 nv_error(pfb, "invalid/missing rammap entry\n"); in nva3_ram_calc()
108 strap = nvbios_ramcfg_index(nv_subdev(pfb)); in nva3_ram_calc()
110 nv_error(pfb, "invalid ramcfg strap\n"); in nva3_ram_calc()
117 nv_error(pfb, "invalid/missing ramcfg entry\n"); in nva3_ram_calc()
127 nv_error(pfb, "invalid/missing timing entry\n"); in nva3_ram_calc()
132 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); in nva3_ram_calc()
134 nv_error(pfb, "failed mclk calculation\n"); in nva3_ram_calc()
[all …]
Dramnve0.c257 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) in nve0_ram_calc_gddr5() argument
259 struct nve0_ram *ram = (void *)pfb->ram; in nve0_ram_calc_gddr5()
683 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) in nve0_ram_calc_sddr3() argument
685 struct nve0_ram *ram = (void *)pfb->ram; in nve0_ram_calc_sddr3()
935 nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, in nve0_ram_calc_data() argument
938 struct nve0_ram *ram = (void *)pfb->ram; in nve0_ram_calc_data()
956 nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) in nve0_ram_calc_xits() argument
958 struct nve0_ram *ram = (void *)pfb->ram; in nve0_ram_calc_xits()
963 ret = ram_init(fuc, pfb); in nve0_ram_calc_xits()
983 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, in nve0_ram_calc_xits()
[all …]
Dnv10.c30 nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, in nv10_fb_tile_init() argument
39 nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv10_fb_tile_fini() argument
48 nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv10_fb_tile_prog() argument
50 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); in nv10_fb_tile_prog()
51 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); in nv10_fb_tile_prog()
52 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); in nv10_fb_tile_prog()
53 nv_rd32(pfb, 0x100240 + (i * 0x10)); in nv10_fb_tile_prog()
Dramgk20a.c35 gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) in gk20a_ram_put() argument
37 struct device *dev = nv_device_base(nv_device(pfb)); in gk20a_ram_put()
53 gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, in gk20a_ram_get() argument
56 struct device *dev = nv_device_base(nv_device(pfb)); in gk20a_ram_get()
62 nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size, in gk20a_ram_get()
100 nv_error(pfb, "%s: cannot allocate memory!\n", __func__); in gk20a_ram_get()
101 gk20a_ram_put(pfb, pmem); in gk20a_ram_get()
109 nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n", in gk20a_ram_get()
112 nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n", in gk20a_ram_get()
Dnv41.c30 nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv41_fb_tile_prog() argument
32 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
33 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
34 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
35 nv_rd32(pfb, 0x100600 + (i * 0x10)); in nv41_fb_tile_prog()
36 nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
Dnv44.c30 nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, in nv44_fb_tile_init() argument
40 nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) in nv44_fb_tile_prog() argument
42 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
43 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
44 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
45 nv_rd32(pfb, 0x100600 + (i * 0x10)); in nv44_fb_tile_prog()
Dramnv20.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv20_ram_create() local
34 u32 pbus1218 = nv_rd32(pfb, 0x001218); in nv20_ram_create()
48 ram->size = (nv_rd32(pfb, 0x10020c) & 0xff000000); in nv20_ram_create()
49 ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv20_ram_create()
50 ram->tags = nv_rd32(pfb, 0x100320); in nv20_ram_create()
Dpriv.h45 struct nouveau_fb *pfb = (p); \
46 _nouveau_fb_dtor(nv_object(pfb)); \
49 struct nouveau_fb *pfb = (p); \
50 _nouveau_fb_init(nv_object(pfb)); \
53 struct nouveau_fb *pfb = (p); \
54 _nouveau_fb_fini(nv_object(pfb), (s)); \
Dnv30.c30 nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, in nv30_fb_tile_init() argument
37 if (pfb->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 pfb->tile.comp(pfb, i, size, flags, tile); in nv30_fb_tile_init()
49 nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, in nv30_fb_tile_comp() argument
53 u32 tags = round_up(tiles / pfb->ram->parts, 0x40); in nv30_fb_tile_comp()
54 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv30_fb_tile_comp()
Dramnv49.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv49_ram_create() local
34 u32 pfb914 = nv_rd32(pfb, 0x100914); in nv49_ram_create()
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv49_ram_create()
50 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv49_ram_create()
51 ram->base.tags = nv_rd32(pfb, 0x100320); in nv49_ram_create()
Dramfuc.h8 struct nouveau_fb *pfb; member
58 ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb) in ramfuc_init() argument
60 struct nouveau_pwr *ppwr = nouveau_pwr(pfb); in ramfuc_init()
68 ram->pfb = pfb; in ramfuc_init()
76 if (ram->pfb) { in ramfuc_exec()
78 ram->pfb = NULL; in ramfuc_exec()
87 reg->data = nv_rd32(ram->pfb, reg->addr); in ramfuc_rd32()
Dramnv41.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv41_ram_create() local
34 u32 pfb474 = nv_rd32(pfb, 0x100474); in nv41_ram_create()
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv41_ram_create()
50 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv41_ram_create()
51 ram->base.tags = nv_rd32(pfb, 0x100320); in nv41_ram_create()
Dramnvaa.c34 struct nouveau_fb *pfb = nouveau_fb(parent); in nvaa_ram_ctor() local
43 ram->size = nv_rd32(pfb, 0x10020c); in nvaa_ram_ctor()
46 ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - in nvaa_ram_ctor()
52 ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; in nvaa_ram_ctor()
Dramnv10.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv10_ram_create() local
34 u32 cfg0 = nv_rd32(pfb, 0x100200); in nv10_ram_create()
47 ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv10_ram_create()
Dramnv1a.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv1a_ram_create() local
40 nv_fatal(pfb, "no bridge device\n"); in nv1a_ram_create()
49 if (nv_device(pfb)->chipset == 0x1a) { in nv1a_ram_create()
Dramnv44.c32 struct nouveau_fb *pfb = nouveau_fb(parent); in nv44_ram_create() local
34 u32 pfb474 = nv_rd32(pfb, 0x100474); in nv44_ram_create()
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv44_ram_create()
/drivers/nfc/st21nfca/
Dst21nfca_dep.c32 #define ST21NFCA_NFC_DEP_PFB_PNI(pfb) ((pfb) & 0x03) argument
33 #define ST21NFCA_NFC_DEP_PFB_TYPE(pfb) ((pfb) & 0xE0) argument
34 #define ST21NFCA_NFC_DEP_PFB_IS_TIMEOUT(pfb) \ argument
35 ((pfb) & ST21NFCA_NFC_DEP_PFB_TIMEOUT_BIT)
36 #define ST21NFCA_NFC_DEP_DID_BIT_SET(pfb) ((pfb) & 0x04) argument
37 #define ST21NFCA_NFC_DEP_NAD_BIT_SET(pfb) ((pfb) & 0x08) argument
40 #define ST21NFCA_NFC_DEP_PFB_IS_TIMEOUT(pfb) \ argument
41 ((pfb) & ST21NFCA_NFC_DEP_PFB_TIMEOUT_BIT)
111 u8 pfb; member
344 if (ST21NFCA_NFC_DEP_DID_BIT_SET(dep_req->pfb)) in st21nfca_tm_recv_dep_req()
[all …]
/drivers/gpu/drm/nouveau/
Dnouveau_ttm.c36 struct nouveau_fb *pfb = nvkm_fb(&drm->device); in nouveau_vram_manager_init() local
37 man->priv = pfb; in nouveau_vram_manager_init()
67 struct nouveau_fb *pfb = nvkm_fb(&drm->device); in nouveau_vram_manager_del() local
69 pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node); in nouveau_vram_manager_del()
79 struct nouveau_fb *pfb = nvkm_fb(&drm->device); in nouveau_vram_manager_new() local
88 ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT, in nouveau_vram_manager_new()
106 struct nouveau_fb *pfb = man->priv; in nouveau_vram_manager_debug() local
107 struct nouveau_mm *mm = &pfb->vram; in nouveau_vram_manager_debug()
111 mutex_lock(&nv_subdev(pfb)->mutex); in nouveau_vram_manager_debug()
121 mutex_unlock(&nv_subdev(pfb)->mutex); in nouveau_vram_manager_debug()
/drivers/gpu/drm/nouveau/core/subdev/ltc/
Dgf100.c135 struct nouveau_fb *pfb = nouveau_fb(object); in gf100_ltc_dtor() local
139 nouveau_mm_free(&pfb->vram, &priv->tag_ram); in gf100_ltc_dtor()
147 gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) in gf100_ltc_init_tag_ram() argument
153 priv->num_tags = (pfb->ram->size >> 17) / 4; in gf100_ltc_init_tag_ram()
173 ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, in gf100_ltc_init_tag_ram()
195 struct nouveau_fb *pfb = nouveau_fb(parent); in gf100_ltc_ctor() local
213 ret = gf100_ltc_init_tag_ram(pfb, priv); in gf100_ltc_ctor()
/drivers/gpu/drm/nouveau/core/subdev/instmem/
Dnv50.c87 struct nouveau_fb *pfb = nouveau_fb(object); in nv50_instobj_dtor() local
88 pfb->ram->put(pfb, &node->mem); in nv50_instobj_dtor()
97 struct nouveau_fb *pfb = nouveau_fb(parent); in nv50_instobj_ctor() local
110 ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem); in nv50_instobj_ctor()

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