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Searched refs:pll2 (Results 1 – 7 of 7) sorted by relevance

/drivers/mfd/
Dsm501.c117 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
122 pll2 = 288 * MHZ; in decode_div()
124 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
141 unsigned long pll2 = 0; in sm501_dump_clk() local
145 pll2 = 336 * MHZ; in sm501_dump_clk()
148 pll2 = 288 * MHZ; in sm501_dump_clk()
151 pll2 = 240 * MHZ; in sm501_dump_clk()
154 pll2 = 192 * MHZ; in sm501_dump_clk()
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
/drivers/gpu/drm/nouveau/core/subdev/devinit/
Dnv04.c202 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
212 pll2 = 0; in setPLL_double_highregs()
221 pll2 |= 0x011f; in setPLL_double_highregs()
227 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
260 nv_wr32(devinit, reg2, pll2); in setPLL_double_highregs()
/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c133 uint32_t pll2, struct nouveau_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/drivers/clk/mxs/
Dclk-imx28.c139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
/drivers/clk/sirf/
Dclk-prima2.c62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
Dclk-atlas6.c63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
/drivers/clk/qcom/
Dmmcc-msm8960.c84 static struct clk_pll pll2 = { variable
2368 [PLL2] = &pll2.clkr,
2528 [PLL2] = &pll2.clkr,