1 /*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include <subdev/vga.h>
28
29 #include "fbmem.h"
30 #include "nv04.h"
31
32 static void
nv04_devinit_meminit(struct nouveau_devinit * devinit)33 nv04_devinit_meminit(struct nouveau_devinit *devinit)
34 {
35 struct nv04_devinit_priv *priv = (void *)devinit;
36 u32 patt = 0xdeadbeef;
37 struct io_mapping *fb;
38 int i;
39
40 /* Map the framebuffer aperture */
41 fb = fbmem_init(nv_device(priv));
42 if (!fb) {
43 nv_error(priv, "failed to map fb\n");
44 return;
45 }
46
47 /* Sequencer and refresh off */
48 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
49 nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
50
51 nv_mask(priv, NV04_PFB_BOOT_0, ~0,
52 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
53 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
54 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
55
56 for (i = 0; i < 4; i++)
57 fbmem_poke(fb, 4 * i, patt);
58
59 fbmem_poke(fb, 0x400000, patt + 1);
60
61 if (fbmem_peek(fb, 0) == patt + 1) {
62 nv_mask(priv, NV04_PFB_BOOT_0,
63 NV04_PFB_BOOT_0_RAM_TYPE,
64 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
65 nv_mask(priv, NV04_PFB_DEBUG_0,
66 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
67
68 for (i = 0; i < 4; i++)
69 fbmem_poke(fb, 4 * i, patt);
70
71 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
72 nv_mask(priv, NV04_PFB_BOOT_0,
73 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
74 NV04_PFB_BOOT_0_RAM_AMOUNT,
75 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
76 } else
77 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
78 nv_mask(priv, NV04_PFB_BOOT_0,
79 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
80 NV04_PFB_BOOT_0_RAM_AMOUNT,
81 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
82 } else
83 if (fbmem_peek(fb, 0) != patt) {
84 if (fbmem_readback(fb, 0x800000, patt))
85 nv_mask(priv, NV04_PFB_BOOT_0,
86 NV04_PFB_BOOT_0_RAM_AMOUNT,
87 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
88 else
89 nv_mask(priv, NV04_PFB_BOOT_0,
90 NV04_PFB_BOOT_0_RAM_AMOUNT,
91 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
92
93 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
94 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
95 } else
96 if (!fbmem_readback(fb, 0x800000, patt)) {
97 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
98 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
99
100 }
101
102 /* Refresh on, sequencer on */
103 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
104 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
105 fbmem_fini(fb);
106 }
107
108 static int
powerctrl_1_shift(int chip_version,int reg)109 powerctrl_1_shift(int chip_version, int reg)
110 {
111 int shift = -4;
112
113 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
114 return shift;
115
116 switch (reg) {
117 case 0x680520:
118 shift += 4;
119 case 0x680508:
120 shift += 4;
121 case 0x680504:
122 shift += 4;
123 case 0x680500:
124 shift += 4;
125 }
126
127 /*
128 * the shift for vpll regs is only used for nv3x chips with a single
129 * stage pll
130 */
131 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
132 chip_version == 0x36 || chip_version >= 0x40))
133 shift = -4;
134
135 return shift;
136 }
137
138 void
setPLL_single(struct nouveau_devinit * devinit,u32 reg,struct nouveau_pll_vals * pv)139 setPLL_single(struct nouveau_devinit *devinit, u32 reg,
140 struct nouveau_pll_vals *pv)
141 {
142 int chip_version = nouveau_bios(devinit)->version.chip;
143 uint32_t oldpll = nv_rd32(devinit, reg);
144 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
145 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
146 uint32_t saved_powerctrl_1 = 0;
147 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
148
149 if (oldpll == pll)
150 return; /* already set */
151
152 if (shift_powerctrl_1 >= 0) {
153 saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
154 nv_wr32(devinit, 0x001584,
155 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
156 1 << shift_powerctrl_1);
157 }
158
159 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
160 /* upclock -- write new post divider first */
161 nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));
162 else
163 /* downclock -- write new NM first */
164 nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);
165
166 if ((chip_version < 0x17 || chip_version == 0x1a) &&
167 chip_version != 0x11)
168 /* wait a bit on older chips */
169 msleep(64);
170 nv_rd32(devinit, reg);
171
172 /* then write the other half as well */
173 nv_wr32(devinit, reg, pll);
174
175 if (shift_powerctrl_1 >= 0)
176 nv_wr32(devinit, 0x001584, saved_powerctrl_1);
177 }
178
179 static uint32_t
new_ramdac580(uint32_t reg1,bool ss,uint32_t ramdac580)180 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
181 {
182 bool head_a = (reg1 == 0x680508);
183
184 if (ss) /* single stage pll mode */
185 ramdac580 |= head_a ? 0x00000100 : 0x10000000;
186 else
187 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
188
189 return ramdac580;
190 }
191
192 void
setPLL_double_highregs(struct nouveau_devinit * devinit,u32 reg1,struct nouveau_pll_vals * pv)193 setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
194 struct nouveau_pll_vals *pv)
195 {
196 int chip_version = nouveau_bios(devinit)->version.chip;
197 bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
198 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
199 uint32_t oldpll1 = nv_rd32(devinit, reg1);
200 uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0;
201 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
202 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
203 uint32_t oldramdac580 = 0, ramdac580 = 0;
204 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
205 uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
206 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
207
208 /* model specific additions to generic pll1 and pll2 set up above */
209 if (nv3035) {
210 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
211 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
212 pll2 = 0;
213 }
214 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
215 oldramdac580 = nv_rd32(devinit, 0x680580);
216 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
217 if (oldramdac580 != ramdac580)
218 oldpll1 = ~0; /* force mismatch */
219 if (single_stage)
220 /* magic value used by nvidia in single stage mode */
221 pll2 |= 0x011f;
222 }
223 if (chip_version > 0x70)
224 /* magic bits set by the blob (but not the bios) on g71-73 */
225 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
226
227 if (oldpll1 == pll1 && oldpll2 == pll2)
228 return; /* already set */
229
230 if (shift_powerctrl_1 >= 0) {
231 saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
232 nv_wr32(devinit, 0x001584,
233 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
234 1 << shift_powerctrl_1);
235 }
236
237 if (chip_version >= 0x40) {
238 int shift_c040 = 14;
239
240 switch (reg1) {
241 case 0x680504:
242 shift_c040 += 2;
243 case 0x680500:
244 shift_c040 += 2;
245 case 0x680520:
246 shift_c040 += 2;
247 case 0x680508:
248 shift_c040 += 2;
249 }
250
251 savedc040 = nv_rd32(devinit, 0xc040);
252 if (shift_c040 != 14)
253 nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040));
254 }
255
256 if (oldramdac580 != ramdac580)
257 nv_wr32(devinit, 0x680580, ramdac580);
258
259 if (!nv3035)
260 nv_wr32(devinit, reg2, pll2);
261 nv_wr32(devinit, reg1, pll1);
262
263 if (shift_powerctrl_1 >= 0)
264 nv_wr32(devinit, 0x001584, saved_powerctrl_1);
265 if (chip_version >= 0x40)
266 nv_wr32(devinit, 0xc040, savedc040);
267 }
268
269 void
setPLL_double_lowregs(struct nouveau_devinit * devinit,u32 NMNMreg,struct nouveau_pll_vals * pv)270 setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
271 struct nouveau_pll_vals *pv)
272 {
273 /* When setting PLLs, there is a merry game of disabling and enabling
274 * various bits of hardware during the process. This function is a
275 * synthesis of six nv4x traces, nearly each card doing a subtly
276 * different thing. With luck all the necessary bits for each card are
277 * combined herein. Without luck it deviates from each card's formula
278 * so as to not work on any :)
279 */
280
281 uint32_t Preg = NMNMreg - 4;
282 bool mpll = Preg == 0x4020;
283 uint32_t oldPval = nv_rd32(devinit, Preg);
284 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
285 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
286 0xc << 28 | pv->log2P << 16;
287 uint32_t saved4600 = 0;
288 /* some cards have different maskc040s */
289 uint32_t maskc040 = ~(3 << 14), savedc040;
290 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
291
292 if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
293 return;
294
295 if (Preg == 0x4000)
296 maskc040 = ~0x333;
297 if (Preg == 0x4058)
298 maskc040 = ~(0xc << 24);
299
300 if (mpll) {
301 struct nvbios_pll info;
302 uint8_t Pval2;
303
304 if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
305 return;
306
307 Pval2 = pv->log2P + info.bias_p;
308 if (Pval2 > info.max_p)
309 Pval2 = info.max_p;
310 Pval |= 1 << 28 | Pval2 << 20;
311
312 saved4600 = nv_rd32(devinit, 0x4600);
313 nv_wr32(devinit, 0x4600, saved4600 | 8 << 28);
314 }
315 if (single_stage)
316 Pval |= mpll ? 1 << 12 : 1 << 8;
317
318 nv_wr32(devinit, Preg, oldPval | 1 << 28);
319 nv_wr32(devinit, Preg, Pval & ~(4 << 28));
320 if (mpll) {
321 Pval |= 8 << 20;
322 nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28));
323 nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28));
324 }
325
326 savedc040 = nv_rd32(devinit, 0xc040);
327 nv_wr32(devinit, 0xc040, savedc040 & maskc040);
328
329 nv_wr32(devinit, NMNMreg, NMNM);
330 if (NMNMreg == 0x4024)
331 nv_wr32(devinit, 0x403c, NMNM);
332
333 nv_wr32(devinit, Preg, Pval);
334 if (mpll) {
335 Pval &= ~(8 << 20);
336 nv_wr32(devinit, 0x4020, Pval);
337 nv_wr32(devinit, 0x4038, Pval);
338 nv_wr32(devinit, 0x4600, saved4600);
339 }
340
341 nv_wr32(devinit, 0xc040, savedc040);
342
343 if (mpll) {
344 nv_wr32(devinit, 0x4020, Pval & ~(1 << 28));
345 nv_wr32(devinit, 0x4038, Pval & ~(1 << 28));
346 }
347 }
348
349 int
nv04_devinit_pll_set(struct nouveau_devinit * devinit,u32 type,u32 freq)350 nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
351 {
352 struct nouveau_bios *bios = nouveau_bios(devinit);
353 struct nouveau_pll_vals pv;
354 struct nvbios_pll info;
355 int cv = bios->version.chip;
356 int N1, M1, N2, M2, P;
357 int ret;
358
359 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
360 if (ret)
361 return ret;
362
363 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
364 &N1, &M1, &N2, &M2, &P);
365 if (!ret)
366 return -EINVAL;
367
368 pv.refclk = info.refclk;
369 pv.N1 = N1;
370 pv.M1 = M1;
371 pv.N2 = N2;
372 pv.M2 = M2;
373 pv.log2P = P;
374
375 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
376 cv >= 0x40) {
377 if (type > 0x405c)
378 setPLL_double_highregs(devinit, type, &pv);
379 else
380 setPLL_double_lowregs(devinit, type, &pv);
381 } else
382 setPLL_single(devinit, type, &pv);
383
384 return 0;
385 }
386
387 int
nv04_devinit_fini(struct nouveau_object * object,bool suspend)388 nv04_devinit_fini(struct nouveau_object *object, bool suspend)
389 {
390 struct nv04_devinit_priv *priv = (void *)object;
391 int ret;
392
393 /* make i2c busses accessible */
394 nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
395
396 ret = nouveau_devinit_fini(&priv->base, suspend);
397 if (ret)
398 return ret;
399
400 /* unslave crtcs */
401 if (priv->owner < 0)
402 priv->owner = nv_rdvgaowner(priv);
403 nv_wrvgaowner(priv, 0);
404
405 return 0;
406 }
407
408 int
nv04_devinit_init(struct nouveau_object * object)409 nv04_devinit_init(struct nouveau_object *object)
410 {
411 struct nv04_devinit_priv *priv = (void *)object;
412
413 if (!priv->base.post) {
414 u32 htotal = nv_rdvgac(priv, 0, 0x06);
415 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
416 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
417 htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
418 htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
419 if (!htotal) {
420 nv_info(priv, "adaptor not initialised\n");
421 priv->base.post = true;
422 }
423 }
424
425 return nouveau_devinit_init(&priv->base);
426 }
427
428 void
nv04_devinit_dtor(struct nouveau_object * object)429 nv04_devinit_dtor(struct nouveau_object *object)
430 {
431 struct nv04_devinit_priv *priv = (void *)object;
432
433 /* restore vga owner saved at first init */
434 nv_wrvgaowner(priv, priv->owner);
435
436 nouveau_devinit_destroy(&priv->base);
437 }
438
439 int
nv04_devinit_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)440 nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
441 struct nouveau_oclass *oclass, void *data, u32 size,
442 struct nouveau_object **pobject)
443 {
444 struct nv04_devinit_priv *priv;
445 int ret;
446
447 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
448 *pobject = nv_object(priv);
449 if (ret)
450 return ret;
451
452 priv->owner = -1;
453 return 0;
454 }
455
456 struct nouveau_oclass *
457 nv04_devinit_oclass = &(struct nouveau_devinit_impl) {
458 .base.handle = NV_SUBDEV(DEVINIT, 0x04),
459 .base.ofuncs = &(struct nouveau_ofuncs) {
460 .ctor = nv04_devinit_ctor,
461 .dtor = nv04_devinit_dtor,
462 .init = nv04_devinit_init,
463 .fini = nv04_devinit_fini,
464 },
465 .meminit = nv04_devinit_meminit,
466 .pll_set = nv04_devinit_pll_set,
467 }.base;
468