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Searched refs:sarea_priv (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/mga/
Dmga_state.c46 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_emit_clip_rect() local
47 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; in mga_emit_clip_rect()
70 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g200_emit_context() local
71 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; in mga_g200_emit_context()
93 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g400_emit_context() local
94 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; in mga_g400_emit_context()
120 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g200_emit_tex0() local
121 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; in mga_g200_emit_tex0()
148 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g400_emit_tex0() local
149 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; in mga_g400_emit_tex0()
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Dmga_dma.c77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset() local
88 sarea_priv->last_wrap = 0; in mga_do_dma_reset()
201 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_wrap_end() local
205 sarea_priv->last_wrap++; in mga_do_dma_wrap_end()
206 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); in mga_do_dma_wrap_end()
230 dev_priv->sarea_priv->last_dispatch, in mga_freelist_print()
332 wrap = dev_priv->sarea_priv->last_wrap; in mga_freelist_get()
857 dev_priv->sarea_priv = in mga_do_init_dma()
911 dev_priv->sarea_priv->last_wrap = 0; in mga_do_init_dma()
912 dev_priv->sarea_priv->last_frame.head = 0; in mga_do_init_dma()
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Dmga_drv.h81 drm_mga_sarea_t *sarea_priv; member
353 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
/drivers/gpu/drm/r128/
Dr128_state.c84 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; in r128_emit_core() local
85 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; in r128_emit_core()
99 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; in r128_emit_context() local
100 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; in r128_emit_context()
125 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; in r128_emit_setup() local
126 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; in r128_emit_setup()
141 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; in r128_emit_masks() local
142 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; in r128_emit_masks()
160 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; in r128_emit_window() local
161 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; in r128_emit_window()
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Dr128_drv.h83 drm_r128_sarea_t *sarea_priv; member
455 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
456 if (sarea_priv->last_dispatch >= R128_MAX_VB_AGE) { \
460 sarea_priv->last_dispatch = 0; \
Dr128_cce.c504 dev_priv->sarea_priv = in r128_do_init_cce()
549 dev_priv->sarea_priv->last_frame = 0; in r128_do_init_cce()
550 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); in r128_do_init_cce()
552 dev_priv->sarea_priv->last_dispatch = 0; in r128_do_init_cce()
553 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); in r128_do_init_cce()
/drivers/gpu/drm/i810/
Di810_dma.c353 dev_priv->sarea_priv = (drm_i810_sarea_t *) in i810_dma_initialize()
559 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; in i810EmitState() local
560 unsigned int dirty = sarea_priv->dirty; in i810EmitState()
565 i810EmitDestVerified(dev, sarea_priv->BufferState); in i810EmitState()
566 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; in i810EmitState()
570 i810EmitContextVerified(dev, sarea_priv->ContextState); in i810EmitState()
571 sarea_priv->dirty &= ~I810_UPLOAD_CTX; in i810EmitState()
575 i810EmitTexVerified(dev, sarea_priv->TexState[0]); in i810EmitState()
576 sarea_priv->dirty &= ~I810_UPLOAD_TEX0; in i810EmitState()
580 i810EmitTexVerified(dev, sarea_priv->TexState[1]); in i810EmitState()
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Di810_drv.h85 drm_i810_sarea_t *sarea_priv; member
/drivers/gpu/drm/radeon/
Dradeon_state.c774 x += master_priv->sarea_priv->boxes[0].x1; in radeon_clear_box()
775 y += master_priv->sarea_priv->boxes[0].y1; in radeon_clear_box()
803 if (master_priv->sarea_priv->pfCurrentPage == 1) { in radeon_clear_box()
881 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; in radeon_cp_dispatch_clear() local
883 int nbox = sarea_priv->nbox; in radeon_cp_dispatch_clear()
884 struct drm_clip_rect *pbox = sarea_priv->boxes; in radeon_cp_dispatch_clear()
893 if (sarea_priv->pfCurrentPage == 1) { in radeon_cp_dispatch_clear()
925 sarea_priv->ctx_owner = 0; in radeon_cp_dispatch_clear()
1002 sarea_priv->ctx_owner = 0; in radeon_cp_dispatch_clear()
1249 sarea_priv->ctx_owner = 0; in radeon_cp_dispatch_clear()
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Dr600_cp.c1927 if (master_priv->sarea_priv) { in r600_cp_init_ring_buffer()
1928 master_priv->sarea_priv->last_frame = 0; in r600_cp_init_ring_buffer()
1929 master_priv->sarea_priv->last_dispatch = 0; in r600_cp_init_ring_buffer()
1930 master_priv->sarea_priv->last_clear = 0; in r600_cp_init_ring_buffer()
2422 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; in r600_cp_dispatch_swap() local
2423 int nbox = sarea_priv->nbox; in r600_cp_dispatch_swap()
2424 struct drm_clip_rect *pbox = sarea_priv->boxes; in r600_cp_dispatch_swap()
2435 if (sarea_priv->pfCurrentPage == 0) { in r600_cp_dispatch_swap()
2470 sarea_priv->last_frame++; in r600_cp_dispatch_swap()
2473 R600_FRAME_AGE(sarea_priv->last_frame); in r600_cp_dispatch_swap()
Dradeon_cp.c848 if (master_priv->sarea_priv) { in radeon_cp_init_ring_buffer()
849 master_priv->sarea_priv->last_frame = 0; in radeon_cp_init_ring_buffer()
850 master_priv->sarea_priv->last_dispatch = 0; in radeon_cp_init_ring_buffer()
851 master_priv->sarea_priv->last_clear = 0; in radeon_cp_init_ring_buffer()
2145 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); in radeon_master_create()
2146 master_priv->sarea_priv->pfCurrentPage = 0; in radeon_master_create()
2159 if (master_priv->sarea_priv && in radeon_master_destroy()
2160 master_priv->sarea_priv->pfCurrentPage != 0) in radeon_master_destroy()
2163 master_priv->sarea_priv = NULL; in radeon_master_destroy()
Dradeon_drv.h196 drm_radeon_sarea_t *sarea_priv; member
2011 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
2012 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
2019 sarea_priv->last_dispatch = 0; \
Dr300_cmdbuf.c856 buf_priv->age = ++master_priv->sarea_priv->last_dispatch; in r300_discard_buffer()
1179 RADEON_DISPATCH_AGE(master_priv->sarea_priv->last_dispatch); in r300_do_cp_cmdbuf()
/drivers/gpu/drm/via/
Dvia_video.c40 XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0; in via_init_futex()
53 if (!dev_priv->sarea_priv) in via_release_futex()
57 lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i); in via_release_futex()
73 drm_via_sarea_t *sAPriv = dev_priv->sarea_priv; in via_decoder_futex()
Dvia_map.c57 dev_priv->sarea_priv = in via_do_init_map()
Dvia_drv.h63 drm_via_sarea_t *sarea_priv; member
/drivers/gpu/drm/i915/
Di915_dma.c103 if (master_priv->sarea_priv) in i915_update_dri1_breadcrumb()
104 master_priv->sarea_priv->last_dispatch = in i915_update_dri1_breadcrumb()
167 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv) in i915_kernel_lost_context()
168 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; in i915_kernel_lost_context()
203 master_priv->sarea_priv = (drm_i915_sarea_t *) in i915_initialize()
230 if (master_priv->sarea_priv) in i915_initialize()
231 master_priv->sarea_priv->pf_current_page = 0; in i915_initialize()
447 if (master_priv->sarea_priv) in i915_emit_breadcrumb()
448 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; in i915_emit_breadcrumb()
562 if (!master_priv->sarea_priv) in i915_dispatch_flip()
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Dintel_ringbuffer.c1921 if (master_priv->sarea_priv) in ring_wait_for_space()
1922 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; in ring_wait_for_space()
Di915_drv.h297 struct _drm_i915_sarea *sarea_priv; member
Dintel_display.c5019 if (!master_priv->sarea_priv) in intel_crtc_update_sarea()
5024 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; in intel_crtc_update_sarea()
5025 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; in intel_crtc_update_sarea()
5028 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; in intel_crtc_update_sarea()
5029 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; in intel_crtc_update_sarea()
/drivers/gpu/drm/savage/
Dsavage_drv.h130 drm_savage_sarea_t *sarea_priv; member
Dsavage_bci.c806 dev_priv->sarea_priv = in savage_do_init_bci()