| /drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 896 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
908 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
941 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
952 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1438 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1624 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1627 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1851 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1933 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1958 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | sumo_dpm.c | 825 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
841 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
859 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1798 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1821 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1829 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 912 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
927 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
942 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
954 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | rv770_dpm.c | 1437 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1444 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1454 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1461 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2150 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2153 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2158 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2159 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2436 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2480 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1519 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.h | 69 u32 vclk; member
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| D | radeon_asic.h | 412 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
474 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
531 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
532 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
731 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
758 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | rv770.c | 44 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
53 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
60 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
66 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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| D | ni_dpm.c | 3515 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3523 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3533 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3541 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3902 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3905 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3908 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
4286 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4314 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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| D | kv_dpm.c | 835 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
840 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); in kv_populate_uvd_table()
845 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
2219 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2592 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2595 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2829 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
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| D | si_dpm.c | 2275 radeon_state->vclk && radeon_state->dclk) in si_should_disable_uvd_powertune()
3019 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5148 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) in si_is_state_ulv_compatible()
5185 if (radeon_state->vclk && radeon_state->dclk) { in si_convert_power_state_to_smc()
6301 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in si_parse_pplib_non_clock_info()
6304 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in si_parse_pplib_non_clock_info()
6307 rps->vclk = 0; in si_parse_pplib_non_clock_info()
6660 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
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| D | radeon.h | 1330 u32 vclk; member
1416 u32 vclk; member
1671 unsigned vclk, unsigned dclk,
1923 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | evergreen.c | 1063 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in sumo_set_uvd_clocks() argument
1068 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); in sumo_set_uvd_clocks()
1072 cg_scratch |= vclk / 100; /* Mhz */ in sumo_set_uvd_clocks()
1086 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in evergreen_set_uvd_clocks() argument
1100 if (!vclk || !dclk) { in evergreen_set_uvd_clocks()
1106 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in evergreen_set_uvd_clocks()
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| D | ci_dpm.c | 2193 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
4867 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ci_parse_pplib_non_clock_info()
4870 rps->vclk = 0; in ci_parse_pplib_non_clock_info()
5303 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ci_dpm_print_power_state()
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| D | r600.c | 123 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in r600_set_uvd_clocks() argument
141 if (!vclk || !dclk) { in r600_set_uvd_clocks()
152 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in r600_set_uvd_clocks()
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| D | r600_dpm.c | 1149 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in r600_parse_extended_power_table()
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| /drivers/video/fbdev/via/ |
| D | vt1636.c | 200 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
224 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
241 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| D | chip.h | 155 u32 vclk; /*panel mode clock value */ member
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| D | lcd.c | 566 plvds_setting_info->vclk = clock; in viafb_lcd_set_mode()
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| /drivers/video/fbdev/aty/ |
| D | aty128fb.c | 440 u32 vclk; member
1386 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1390 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1393 if (vclk > c.ppll_max) in aty128_var_to_pll()
1394 vclk = c.ppll_max; in aty128_var_to_pll()
1395 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1396 vclk = c.ppll_min/12; in aty128_var_to_pll()
1400 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1415 pll->vclk = vclk; in aty128_var_to_pll()
1419 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
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| D | radeon_base.c | 462 unsigned long long hz, vclk; in radeon_probe_pll_params() local
506 vclk = (long long)hTotal * (long long)vTotal * hz; in radeon_probe_pll_params()
558 vclk *= denom; in radeon_probe_pll_params()
559 do_div(vclk, 1000 * num); in radeon_probe_pll_params()
560 xtal = vclk; in radeon_probe_pll_params()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 253 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| D | hw.h | 57 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
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| /drivers/video/fbdev/ |
| D | tridentfb.c | 1016 unsigned long vclk; in tridentfb_set_par() local
1176 vclk = PICOS2KHZ(info->var.pixclock); in tridentfb_set_par()
1182 vclk *= 2; in tridentfb_set_par()
1184 set_vclk(par, vclk); in tridentfb_set_par()
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