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Searched refs:uint32_t (Results 1 – 25 of 122) sorted by relevance

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/include/uapi/linux/
Dfuse.h155 uint32_t atimensec;
156 uint32_t mtimensec;
157 uint32_t ctimensec;
158 uint32_t mode;
159 uint32_t nlink;
160 uint32_t uid;
161 uint32_t gid;
162 uint32_t rdev;
163 uint32_t blksize;
164 uint32_t padding;
[all …]
Dwil6210_uapi.h75 uint32_t op; /* enum wil_memio_op */
76 uint32_t addr; /* should be 32-bit aligned */
77 uint32_t val;
81 uint32_t op; /* enum wil_memio_op */
82 uint32_t addr; /* should be 32-bit aligned */
83 uint32_t size; /* should be multiple of 4 */
/include/uapi/drm/
Dvmwgfx_drm.h112 uint32_t param;
113 uint32_t pad64;
135 uint32_t pad64;
177 uint32_t flags;
178 uint32_t format;
179 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
213 uint32_t width;
214 uint32_t height;
215 uint32_t depth;
216 uint32_t pad64;
[all …]
Dqxl_drm.h51 uint32_t size;
52 uint32_t handle; /* 0 is an invalid handle */
57 uint32_t handle;
58 uint32_t pad;
73 uint32_t src_handle; /* dest handle to compute address from */
74 uint32_t dst_handle; /* 0 if to command buffer */
75 uint32_t reloc_type;
76 uint32_t pad;
82 uint32_t type;
83 uint32_t command_size;
[all …]
Dnouveau_drm.h51 uint32_t handle;
52 uint32_t domain;
56 uint32_t tile_mode;
57 uint32_t tile_flags;
62 uint32_t channel_hint;
63 uint32_t align;
68 uint32_t valid;
69 uint32_t domain;
75 uint32_t handle;
76 uint32_t read_domains;
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Dmsm_drm.h56 uint32_t pipe; /* in, MSM_PIPE_x */
57 uint32_t param; /* in, MSM_PARAM_x */
81 uint32_t flags; /* in, mask of MSM_BO_x */
82 uint32_t handle; /* out */
86 uint32_t handle; /* in */
87 uint32_t pad;
98 uint32_t handle; /* in */
99 uint32_t op; /* in, mask of MSM_PREP_x */
104 uint32_t handle; /* in */
123 uint32_t submit_offset; /* in, offset from submit_bo */
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Domap_drm.h52 uint32_t bytes; /* (for non-tiled formats) */
61 uint32_t flags; /* in */
62 uint32_t handle; /* out */
63 uint32_t __pad;
73 uint32_t handle; /* buffer handle (in) */
74 uint32_t op; /* mask of omap_gem_op (in) */
78 uint32_t handle; /* buffer handle (in) */
79 uint32_t op; /* mask of omap_gem_op (in) */
84 uint32_t nregions;
85 uint32_t __pad;
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Darmada_drm.h20 uint32_t handle;
21 uint32_t size;
27 uint32_t handle;
28 uint32_t pad;
38 uint32_t handle;
39 uint32_t offset;
40 uint32_t size;
/include/linux/
Dioc4.h34 uint32_t raw;
36 uint32_t valid:1; /* Address captured */
37 uint32_t master_id:4; /* Unit causing error
45 uint32_t mul_err:1; /* Multiple errors occurred */
46 uint32_t addr:26; /* Bits 31-6 of error addr */
49 uint32_t pci_err_addr_h; /* Bits 63-32 of error addr */
51 uint32_t raw;
64 uint32_t raw;
66 uint32_t ata_int:1; /* ATA port passthru */
67 uint32_t ata_memerr:1; /* ATA halted by mem error */
[all …]
Dpe.h45 uint32_t peaddr; /* address of pe header */
102 uint32_t magic; /* PE magic */
105 uint32_t timestamp; /* time_t */
106 uint32_t symbol_table; /* symbol table offset */
107 uint32_t symbols; /* number of symbols */
144 uint32_t text_size; /* size of text section(s) */
145 uint32_t data_size; /* size of data section(s) */
146 uint32_t bss_size; /* size of bss section(s) */
147 uint32_t entry_point; /* file offset of entry point */
148 uint32_t code_base; /* relative code addr in ram */
[all …]
/include/video/
Dgbe.h14 volatile uint32_t ctrlstat; /* general control */
15 volatile uint32_t dotclock; /* dot clock PLL control */
16 volatile uint32_t i2c; /* crt I2C control */
17 volatile uint32_t sysclk; /* system clock PLL control */
18 volatile uint32_t i2cfp; /* flat panel I2C control */
19 volatile uint32_t id; /* device id/chip revision */
20 volatile uint32_t config; /* power on configuration [1] */
21 volatile uint32_t bist; /* internal bist status [1] */
22 uint32_t _pad0[0x010000/4 - 8];
23 volatile uint32_t vt_xy; /* current dot coords */
[all …]
/include/xen/interface/
Dplatform.h41 uint32_t secs;
42 uint32_t nsecs;
59 uint32_t type;
61 uint32_t handle;
62 uint32_t reg;
76 uint32_t handle;
77 uint32_t reg;
85 uint32_t reg;
89 uint32_t type;
97 uint32_t length; /* Length of microcode data. */
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Dxen-mca.h86 uint32_t mc_socketid; /* physical socket of the physical core */
89 uint32_t mc_apicid;
90 uint32_t mc_flags;
115 uint32_t mc_msrs; /* Number of msr with valid values. */
157 uint32_t mc_socketid;
179 uint32_t mi_nentries;
180 uint32_t flags;
190 uint32_t mc_cpunr;
191 uint32_t mc_chipid;
194 uint32_t mc_apicid;
[all …]
Devent_channel.h14 typedef uint32_t evtchn_port_t;
62 uint32_t virq;
63 uint32_t vcpu;
77 uint32_t pirq;
79 uint32_t flags; /* BIND_PIRQ__* */
92 uint32_t vcpu;
138 uint32_t status;
139 uint32_t vcpu; /* VCPU to which this channel is bound. */
148 uint32_t pirq; /* EVTCHNSTAT_pirq */
149 uint32_t virq; /* EVTCHNSTAT_virq */
[all …]
Dphysdev.h38 uint32_t irq;
69 uint32_t irq;
71 uint32_t flags; /* XENIRQSTAT_* */
89 uint32_t iopl;
100 uint32_t nr_ports;
112 uint32_t reg;
114 uint32_t value;
125 uint32_t irq;
127 uint32_t vector;
200 uint32_t cmd;
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Dxen.h484 uint32_t version;
485 uint32_t pad0;
494 uint32_t tsc_to_system_mul;
614 uint32_t flags; /* SIF_xxx flags. */
616 uint32_t store_evtchn; /* Event channel for store communication. */
620 uint32_t evtchn; /* Event channel for console page. */
623 uint32_t info_off; /* Offset of console_info struct. */
624 uint32_t info_size; /* Size of console_info struct from start.*/
662 uint32_t mod_start;
664 uint32_t mod_end;
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/include/scsi/
Discsi_if.h104 uint32_t type; /* k/u events type */
105 uint32_t iferror; /* carries interface or resource errors */
111 uint32_t initial_cmdsn;
117 uint32_t initial_cmdsn;
122 uint32_t sid;
125 uint32_t sid;
126 uint32_t cid;
129 uint32_t sid;
130 uint32_t cid;
132 uint32_t is_leading;
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Dscsi_bsg_iscsi.h69 uint32_t vendor_cmd[0];
76 uint32_t vendor_rsp[0];
82 uint32_t msgcode;
99 uint32_t result;
102 uint32_t reply_payload_rcv_len;
/include/uapi/xen/
Dgntdev.h38 uint32_t domid;
40 uint32_t ref;
53 uint32_t count;
54 uint32_t pad;
75 uint32_t count;
76 uint32_t pad;
101 uint32_t count;
102 uint32_t pad;
116 uint32_t count;
140 uint32_t action;
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/include/xen/interface/io/
Dpciif.h71 uint32_t cmd;
77 uint32_t domain; /* PCI Domain/Segment */
78 uint32_t bus;
79 uint32_t devfn;
86 uint32_t value;
88 uint32_t info;
96 uint32_t cmd;
101 uint32_t domain; /* PCI Domain/Segment*/
102 uint32_t bus;
103 uint32_t devfn;
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/include/uapi/scsi/
Dscsi_bsg_fc.h168 uint32_t status; /* See FC_CTELS_STATUS_xxx */
199 uint32_t preamble_word0; /* revision & IN_ID */
200 uint32_t preamble_word1; /* GS_Type, GS_SubType, Options, Rsvd */
201 uint32_t preamble_word2; /* Cmd Code, Max Size */
224 uint32_t vendor_cmd[0];
231 uint32_t vendor_rsp[0];
268 uint32_t preamble_word0; /* revision & IN_ID */
269 uint32_t preamble_word1; /* GS_Type, GS_SubType, Options, Rsvd */
270 uint32_t preamble_word2; /* Cmd Code, Max Size */
282 uint32_t msgcode;
[all …]
/include/asm-generic/
Ddiv64.h26 uint32_t __base = (base); \
27 uint32_t __rem; \
35 extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
41 uint32_t __base = (base); \
42 uint32_t __rem; \
45 __rem = (uint32_t)(n) % __base; \
46 (n) = (uint32_t)(n) / __base; \
/include/linux/mfd/
Dcros_ec_commands.h536 uint32_t version;
546 uint32_t in_data; /* Pass anything here */
550 uint32_t out_data; /* Output will be in_data + 0x01020304 */
567 uint32_t current_image; /* One of ec_current_image */
574 uint32_t offset; /* Starting value for read buffer */
575 uint32_t size; /* Size to read in bytes */
579 uint32_t data[32];
633 uint32_t version_mask;
651 uint32_t flags; /* Mask of enum ec_comms_status */
659 uint32_t ec_result;
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/include/linux/platform_data/
Dvideo-msm_fb.h61 uint32_t caps;
68 void (*remote_write)(struct msm_mddi_client_data *, uint32_t val,
69 uint32_t reg);
70 uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg);
116 void (*dma)(struct mdp_device *mpd, uint32_t addr,
117 uint32_t stride, uint32_t w, uint32_t h, uint32_t x,
118 uint32_t y, struct msmfb_callback *callback, int interface);
122 void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id);
/include/uapi/linux/hsi/
Dhsi_char.h51 uint32_t mode;
52 uint32_t flow;
53 uint32_t channels;
57 uint32_t mode;
58 uint32_t channels;
59 uint32_t speed;
60 uint32_t arb_mode;

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