Searched refs:MCF_IPSBAR (Results 1 – 5 of 5) sorted by relevance
23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */69 #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */70 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */71 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */72 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */73 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */76 #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */77 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */78 #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */[all …]
23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */59 #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */60 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */61 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */62 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */63 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */68 #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)69 #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)70 #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)[all …]
23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */60 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */61 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */62 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */63 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */64 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */69 #define MCF_RCR (MCF_IPSBAR + 0x110000)70 #define MCF_RSR (MCF_IPSBAR + 0x110001)78 #define MCFUART_BASE0 (MCF_IPSBAR + 0x200)[all …]
45 #define MCF_IPSBAR CONFIG_IPSBAR macro
22 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)23 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)24 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)25 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)26 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)27 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)