/arch/m32r/mm/ |
D | discontig.c | 42 unsigned long ul; in mem_prof_init() local 57 ul = zone_alignment; in mem_prof_init() 58 while (start_pfn >= ul) in mem_prof_init() 59 ul += zone_alignment; in mem_prof_init() 61 start_pfn = ul - zone_alignment; in mem_prof_init()
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/arch/alpha/lib/ |
D | checksum.c | 23 unsigned long ul; in from64to16() member 28 in_v.ul = x; in from64to16() 29 tmp_v.ul = (unsigned long) in_v.ui[0] + (unsigned long) in_v.ui[1]; in from64to16() 33 out_v.ul = (unsigned long) tmp_v.us[0] + (unsigned long) tmp_v.us[1] in from64to16()
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D | csum_partial_copy.c | 79 unsigned long ul; in from64to16() member 84 in_v.ul = x; in from64to16() 85 tmp_v.ul = (unsigned long) in_v.ui[0] + (unsigned long) in_v.ui[1]; in from64to16() 89 out_v.ul = (unsigned long) tmp_v.us[0] + (unsigned long) tmp_v.us[1] in from64to16()
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/arch/mips/include/asm/ |
D | bitops.h | 513 if (!(word & (~0ul << 32))) { in __fls() 518 if (!(word & (~0ul << (BITS_PER_LONG-16)))) { in __fls() 522 if (!(word & (~0ul << (BITS_PER_LONG-8)))) { in __fls() 526 if (!(word & (~0ul << (BITS_PER_LONG-4)))) { in __fls() 530 if (!(word & (~0ul << (BITS_PER_LONG-2)))) { in __fls() 534 if (!(word & (~0ul << (BITS_PER_LONG-1)))) in __fls()
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/arch/arm/mach-tegra/ |
D | irq.c | 177 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); in tegra_legacy_irq_suspend() 180 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); in tegra_legacy_irq_suspend() 199 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); in tegra_legacy_irq_resume() 202 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); in tegra_legacy_irq_resume()
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/arch/blackfin/include/asm/ |
D | ipipe.h | 154 static inline unsigned long __ipipe_ffnz(unsigned long ul) in __ipipe_ffnz() argument 156 return ffs(ul) - 1; in __ipipe_ffnz()
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/arch/sh/include/mach-common/mach/ |
D | microdev.h | 26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INT…
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/arch/arm/mm/ |
D | mm.h | 90 #define arm_dma_pfn_limit (~0ul >> PAGE_SHIFT)
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/arch/sh/boards/mach-microdev/ |
D | irq.c | 128 __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG); in init_microdev_irq()
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/arch/powerpc/lib/ |
D | sstep.c | 349 unsigned long ul[2]; in do_fp_load() member 367 ptr = (unsigned long) &data.ul; in do_fp_load() 369 err = read_mem_unaligned(&data.ul[0], ea, nb, regs); in do_fp_load() 374 err = read_mem_unaligned(&data.ul[0], ea, 4, regs); in do_fp_load() 376 err = read_mem_unaligned(&data.ul[1], ea + 4, 4, regs); in do_fp_load() 390 unsigned long ul[2]; in do_fp_store() member 408 ptr = (unsigned long) &data.ul[0]; in do_fp_store() 415 err = write_mem_unaligned(data.ul[0], ea, nb, regs); in do_fp_store() 421 err = write_mem_unaligned(data.ul[0], ea, 4, regs); in do_fp_store() 423 err = write_mem_unaligned(data.ul[1], ea + 4, 4, regs); in do_fp_store()
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/arch/powerpc/platforms/cell/ |
D | spu_priv1_mmio.c | 135 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); in tlb_invalidate()
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D | beat_spu_priv1.c | 145 offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul); in tlb_invalidate()
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D | spu_base.c | 328 spu_mfc_dsisr_set(spu, 0ul); in spu_irq_class_1()
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/arch/powerpc/platforms/cell/spufs/ |
D | switch.c | 130 spu_int_mask_set(spu, 0, 0ul); in disable_interrupts() 131 spu_int_mask_set(spu, 1, 0ul); in disable_interrupts() 132 spu_int_mask_set(spu, 2, 0ul); in disable_interrupts() 772 spu_int_mask_set(spu, 0, 0ul); in enable_interrupts() 774 spu_int_mask_set(spu, 2, 0ul); in enable_interrupts() 1421 spu_int_mask_set(spu, 0, 0ul); in clear_interrupts() 1422 spu_int_mask_set(spu, 1, 0ul); in clear_interrupts() 1423 spu_int_mask_set(spu, 2, 0ul); in clear_interrupts()
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/arch/powerpc/include/asm/ |
D | spu.h | 694 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul) 704 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
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/arch/powerpc/kvm/ |
D | book3s_hv_rm_mmu.c | 198 is_io = ~0ul; in kvmppc_do_h_enter() 261 if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) { in kvmppc_do_h_enter()
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/arch/x86/xen/ |
D | setup.c | 675 set_phys_range_identity(map[i-1].addr / PAGE_SIZE, ~0ul); in xen_memory_setup()
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/arch/blackfin/kernel/ |
D | setup.c | 1427 physical_mem_end >> 10, 0ul, physical_mem_end);
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