Searched refs:vce_level (Results 1 – 5 of 5) sorted by relevance
134 SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; member
906 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()907 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()909 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()916 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()944 (u8 *)&pi->vce_level, in kv_populate_vce_table()2152 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()2153 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()2179 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()2180 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
765 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()766 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()808 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()809 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()810 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()811 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
1336 enum radeon_vce_level vce_level; member1536 enum radeon_vce_level vce_level; member
1028 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; in radeon_dpm_enable_vce()