1/* 2 * Device Tree file for Marvell Armada 370 Reference Design board 3 * (RD-88F6710-A1) 4 * 5 * Copied from arch/arm/boot/dts/armada-370-db.dts 6 * 7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 * 13 * Note: this Device Tree assumes that the bootloader has remapped the 14 * internal registers to 0xf1000000 (instead of the default 15 * 0xd0000000). The 0xf1000000 is the default used by the recent, 16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 17 * boards were delivered with an older version of the bootloader that 18 * left internal registers mapped at 0xd0000000. If you are in this 19 * situation, you should either update your bootloader (preferred 20 * solution) or the below Device Tree should be adjusted. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/input/input.h> 25#include <dt-bindings/gpio/gpio.h> 26#include "armada-370.dtsi" 27 28/ { 29 model = "Marvell Armada 370 Reference Design"; 30 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; 31 32 chosen { 33 bootargs = "console=ttyS0,115200 earlyprintk"; 34 }; 35 36 memory { 37 device_type = "memory"; 38 reg = <0x00000000 0x20000000>; /* 512 MB */ 39 }; 40 41 soc { 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; 44 45 pcie-controller { 46 status = "okay"; 47 48 /* Internal mini-PCIe connector */ 49 pcie@1,0 { 50 /* Port 0, Lane 0 */ 51 status = "okay"; 52 }; 53 54 /* Internal mini-PCIe connector */ 55 pcie@2,0 { 56 /* Port 1, Lane 0 */ 57 status = "okay"; 58 }; 59 }; 60 61 internal-regs { 62 pinctrl { 63 fan_pins: fan-pins { 64 marvell,pins = "mpp8"; 65 marvell,function = "gpio"; 66 }; 67 68 led_pins: led-pins { 69 marvell,pins = "mpp32"; 70 marvell,function = "gpio"; 71 }; 72 }; 73 74 serial@12000 { 75 status = "okay"; 76 }; 77 sata@a0000 { 78 nr-ports = <2>; 79 status = "okay"; 80 }; 81 82 mdio { 83 pinctrl-0 = <&mdio_pins>; 84 pinctrl-names = "default"; 85 phy0: ethernet-phy@0 { 86 reg = <0>; 87 }; 88 89 phy1: ethernet-phy@1 { 90 reg = <1>; 91 }; 92 }; 93 94 ethernet@70000 { 95 status = "okay"; 96 phy = <&phy0>; 97 phy-mode = "sgmii"; 98 }; 99 ethernet@74000 { 100 pinctrl-0 = <&ge1_rgmii_pins>; 101 pinctrl-names = "default"; 102 status = "okay"; 103 phy = <&phy1>; 104 phy-mode = "rgmii-id"; 105 }; 106 107 mvsdio@d4000 { 108 pinctrl-0 = <&sdio_pins1>; 109 pinctrl-names = "default"; 110 status = "okay"; 111 /* No CD or WP GPIOs */ 112 broken-cd; 113 }; 114 115 usb@50000 { 116 status = "okay"; 117 }; 118 119 usb@51000 { 120 status = "okay"; 121 }; 122 123 gpio-keys { 124 compatible = "gpio-keys"; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 button@1 { 128 label = "Software Button"; 129 linux,code = <KEY_POWER>; 130 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 131 }; 132 }; 133 134 gpio-fan { 135 compatible = "gpio-fan"; 136 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; 137 gpio-fan,speed-map = <0 0 3000 1>; 138 pinctrl-0 = <&fan_pins>; 139 pinctrl-names = "default"; 140 }; 141 142 gpio_leds { 143 compatible = "gpio-leds"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&led_pins>; 146 147 sw_led { 148 label = "370rd:green:sw"; 149 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 150 default-state = "keep"; 151 }; 152 }; 153 154 nand@d0000 { 155 status = "okay"; 156 num-cs = <1>; 157 marvell,nand-keep-config; 158 marvell,nand-enable-arbiter; 159 nand-on-flash-bbt; 160 161 partition@0 { 162 label = "U-Boot"; 163 reg = <0 0x800000>; 164 }; 165 partition@800000 { 166 label = "Linux"; 167 reg = <0x800000 0x800000>; 168 }; 169 partition@1000000 { 170 label = "Filesystem"; 171 reg = <0x1000000 0x3f000000>; 172 }; 173 }; 174 }; 175 }; 176 }; 177