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1/*
2 * Device Tree file for Marvell Armada 385 evaluation board
3 * (DB-88F6820)
4 *
5 *  Copyright (C) 2014 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2.  This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/dts-v1/;
15#include "armada-385.dtsi"
16
17/ {
18	model = "Marvell Armada 385 Development Board";
19	compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380";
20
21	chosen {
22		bootargs = "console=ttyS0,115200 earlyprintk";
23	};
24
25	memory {
26		device_type = "memory";
27		reg = <0x00000000 0x10000000>; /* 256 MB */
28	};
29
30	soc {
31		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
32			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
33
34		internal-regs {
35			spi@10600 {
36				status = "okay";
37
38				spi-flash@0 {
39					#address-cells = <1>;
40					#size-cells = <1>;
41					compatible = "w25q32";
42					reg = <0>; /* Chip select 0 */
43					spi-max-frequency = <108000000>;
44				};
45			};
46
47			i2c@11000 {
48				status = "okay";
49				clock-frequency = <100000>;
50			};
51
52			i2c@11100 {
53				status = "okay";
54				clock-frequency = <100000>;
55			};
56
57			serial@12000 {
58				status = "okay";
59			};
60
61			ethernet@30000 {
62				status = "okay";
63				phy = <&phy1>;
64				phy-mode = "rgmii-id";
65			};
66
67			usb@50000 {
68				status = "ok";
69			};
70
71			ethernet@70000 {
72				status = "okay";
73				phy = <&phy0>;
74				phy-mode = "rgmii-id";
75			};
76
77			mdio {
78				phy0: ethernet-phy@0 {
79					reg = <0>;
80				};
81
82				phy1: ethernet-phy@1 {
83					reg = <1>;
84				};
85			};
86
87			sata@a8000 {
88				status = "okay";
89			};
90
91			sata@e0000 {
92				status = "okay";
93			};
94
95			flash@d0000 {
96				status = "okay";
97				num-cs = <1>;
98				marvell,nand-keep-config;
99				marvell,nand-enable-arbiter;
100				nand-on-flash-bbt;
101				nand-ecc-strength = <4>;
102				nand-ecc-step-size = <512>;
103
104				partition@0 {
105					label = "U-Boot";
106					reg = <0 0x800000>;
107				};
108				partition@800000 {
109					label = "Linux";
110					reg = <0x800000 0x800000>;
111				};
112				partition@1000000 {
113					label = "Filesystem";
114					reg = <0x1000000 0x3f000000>;
115				};
116			};
117
118			sdhci@d8000 {
119				clock-frequency = <200000000>;
120				broken-cd;
121				wp-inverted;
122				bus-width = <8>;
123				status = "okay";
124			};
125
126			usb3@f0000 {
127				status = "okay";
128			};
129
130			usb3@f8000 {
131				status = "okay";
132			};
133		};
134
135		pcie-controller {
136			status = "okay";
137			/*
138			 * The two PCIe units are accessible through
139			 * standard PCIe slots on the board.
140			 */
141			pcie@1,0 {
142				/* Port 0, Lane 0 */
143				status = "okay";
144			};
145			pcie@2,0 {
146				/* Port 1, Lane 0 */
147				status = "okay";
148			};
149		};
150	};
151};
152