1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 * 12 * Contains definitions specific to the Armada XP MV78260 SoC that are not 13 * common to all Armada XP SoCs. 14 */ 15 16#include "armada-xp.dtsi" 17 18/ { 19 model = "Marvell Armada XP MV78260 SoC"; 20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 eth3 = ð3; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 enable-method = "marvell,armada-xp-smp"; 33 34 cpu@0 { 35 device_type = "cpu"; 36 compatible = "marvell,sheeva-v7"; 37 reg = <0>; 38 clocks = <&cpuclk 0>; 39 clock-latency = <1000000>; 40 }; 41 42 cpu@1 { 43 device_type = "cpu"; 44 compatible = "marvell,sheeva-v7"; 45 reg = <1>; 46 clocks = <&cpuclk 1>; 47 clock-latency = <1000000>; 48 }; 49 }; 50 51 soc { 52 /* 53 * MV78260 has 3 PCIe units Gen2.0: Two units can be 54 * configured as x4 or quad x1 lanes. One unit is 55 * x4 only. 56 */ 57 pcie-controller { 58 compatible = "marvell,armada-xp-pcie"; 59 status = "disabled"; 60 device_type = "pci"; 61 62 #address-cells = <3>; 63 #size-cells = <2>; 64 65 msi-parent = <&mpic>; 66 bus-range = <0x00 0xff>; 67 68 ranges = 69 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 70 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 71 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 72 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 73 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 74 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 75 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 76 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 77 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 78 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 79 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 80 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 81 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 82 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 83 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 84 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 85 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 86 87 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 88 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 89 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 90 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 91 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 92 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 93 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 94 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 95 96 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 97 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 98 99 pcie@1,0 { 100 device_type = "pci"; 101 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 102 reg = <0x0800 0 0 0 0>; 103 #address-cells = <3>; 104 #size-cells = <2>; 105 #interrupt-cells = <1>; 106 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 107 0x81000000 0 0 0x81000000 0x1 0 1 0>; 108 interrupt-map-mask = <0 0 0 0>; 109 interrupt-map = <0 0 0 0 &mpic 58>; 110 marvell,pcie-port = <0>; 111 marvell,pcie-lane = <0>; 112 clocks = <&gateclk 5>; 113 status = "disabled"; 114 }; 115 116 pcie@2,0 { 117 device_type = "pci"; 118 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 119 reg = <0x1000 0 0 0 0>; 120 #address-cells = <3>; 121 #size-cells = <2>; 122 #interrupt-cells = <1>; 123 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 124 0x81000000 0 0 0x81000000 0x2 0 1 0>; 125 interrupt-map-mask = <0 0 0 0>; 126 interrupt-map = <0 0 0 0 &mpic 59>; 127 marvell,pcie-port = <0>; 128 marvell,pcie-lane = <1>; 129 clocks = <&gateclk 6>; 130 status = "disabled"; 131 }; 132 133 pcie@3,0 { 134 device_type = "pci"; 135 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 136 reg = <0x1800 0 0 0 0>; 137 #address-cells = <3>; 138 #size-cells = <2>; 139 #interrupt-cells = <1>; 140 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 141 0x81000000 0 0 0x81000000 0x3 0 1 0>; 142 interrupt-map-mask = <0 0 0 0>; 143 interrupt-map = <0 0 0 0 &mpic 60>; 144 marvell,pcie-port = <0>; 145 marvell,pcie-lane = <2>; 146 clocks = <&gateclk 7>; 147 status = "disabled"; 148 }; 149 150 pcie@4,0 { 151 device_type = "pci"; 152 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 153 reg = <0x2000 0 0 0 0>; 154 #address-cells = <3>; 155 #size-cells = <2>; 156 #interrupt-cells = <1>; 157 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 158 0x81000000 0 0 0x81000000 0x4 0 1 0>; 159 interrupt-map-mask = <0 0 0 0>; 160 interrupt-map = <0 0 0 0 &mpic 61>; 161 marvell,pcie-port = <0>; 162 marvell,pcie-lane = <3>; 163 clocks = <&gateclk 8>; 164 status = "disabled"; 165 }; 166 167 pcie@5,0 { 168 device_type = "pci"; 169 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 170 reg = <0x2800 0 0 0 0>; 171 #address-cells = <3>; 172 #size-cells = <2>; 173 #interrupt-cells = <1>; 174 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 175 0x81000000 0 0 0x81000000 0x5 0 1 0>; 176 interrupt-map-mask = <0 0 0 0>; 177 interrupt-map = <0 0 0 0 &mpic 62>; 178 marvell,pcie-port = <1>; 179 marvell,pcie-lane = <0>; 180 clocks = <&gateclk 9>; 181 status = "disabled"; 182 }; 183 184 pcie@6,0 { 185 device_type = "pci"; 186 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; 187 reg = <0x3000 0 0 0 0>; 188 #address-cells = <3>; 189 #size-cells = <2>; 190 #interrupt-cells = <1>; 191 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 192 0x81000000 0 0 0x81000000 0x6 0 1 0>; 193 interrupt-map-mask = <0 0 0 0>; 194 interrupt-map = <0 0 0 0 &mpic 63>; 195 marvell,pcie-port = <1>; 196 marvell,pcie-lane = <1>; 197 clocks = <&gateclk 10>; 198 status = "disabled"; 199 }; 200 201 pcie@7,0 { 202 device_type = "pci"; 203 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; 204 reg = <0x3800 0 0 0 0>; 205 #address-cells = <3>; 206 #size-cells = <2>; 207 #interrupt-cells = <1>; 208 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 209 0x81000000 0 0 0x81000000 0x7 0 1 0>; 210 interrupt-map-mask = <0 0 0 0>; 211 interrupt-map = <0 0 0 0 &mpic 64>; 212 marvell,pcie-port = <1>; 213 marvell,pcie-lane = <2>; 214 clocks = <&gateclk 11>; 215 status = "disabled"; 216 }; 217 218 pcie@8,0 { 219 device_type = "pci"; 220 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; 221 reg = <0x4000 0 0 0 0>; 222 #address-cells = <3>; 223 #size-cells = <2>; 224 #interrupt-cells = <1>; 225 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 226 0x81000000 0 0 0x81000000 0x8 0 1 0>; 227 interrupt-map-mask = <0 0 0 0>; 228 interrupt-map = <0 0 0 0 &mpic 65>; 229 marvell,pcie-port = <1>; 230 marvell,pcie-lane = <3>; 231 clocks = <&gateclk 12>; 232 status = "disabled"; 233 }; 234 235 pcie@9,0 { 236 device_type = "pci"; 237 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 238 reg = <0x4800 0 0 0 0>; 239 #address-cells = <3>; 240 #size-cells = <2>; 241 #interrupt-cells = <1>; 242 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 243 0x81000000 0 0 0x81000000 0x9 0 1 0>; 244 interrupt-map-mask = <0 0 0 0>; 245 interrupt-map = <0 0 0 0 &mpic 99>; 246 marvell,pcie-port = <2>; 247 marvell,pcie-lane = <0>; 248 clocks = <&gateclk 26>; 249 status = "disabled"; 250 }; 251 }; 252 253 internal-regs { 254 pinctrl { 255 compatible = "marvell,mv78260-pinctrl"; 256 reg = <0x18000 0x38>; 257 258 sdio_pins: sdio-pins { 259 marvell,pins = "mpp30", "mpp31", "mpp32", 260 "mpp33", "mpp34", "mpp35"; 261 marvell,function = "sd0"; 262 }; 263 }; 264 265 gpio0: gpio@18100 { 266 compatible = "marvell,orion-gpio"; 267 reg = <0x18100 0x40>; 268 ngpios = <32>; 269 gpio-controller; 270 #gpio-cells = <2>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 interrupts = <82>, <83>, <84>, <85>; 274 }; 275 276 gpio1: gpio@18140 { 277 compatible = "marvell,orion-gpio"; 278 reg = <0x18140 0x40>; 279 ngpios = <32>; 280 gpio-controller; 281 #gpio-cells = <2>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 interrupts = <87>, <88>, <89>, <90>; 285 }; 286 287 gpio2: gpio@18180 { 288 compatible = "marvell,orion-gpio"; 289 reg = <0x18180 0x40>; 290 ngpios = <3>; 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 interrupts = <91>; 296 }; 297 298 eth3: ethernet@34000 { 299 compatible = "marvell,armada-xp-neta"; 300 reg = <0x34000 0x4000>; 301 interrupts = <14>; 302 clocks = <&gateclk 1>; 303 status = "disabled"; 304 }; 305 }; 306 }; 307}; 308