1/* 2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC 3 * 4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * based on GPL'ed 2.6 kernel sources 7 * (c) Marvell International Ltd. 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#include "skeleton.dtsi" 15#include <dt-bindings/clock/berlin2.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17 18/ { 19 model = "Marvell Armada 1500 (BG2) SoC"; 20 compatible = "marvell,berlin2", "marvell,berlin"; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 enable-method = "marvell,berlin-smp"; 26 27 cpu@0 { 28 compatible = "marvell,pj4b"; 29 device_type = "cpu"; 30 next-level-cache = <&l2>; 31 reg = <0>; 32 }; 33 34 cpu@1 { 35 compatible = "marvell,pj4b"; 36 device_type = "cpu"; 37 next-level-cache = <&l2>; 38 reg = <1>; 39 }; 40 }; 41 42 refclk: oscillator { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <25000000>; 46 }; 47 48 soc { 49 compatible = "simple-bus"; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 interrupt-parent = <&gic>; 53 54 ranges = <0 0xf7000000 0x1000000>; 55 56 l2: l2-cache-controller@ac0000 { 57 compatible = "marvell,tauros3-cache", "arm,pl310-cache"; 58 reg = <0xac0000 0x1000>; 59 cache-unified; 60 cache-level = <2>; 61 }; 62 63 scu: snoop-control-unit@ad0000 { 64 compatible = "arm,cortex-a9-scu"; 65 reg = <0xad0000 0x58>; 66 }; 67 68 gic: interrupt-controller@ad1000 { 69 compatible = "arm,cortex-a9-gic"; 70 reg = <0xad1000 0x1000>, <0xad0100 0x0100>; 71 interrupt-controller; 72 #interrupt-cells = <3>; 73 }; 74 75 local-timer@ad0600 { 76 compatible = "arm,cortex-a9-twd-timer"; 77 reg = <0xad0600 0x20>; 78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&chip CLKID_TWD>; 80 }; 81 82 cpu-ctrl@dd0000 { 83 compatible = "marvell,berlin-cpu-ctrl"; 84 reg = <0xdd0000 0x10000>; 85 }; 86 87 apb@e80000 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 92 ranges = <0 0xe80000 0x10000>; 93 interrupt-parent = <&aic>; 94 95 gpio0: gpio@0400 { 96 compatible = "snps,dw-apb-gpio"; 97 reg = <0x0400 0x400>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 porta: gpio-port@0 { 102 compatible = "snps,dw-apb-gpio-port"; 103 gpio-controller; 104 #gpio-cells = <2>; 105 snps,nr-gpios = <8>; 106 reg = <0>; 107 interrupt-controller; 108 #interrupt-cells = <2>; 109 interrupts = <0>; 110 }; 111 }; 112 113 gpio1: gpio@0800 { 114 compatible = "snps,dw-apb-gpio"; 115 reg = <0x0800 0x400>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 portb: gpio-port@1 { 120 compatible = "snps,dw-apb-gpio-port"; 121 gpio-controller; 122 #gpio-cells = <2>; 123 snps,nr-gpios = <8>; 124 reg = <0>; 125 interrupt-controller; 126 #interrupt-cells = <2>; 127 interrupts = <1>; 128 }; 129 }; 130 131 gpio2: gpio@0c00 { 132 compatible = "snps,dw-apb-gpio"; 133 reg = <0x0c00 0x400>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 portc: gpio-port@2 { 138 compatible = "snps,dw-apb-gpio-port"; 139 gpio-controller; 140 #gpio-cells = <2>; 141 snps,nr-gpios = <8>; 142 reg = <0>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 interrupts = <2>; 146 }; 147 }; 148 149 gpio3: gpio@1000 { 150 compatible = "snps,dw-apb-gpio"; 151 reg = <0x1000 0x400>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 155 portd: gpio-port@3 { 156 compatible = "snps,dw-apb-gpio-port"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 snps,nr-gpios = <8>; 160 reg = <0>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 interrupts = <3>; 164 }; 165 }; 166 167 timer0: timer@2c00 { 168 compatible = "snps,dw-apb-timer"; 169 reg = <0x2c00 0x14>; 170 interrupts = <8>; 171 clocks = <&chip CLKID_CFG>; 172 clock-names = "timer"; 173 status = "okay"; 174 }; 175 176 timer1: timer@2c14 { 177 compatible = "snps,dw-apb-timer"; 178 reg = <0x2c14 0x14>; 179 interrupts = <9>; 180 clocks = <&chip CLKID_CFG>; 181 clock-names = "timer"; 182 status = "okay"; 183 }; 184 185 timer2: timer@2c28 { 186 compatible = "snps,dw-apb-timer"; 187 reg = <0x2c28 0x14>; 188 interrupts = <10>; 189 clocks = <&chip CLKID_CFG>; 190 clock-names = "timer"; 191 status = "disabled"; 192 }; 193 194 timer3: timer@2c3c { 195 compatible = "snps,dw-apb-timer"; 196 reg = <0x2c3c 0x14>; 197 interrupts = <11>; 198 clocks = <&chip CLKID_CFG>; 199 clock-names = "timer"; 200 status = "disabled"; 201 }; 202 203 timer4: timer@2c50 { 204 compatible = "snps,dw-apb-timer"; 205 reg = <0x2c50 0x14>; 206 interrupts = <12>; 207 clocks = <&chip CLKID_CFG>; 208 clock-names = "timer"; 209 status = "disabled"; 210 }; 211 212 timer5: timer@2c64 { 213 compatible = "snps,dw-apb-timer"; 214 reg = <0x2c64 0x14>; 215 interrupts = <13>; 216 clocks = <&chip CLKID_CFG>; 217 clock-names = "timer"; 218 status = "disabled"; 219 }; 220 221 timer6: timer@2c78 { 222 compatible = "snps,dw-apb-timer"; 223 reg = <0x2c78 0x14>; 224 interrupts = <14>; 225 clocks = <&chip CLKID_CFG>; 226 clock-names = "timer"; 227 status = "disabled"; 228 }; 229 230 timer7: timer@2c8c { 231 compatible = "snps,dw-apb-timer"; 232 reg = <0x2c8c 0x14>; 233 interrupts = <15>; 234 clocks = <&chip CLKID_CFG>; 235 clock-names = "timer"; 236 status = "disabled"; 237 }; 238 239 aic: interrupt-controller@3000 { 240 compatible = "snps,dw-apb-ictl"; 241 reg = <0x3000 0xc00>; 242 interrupt-controller; 243 #interrupt-cells = <1>; 244 interrupt-parent = <&gic>; 245 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 246 }; 247 }; 248 249 chip: chip-control@ea0000 { 250 compatible = "marvell,berlin2-chip-ctrl"; 251 #clock-cells = <1>; 252 reg = <0xea0000 0x400>; 253 clocks = <&refclk>; 254 clock-names = "refclk"; 255 }; 256 257 apb@fc0000 { 258 compatible = "simple-bus"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 ranges = <0 0xfc0000 0x10000>; 263 interrupt-parent = <&sic>; 264 265 sm_gpio1: gpio@5000 { 266 compatible = "snps,dw-apb-gpio"; 267 reg = <0x5000 0x400>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 portf: gpio-port@5 { 272 compatible = "snps,dw-apb-gpio-port"; 273 gpio-controller; 274 #gpio-cells = <2>; 275 snps,nr-gpios = <8>; 276 reg = <0>; 277 }; 278 }; 279 280 sm_gpio0: gpio@c000 { 281 compatible = "snps,dw-apb-gpio"; 282 reg = <0xc000 0x400>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 286 porte: gpio-port@4 { 287 compatible = "snps,dw-apb-gpio-port"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 snps,nr-gpios = <8>; 291 reg = <0>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 interrupts = <11>; 295 }; 296 }; 297 298 uart0: serial@9000 { 299 compatible = "snps,dw-apb-uart"; 300 reg = <0x9000 0x100>; 301 reg-shift = <2>; 302 reg-io-width = <1>; 303 interrupts = <8>; 304 clocks = <&refclk>; 305 pinctrl-0 = <&uart0_pmux>; 306 pinctrl-names = "default"; 307 status = "disabled"; 308 }; 309 310 uart1: serial@a000 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0xa000 0x100>; 313 reg-shift = <2>; 314 reg-io-width = <1>; 315 interrupts = <9>; 316 clocks = <&refclk>; 317 pinctrl-0 = <&uart1_pmux>; 318 pinctrl-names = "default"; 319 status = "disabled"; 320 }; 321 322 uart2: serial@b000 { 323 compatible = "snps,dw-apb-uart"; 324 reg = <0xb000 0x100>; 325 reg-shift = <2>; 326 reg-io-width = <1>; 327 interrupts = <10>; 328 clocks = <&refclk>; 329 pinctrl-0 = <&uart2_pmux>; 330 pinctrl-names = "default"; 331 status = "disabled"; 332 }; 333 334 sysctrl: system-controller@d000 { 335 compatible = "marvell,berlin2-system-ctrl"; 336 reg = <0xd000 0x100>; 337 338 uart0_pmux: uart0-pmux { 339 groups = "GSM4"; 340 function = "uart0"; 341 }; 342 343 uart1_pmux: uart1-pmux { 344 groups = "GSM5"; 345 function = "uart1"; 346 }; 347 348 uart2_pmux: uart2-pmux { 349 groups = "GSM3"; 350 function = "uart2"; 351 }; 352 }; 353 354 sic: interrupt-controller@e000 { 355 compatible = "snps,dw-apb-ictl"; 356 reg = <0xe000 0x400>; 357 interrupt-controller; 358 #interrupt-cells = <1>; 359 interrupt-parent = <&gic>; 360 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 361 }; 362 }; 363 }; 364}; 365