1/* 2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9#include <dt-bindings/clock/berlin2q.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12#include "skeleton.dtsi" 13 14/ { 15 model = "Marvell Armada 1500 pro (BG2-Q) SoC"; 16 compatible = "marvell,berlin2q", "marvell,berlin"; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 enable-method = "marvell,berlin-smp"; 22 23 cpu@0 { 24 compatible = "arm,cortex-a9"; 25 device_type = "cpu"; 26 next-level-cache = <&l2>; 27 reg = <0>; 28 }; 29 30 cpu@1 { 31 compatible = "arm,cortex-a9"; 32 device_type = "cpu"; 33 next-level-cache = <&l2>; 34 reg = <1>; 35 }; 36 37 cpu@2 { 38 compatible = "arm,cortex-a9"; 39 device_type = "cpu"; 40 next-level-cache = <&l2>; 41 reg = <2>; 42 }; 43 44 cpu@3 { 45 compatible = "arm,cortex-a9"; 46 device_type = "cpu"; 47 next-level-cache = <&l2>; 48 reg = <3>; 49 }; 50 }; 51 52 refclk: oscillator { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 }; 57 58 soc { 59 compatible = "simple-bus"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 ranges = <0 0xf7000000 0x1000000>; 64 interrupt-parent = <&gic>; 65 66 sdhci0: sdhci@ab0000 { 67 compatible = "mrvl,pxav3-mmc"; 68 reg = <0xab0000 0x200>; 69 clocks = <&chip CLKID_SDIO1XIN>; 70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 71 status = "disabled"; 72 }; 73 74 sdhci1: sdhci@ab0800 { 75 compatible = "mrvl,pxav3-mmc"; 76 reg = <0xab0800 0x200>; 77 clocks = <&chip CLKID_SDIO1XIN>; 78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 79 status = "disabled"; 80 }; 81 82 sdhci2: sdhci@ab1000 { 83 compatible = "mrvl,pxav3-mmc"; 84 reg = <0xab1000 0x200>; 85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; 87 clock-names = "io", "core"; 88 status = "disabled"; 89 }; 90 91 l2: l2-cache-controller@ac0000 { 92 compatible = "arm,pl310-cache"; 93 reg = <0xac0000 0x1000>; 94 cache-level = <2>; 95 arm,data-latency = <2 2 2>; 96 arm,tag-latency = <2 2 2>; 97 }; 98 99 scu: snoop-control-unit@ad0000 { 100 compatible = "arm,cortex-a9-scu"; 101 reg = <0xad0000 0x58>; 102 }; 103 104 local-timer@ad0600 { 105 compatible = "arm,cortex-a9-twd-timer"; 106 reg = <0xad0600 0x20>; 107 clocks = <&chip CLKID_TWD>; 108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 109 }; 110 111 gic: interrupt-controller@ad1000 { 112 compatible = "arm,cortex-a9-gic"; 113 reg = <0xad1000 0x1000>, <0xad0100 0x100>; 114 interrupt-controller; 115 #interrupt-cells = <3>; 116 }; 117 118 eth0: ethernet@b90000 { 119 compatible = "marvell,pxa168-eth"; 120 reg = <0xb90000 0x10000>; 121 clocks = <&chip CLKID_GETH0>; 122 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 123 /* set by bootloader */ 124 local-mac-address = [00 00 00 00 00 00]; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 phy-handle = <ðphy0>; 128 status = "disabled"; 129 130 ethphy0: ethernet-phy@0 { 131 reg = <0>; 132 }; 133 }; 134 135 cpu-ctrl@dd0000 { 136 compatible = "marvell,berlin-cpu-ctrl"; 137 reg = <0xdd0000 0x10000>; 138 }; 139 140 apb@e80000 { 141 compatible = "simple-bus"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 145 ranges = <0 0xe80000 0x10000>; 146 interrupt-parent = <&aic>; 147 148 gpio0: gpio@0400 { 149 compatible = "snps,dw-apb-gpio"; 150 reg = <0x0400 0x400>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 porta: gpio-port@0 { 155 compatible = "snps,dw-apb-gpio-port"; 156 gpio-controller; 157 #gpio-cells = <2>; 158 snps,nr-gpios = <32>; 159 reg = <0>; 160 interrupt-controller; 161 #interrupt-cells = <2>; 162 interrupts = <0>; 163 }; 164 }; 165 166 gpio1: gpio@0800 { 167 compatible = "snps,dw-apb-gpio"; 168 reg = <0x0800 0x400>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 portb: gpio-port@1 { 173 compatible = "snps,dw-apb-gpio-port"; 174 gpio-controller; 175 #gpio-cells = <2>; 176 snps,nr-gpios = <32>; 177 reg = <0>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 interrupts = <1>; 181 }; 182 }; 183 184 gpio2: gpio@0c00 { 185 compatible = "snps,dw-apb-gpio"; 186 reg = <0x0c00 0x400>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 portc: gpio-port@2 { 191 compatible = "snps,dw-apb-gpio-port"; 192 gpio-controller; 193 #gpio-cells = <2>; 194 snps,nr-gpios = <32>; 195 reg = <0>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 interrupts = <2>; 199 }; 200 }; 201 202 gpio3: gpio@1000 { 203 compatible = "snps,dw-apb-gpio"; 204 reg = <0x1000 0x400>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 portd: gpio-port@3 { 209 compatible = "snps,dw-apb-gpio-port"; 210 gpio-controller; 211 #gpio-cells = <2>; 212 snps,nr-gpios = <32>; 213 reg = <0>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 interrupts = <3>; 217 }; 218 }; 219 220 i2c0: i2c@1400 { 221 compatible = "snps,designware-i2c"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 reg = <0x1400 0x100>; 225 interrupt-parent = <&aic>; 226 interrupts = <4>; 227 clocks = <&chip CLKID_CFG>; 228 pinctrl-0 = <&twsi0_pmux>; 229 pinctrl-names = "default"; 230 status = "disabled"; 231 }; 232 233 i2c1: i2c@1800 { 234 compatible = "snps,designware-i2c"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <0x1800 0x100>; 238 interrupt-parent = <&aic>; 239 interrupts = <5>; 240 clocks = <&chip CLKID_CFG>; 241 pinctrl-0 = <&twsi1_pmux>; 242 pinctrl-names = "default"; 243 status = "disabled"; 244 }; 245 246 timer0: timer@2c00 { 247 compatible = "snps,dw-apb-timer"; 248 reg = <0x2c00 0x14>; 249 clocks = <&chip CLKID_CFG>; 250 clock-names = "timer"; 251 interrupts = <8>; 252 }; 253 254 timer1: timer@2c14 { 255 compatible = "snps,dw-apb-timer"; 256 reg = <0x2c14 0x14>; 257 clocks = <&chip CLKID_CFG>; 258 clock-names = "timer"; 259 status = "disabled"; 260 }; 261 262 timer2: timer@2c28 { 263 compatible = "snps,dw-apb-timer"; 264 reg = <0x2c28 0x14>; 265 clocks = <&chip CLKID_CFG>; 266 clock-names = "timer"; 267 status = "disabled"; 268 }; 269 270 timer3: timer@2c3c { 271 compatible = "snps,dw-apb-timer"; 272 reg = <0x2c3c 0x14>; 273 clocks = <&chip CLKID_CFG>; 274 clock-names = "timer"; 275 status = "disabled"; 276 }; 277 278 timer4: timer@2c50 { 279 compatible = "snps,dw-apb-timer"; 280 reg = <0x2c50 0x14>; 281 clocks = <&chip CLKID_CFG>; 282 clock-names = "timer"; 283 status = "disabled"; 284 }; 285 286 timer5: timer@2c64 { 287 compatible = "snps,dw-apb-timer"; 288 reg = <0x2c64 0x14>; 289 clocks = <&chip CLKID_CFG>; 290 clock-names = "timer"; 291 status = "disabled"; 292 }; 293 294 timer6: timer@2c78 { 295 compatible = "snps,dw-apb-timer"; 296 reg = <0x2c78 0x14>; 297 clocks = <&chip CLKID_CFG>; 298 clock-names = "timer"; 299 status = "disabled"; 300 }; 301 302 timer7: timer@2c8c { 303 compatible = "snps,dw-apb-timer"; 304 reg = <0x2c8c 0x14>; 305 clocks = <&chip CLKID_CFG>; 306 clock-names = "timer"; 307 status = "disabled"; 308 }; 309 310 aic: interrupt-controller@3800 { 311 compatible = "snps,dw-apb-ictl"; 312 reg = <0x3800 0x30>; 313 interrupt-controller; 314 #interrupt-cells = <1>; 315 interrupt-parent = <&gic>; 316 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 }; 319 320 chip: chip-control@ea0000 { 321 compatible = "marvell,berlin2q-chip-ctrl"; 322 #clock-cells = <1>; 323 reg = <0xea0000 0x400>, <0xdd0170 0x10>; 324 clocks = <&refclk>; 325 clock-names = "refclk"; 326 327 twsi0_pmux: twsi0-pmux { 328 groups = "G6"; 329 function = "twsi0"; 330 }; 331 332 twsi1_pmux: twsi1-pmux { 333 groups = "G7"; 334 function = "twsi1"; 335 }; 336 }; 337 338 apb@fc0000 { 339 compatible = "simple-bus"; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 343 ranges = <0 0xfc0000 0x10000>; 344 interrupt-parent = <&sic>; 345 346 sm_gpio1: gpio@5000 { 347 compatible = "snps,dw-apb-gpio"; 348 reg = <0x5000 0x400>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 352 portf: gpio-port@5 { 353 compatible = "snps,dw-apb-gpio-port"; 354 gpio-controller; 355 #gpio-cells = <2>; 356 snps,nr-gpios = <32>; 357 reg = <0>; 358 }; 359 }; 360 361 i2c2: i2c@7000 { 362 compatible = "snps,designware-i2c"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <0x7000 0x100>; 366 interrupt-parent = <&sic>; 367 interrupts = <6>; 368 clocks = <&refclk>; 369 pinctrl-0 = <&twsi2_pmux>; 370 pinctrl-names = "default"; 371 status = "disabled"; 372 }; 373 374 i2c3: i2c@8000 { 375 compatible = "snps,designware-i2c"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 reg = <0x8000 0x100>; 379 interrupt-parent = <&sic>; 380 interrupts = <7>; 381 clocks = <&refclk>; 382 pinctrl-0 = <&twsi3_pmux>; 383 pinctrl-names = "default"; 384 status = "disabled"; 385 }; 386 387 uart0: uart@9000 { 388 compatible = "snps,dw-apb-uart"; 389 reg = <0x9000 0x100>; 390 interrupt-parent = <&sic>; 391 interrupts = <8>; 392 clocks = <&refclk>; 393 reg-shift = <2>; 394 pinctrl-0 = <&uart0_pmux>; 395 pinctrl-names = "default"; 396 status = "disabled"; 397 }; 398 399 uart1: uart@a000 { 400 compatible = "snps,dw-apb-uart"; 401 reg = <0xa000 0x100>; 402 interrupt-parent = <&sic>; 403 interrupts = <9>; 404 clocks = <&refclk>; 405 reg-shift = <2>; 406 pinctrl-0 = <&uart1_pmux>; 407 pinctrl-names = "default"; 408 status = "disabled"; 409 }; 410 411 sm_gpio0: gpio@c000 { 412 compatible = "snps,dw-apb-gpio"; 413 reg = <0xc000 0x400>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 porte: gpio-port@4 { 418 compatible = "snps,dw-apb-gpio-port"; 419 gpio-controller; 420 #gpio-cells = <2>; 421 snps,nr-gpios = <32>; 422 reg = <0>; 423 }; 424 }; 425 426 sysctrl: pin-controller@d000 { 427 compatible = "marvell,berlin2q-system-ctrl"; 428 reg = <0xd000 0x100>; 429 430 uart0_pmux: uart0-pmux { 431 groups = "GSM12"; 432 function = "uart0"; 433 }; 434 435 uart1_pmux: uart1-pmux { 436 groups = "GSM14"; 437 function = "uart1"; 438 }; 439 440 twsi2_pmux: twsi2-pmux { 441 groups = "GSM13"; 442 function = "twsi2"; 443 }; 444 445 twsi3_pmux: twsi3-pmux { 446 groups = "GSM14"; 447 function = "twsi3"; 448 }; 449 }; 450 451 sic: interrupt-controller@e000 { 452 compatible = "snps,dw-apb-ictl"; 453 reg = <0xe000 0x30>; 454 interrupt-controller; 455 #interrupt-cells = <1>; 456 interrupt-parent = <&gic>; 457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 458 }; 459 }; 460 }; 461}; 462