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1/*
2 * Copyright (c) 2013-2014 Linaro Ltd.
3 * Copyright (c) 2013-2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10#include "skeleton.dtsi"
11#include <dt-bindings/clock/hix5hd2-clock.h>
12
13/ {
14	aliases {
15		serial0 = &uart0;
16	};
17
18	gic: interrupt-controller@f8a01000 {
19		compatible = "arm,cortex-a9-gic";
20		#interrupt-cells = <3>;
21		#address-cells = <0>;
22		interrupt-controller;
23		/* gic dist base, gic cpu base */
24		reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
25	};
26
27	soc {
28		#address-cells = <1>;
29		#size-cells = <1>;
30		compatible = "simple-bus";
31		interrupt-parent = <&gic>;
32		ranges = <0 0xf8000000 0x8000000>;
33
34		amba {
35			#address-cells = <1>;
36			#size-cells = <1>;
37			compatible = "arm,amba-bus";
38			ranges;
39
40			timer0: timer@00002000 {
41				compatible = "arm,sp804", "arm,primecell";
42				reg = <0x00002000 0x1000>;
43				/* timer00 & timer01 */
44				interrupts = <0 24 4>;
45				clocks = <&clock HIX5HD2_FIXED_24M>;
46				status = "disabled";
47			};
48
49			timer1: timer@00a29000 {
50				/*
51				 * Only used in NORMAL state, not available ins
52				 * SLOW or DOZE state.
53				 * The rate is fixed in 24MHz.
54				 */
55				compatible = "arm,sp804", "arm,primecell";
56				reg = <0x00a29000 0x1000>;
57				/* timer10 & timer11 */
58				interrupts = <0 25 4>;
59				clocks = <&clock HIX5HD2_FIXED_24M>;
60				status = "disabled";
61			};
62
63			timer2: timer@00a2a000 {
64				compatible = "arm,sp804", "arm,primecell";
65				reg = <0x00a2a000 0x1000>;
66				/* timer20 & timer21 */
67				interrupts = <0 26 4>;
68				clocks = <&clock HIX5HD2_FIXED_24M>;
69				status = "disabled";
70			};
71
72			timer3: timer@00a2b000 {
73				compatible = "arm,sp804", "arm,primecell";
74				reg = <0x00a2b000 0x1000>;
75				/* timer30 & timer31 */
76				interrupts = <0 27 4>;
77				clocks = <&clock HIX5HD2_FIXED_24M>;
78				status = "disabled";
79			};
80
81			timer4: timer@00a81000 {
82				compatible = "arm,sp804", "arm,primecell";
83				reg = <0x00a81000 0x1000>;
84				/* timer30 & timer31 */
85				interrupts = <0 28 4>;
86				clocks = <&clock HIX5HD2_FIXED_24M>;
87				status = "disabled";
88			};
89
90			uart0: uart@00b00000 {
91				compatible = "arm,pl011", "arm,primecell";
92				reg = <0x00b00000 0x1000>;
93				interrupts = <0 49 4>;
94				clocks = <&clock HIX5HD2_FIXED_83M>;
95				clock-names = "apb_pclk";
96				status = "disabled";
97			};
98
99			uart1: uart@00006000 {
100				compatible = "arm,pl011", "arm,primecell";
101				reg = <0x00006000 0x1000>;
102				interrupts = <0 50 4>;
103				clocks = <&clock HIX5HD2_FIXED_83M>;
104				clock-names = "apb_pclk";
105				status = "disabled";
106			};
107
108			uart2: uart@00b02000 {
109				compatible = "arm,pl011", "arm,primecell";
110				reg = <0x00b02000 0x1000>;
111				interrupts = <0 51 4>;
112				clocks = <&clock HIX5HD2_FIXED_83M>;
113				clock-names = "apb_pclk";
114				status = "disabled";
115			};
116
117			uart3: uart@00b03000 {
118				compatible = "arm,pl011", "arm,primecell";
119				reg = <0x00b03000 0x1000>;
120				interrupts = <0 52 4>;
121				clocks = <&clock HIX5HD2_FIXED_83M>;
122				clock-names = "apb_pclk";
123				status = "disabled";
124			};
125
126			uart4: uart@00b04000 {
127				compatible = "arm,pl011", "arm,primecell";
128				reg = <0xb04000 0x1000>;
129				interrupts = <0 53 4>;
130				clocks = <&clock HIX5HD2_FIXED_83M>;
131				clock-names = "apb_pclk";
132				status = "disabled";
133			};
134		};
135
136		local_timer@00a00600 {
137			compatible = "arm,cortex-a9-twd-timer";
138			reg = <0x00a00600 0x20>;
139			interrupts = <1 13 0xf01>;
140		};
141
142		l2: l2-cache {
143			compatible = "arm,pl310-cache";
144			reg = <0x00a10000 0x100000>;
145			interrupts = <0 15 4>;
146			cache-unified;
147			cache-level = <2>;
148		};
149
150		sysctrl: system-controller@00000000 {
151			compatible = "hisilicon,sysctrl";
152			reg = <0x00000000 0x1000>;
153			reboot-offset = <0x4>;
154		};
155
156		cpuctrl@00a22000 {
157			compatible = "hisilicon,cpuctrl";
158			#address-cells = <1>;
159			#size-cells = <1>;
160			reg = <0x00a22000 0x2000>;
161			ranges = <0 0x00a22000 0x2000>;
162
163			clock: clock@0 {
164				compatible = "hisilicon,hix5hd2-clock";
165				reg = <0 0x2000>;
166				#clock-cells = <1>;
167			};
168		};
169	};
170};
171