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1/*
2 * DTS file for CSR SiRFmarco SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11	compatible = "sirf,marco";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a9";
23			reg = <0>;
24		};
25		cpu@1 {
26			device_type = "cpu";
27			compatible = "arm,cortex-a9";
28			reg = <1>;
29		};
30	};
31
32	axi {
33		compatible = "simple-bus";
34		#address-cells = <1>;
35		#size-cells = <1>;
36		ranges = <0x40000000 0x40000000 0xa0000000>;
37
38		l2-cache-controller@c0030000 {
39			compatible = "arm,pl310-cache";
40			reg = <0xc0030000 0x1000>;
41			interrupts = <0 59 0>;
42			arm,tag-latency = <1 1 1>;
43			arm,data-latency = <1 1 1>;
44			arm,filter-ranges = <0x40000000 0x80000000>;
45		};
46
47		gic: interrupt-controller@c0011000 {
48			compatible = "arm,cortex-a9-gic";
49			interrupt-controller;
50			#interrupt-cells = <3>;
51			reg = <0xc0011000 0x1000>,
52			      <0xc0010100 0x0100>;
53		};
54
55		rstc-iobg {
56			compatible = "simple-bus";
57			#address-cells = <1>;
58			#size-cells = <1>;
59			ranges = <0xc2000000 0xc2000000 0x1000000>;
60
61			rstc: reset-controller@c2000000 {
62				compatible = "sirf,marco-rstc";
63				reg = <0xc2000000 0x10000>;
64				#reset-cells = <1>;
65			};
66		};
67
68		sys-iobg {
69			compatible = "simple-bus";
70			#address-cells = <1>;
71			#size-cells = <1>;
72			ranges = <0xc3000000 0xc3000000 0x1000000>;
73
74			clock-controller@c3000000 {
75				compatible = "sirf,marco-clkc";
76				reg = <0xc3000000 0x1000>;
77				interrupts = <0 3 0>;
78			};
79
80			rsc-controller@c3010000 {
81				compatible = "sirf,marco-rsc";
82				reg = <0xc3010000 0x1000>;
83			};
84		};
85
86		mem-iobg {
87			compatible = "simple-bus";
88			#address-cells = <1>;
89			#size-cells = <1>;
90			ranges = <0xc4000000 0xc4000000 0x1000000>;
91
92			memory-controller@c4000000 {
93				compatible = "sirf,marco-memc";
94				reg = <0xc4000000 0x10000>;
95				interrupts = <0 27 0>;
96			};
97		};
98
99		disp-iobg0 {
100			compatible = "simple-bus";
101			#address-cells = <1>;
102			#size-cells = <1>;
103			ranges = <0xc5000000 0xc5000000 0x1000000>;
104
105			display0@c5000000 {
106				compatible = "sirf,marco-lcd";
107				reg = <0xc5000000 0x10000>;
108				interrupts = <0 30 0>;
109			};
110
111			vpp0@c5010000 {
112				compatible = "sirf,marco-vpp";
113				reg = <0xc5010000 0x10000>;
114				interrupts = <0 31 0>;
115			};
116		};
117
118		disp-iobg1 {
119			compatible = "simple-bus";
120			#address-cells = <1>;
121			#size-cells = <1>;
122			ranges = <0xc6000000 0xc6000000 0x1000000>;
123
124			display1@c6000000 {
125				compatible = "sirf,marco-lcd";
126				reg = <0xc6000000 0x10000>;
127				interrupts = <0 62 0>;
128			};
129
130			vpp1@c6010000 {
131				compatible = "sirf,marco-vpp";
132				reg = <0xc6010000 0x10000>;
133				interrupts = <0 63 0>;
134			};
135		};
136
137		graphics-iobg {
138			compatible = "simple-bus";
139			#address-cells = <1>;
140			#size-cells = <1>;
141			ranges = <0xc8000000 0xc8000000 0x1000000>;
142
143			graphics@c8000000 {
144				compatible = "powervr,sgx540";
145				reg = <0xc8000000 0x1000000>;
146				interrupts = <0 6 0>;
147			};
148		};
149
150		multimedia-iobg {
151			compatible = "simple-bus";
152			#address-cells = <1>;
153			#size-cells = <1>;
154			ranges = <0xc9000000 0xc9000000 0x1000000>;
155
156			multimedia@a0000000 {
157				compatible = "sirf,marco-video-codec";
158				reg = <0xc9000000 0x1000000>;
159				interrupts = <0 5 0>;
160			};
161		};
162
163		dsp-iobg {
164			compatible = "simple-bus";
165			#address-cells = <1>;
166			#size-cells = <1>;
167			ranges = <0xca000000 0xca000000 0x2000000>;
168
169			dspif@ca000000 {
170				compatible = "sirf,marco-dspif";
171				reg = <0xca000000 0x10000>;
172				interrupts = <0 9 0>;
173			};
174
175			gps@ca010000 {
176				compatible = "sirf,marco-gps";
177				reg = <0xca010000 0x10000>;
178				interrupts = <0 7 0>;
179			};
180
181			dsp@cb000000 {
182				compatible = "sirf,marco-dsp";
183				reg = <0xcb000000 0x1000000>;
184				interrupts = <0 8 0>;
185			};
186		};
187
188		peri-iobg {
189			compatible = "simple-bus";
190			#address-cells = <1>;
191			#size-cells = <1>;
192			ranges = <0xcc000000 0xcc000000 0x2000000>;
193
194			timer@cc020000 {
195				compatible = "sirf,marco-tick";
196				reg = <0xcc020000 0x1000>;
197				interrupts = <0 0 0>,
198					   <0 1 0>,
199					   <0 2 0>,
200					   <0 49 0>,
201					   <0 50 0>,
202					   <0 51 0>;
203			};
204
205			nand@cc030000 {
206				compatible = "sirf,marco-nand";
207				reg = <0xcc030000 0x10000>;
208				interrupts = <0 41 0>;
209			};
210
211			audio@cc040000 {
212				compatible = "sirf,marco-audio";
213				reg = <0xcc040000 0x10000>;
214				interrupts = <0 35 0>;
215			};
216
217			uart0: uart@cc050000 {
218				cell-index = <0>;
219				compatible = "sirf,marco-uart";
220				reg = <0xcc050000 0x1000>;
221				interrupts = <0 17 0>;
222				fifosize = <128>;
223				status = "disabled";
224			};
225
226			uart1: uart@cc060000 {
227				cell-index = <1>;
228				compatible = "sirf,marco-uart";
229				reg = <0xcc060000 0x1000>;
230				interrupts = <0 18 0>;
231				fifosize = <32>;
232				status = "disabled";
233			};
234
235			uart2: uart@cc070000 {
236				cell-index = <2>;
237				compatible = "sirf,marco-uart";
238				reg = <0xcc070000 0x1000>;
239				interrupts = <0 19 0>;
240				fifosize = <128>;
241				status = "disabled";
242			};
243
244			uart3: uart@cc190000 {
245				cell-index = <3>;
246				compatible = "sirf,marco-uart";
247				reg = <0xcc190000 0x1000>;
248				interrupts = <0 66 0>;
249				fifosize = <128>;
250				status = "disabled";
251			};
252
253			uart4: uart@cc1a0000 {
254				cell-index = <4>;
255				compatible = "sirf,marco-uart";
256				reg = <0xcc1a0000 0x1000>;
257				interrupts = <0 69 0>;
258				fifosize = <128>;
259				status = "disabled";
260			};
261
262			usp0: usp@cc080000 {
263				cell-index = <0>;
264				compatible = "sirf,marco-usp";
265				reg = <0xcc080000 0x10000>;
266				interrupts = <0 20 0>;
267				status = "disabled";
268			};
269
270			usp1: usp@cc090000 {
271				cell-index = <1>;
272				compatible = "sirf,marco-usp";
273				reg = <0xcc090000 0x10000>;
274				interrupts = <0 21 0>;
275				status = "disabled";
276			};
277
278			usp2: usp@cc0a0000 {
279				cell-index = <2>;
280				compatible = "sirf,marco-usp";
281				reg = <0xcc0a0000 0x10000>;
282				interrupts = <0 22 0>;
283				status = "disabled";
284			};
285
286			dmac0: dma-controller@cc0b0000 {
287				cell-index = <0>;
288				compatible = "sirf,marco-dmac";
289				reg = <0xcc0b0000 0x10000>;
290				interrupts = <0 12 0>;
291			};
292
293			dmac1: dma-controller@cc160000 {
294				cell-index = <1>;
295				compatible = "sirf,marco-dmac";
296				reg = <0xcc160000 0x10000>;
297				interrupts = <0 13 0>;
298			};
299
300			vip@cc0c0000 {
301				compatible = "sirf,marco-vip";
302				reg = <0xcc0c0000 0x10000>;
303			};
304
305			spi0: spi@cc0d0000 {
306				cell-index = <0>;
307				compatible = "sirf,marco-spi";
308				reg = <0xcc0d0000 0x10000>;
309				interrupts = <0 15 0>;
310				sirf,spi-num-chipselects = <1>;
311				cs-gpios = <&gpio 0 0>;
312				sirf,spi-dma-rx-channel = <25>;
313				sirf,spi-dma-tx-channel = <20>;
314				#address-cells = <1>;
315				#size-cells = <0>;
316				status = "disabled";
317			};
318
319			spi1: spi@cc170000 {
320				cell-index = <1>;
321				compatible = "sirf,marco-spi";
322				reg = <0xcc170000 0x10000>;
323				interrupts = <0 16 0>;
324				sirf,spi-num-chipselects = <1>;
325				cs-gpios = <&gpio 0 0>;
326				sirf,spi-dma-rx-channel = <12>;
327				sirf,spi-dma-tx-channel = <13>;
328				#address-cells = <1>;
329				#size-cells = <0>;
330				status = "disabled";
331			};
332
333			i2c0: i2c@cc0e0000 {
334				cell-index = <0>;
335				compatible = "sirf,marco-i2c";
336				reg = <0xcc0e0000 0x10000>;
337				interrupts = <0 24 0>;
338				#address-cells = <1>;
339				#size-cells = <0>;
340				status = "disabled";
341			};
342
343			i2c1: i2c@cc0f0000 {
344				cell-index = <1>;
345				compatible = "sirf,marco-i2c";
346				reg = <0xcc0f0000 0x10000>;
347				interrupts = <0 25 0>;
348				#address-cells = <1>;
349				#size-cells = <0>;
350				status = "disabled";
351			};
352
353			tsc@cc110000 {
354				compatible = "sirf,marco-tsc";
355				reg = <0xcc110000 0x10000>;
356				interrupts = <0 33 0>;
357			};
358
359			gpio: pinctrl@cc120000 {
360				#gpio-cells = <2>;
361				#interrupt-cells = <2>;
362				compatible = "sirf,marco-pinctrl";
363				reg = <0xcc120000 0x10000>;
364				interrupts = <0 43 0>,
365					   <0 44 0>,
366					   <0 45 0>,
367					   <0 46 0>,
368					   <0 47 0>;
369				gpio-controller;
370				interrupt-controller;
371
372				lcd_16pins_a: lcd0_0 {
373					lcd {
374						sirf,pins = "lcd_16bitsgrp";
375						sirf,function = "lcd_16bits";
376					};
377				};
378				lcd_18pins_a: lcd0_1 {
379					lcd {
380						sirf,pins = "lcd_18bitsgrp";
381						sirf,function = "lcd_18bits";
382					};
383				};
384				lcd_24pins_a: lcd0_2 {
385					lcd {
386						sirf,pins = "lcd_24bitsgrp";
387						sirf,function = "lcd_24bits";
388					};
389				};
390				lcdrom_pins_a: lcdrom0_0 {
391					lcd {
392						sirf,pins = "lcdromgrp";
393						sirf,function = "lcdrom";
394					};
395				};
396				uart0_pins_a: uart0_0 {
397					uart {
398						sirf,pins = "uart0grp";
399						sirf,function = "uart0";
400					};
401				};
402				uart1_pins_a: uart1_0 {
403					uart {
404						sirf,pins = "uart1grp";
405						sirf,function = "uart1";
406					};
407				};
408				uart2_pins_a: uart2_0 {
409					uart {
410						sirf,pins = "uart2grp";
411						sirf,function = "uart2";
412					};
413				};
414				uart2_noflow_pins_a: uart2_1 {
415					uart {
416						sirf,pins = "uart2_nostreamctrlgrp";
417						sirf,function = "uart2_nostreamctrl";
418					};
419				};
420				spi0_pins_a: spi0_0 {
421					spi {
422						sirf,pins = "spi0grp";
423						sirf,function = "spi0";
424					};
425				};
426				spi1_pins_a: spi1_0 {
427					spi {
428						sirf,pins = "spi1grp";
429						sirf,function = "spi1";
430					};
431				};
432				i2c0_pins_a: i2c0_0 {
433					i2c {
434						sirf,pins = "i2c0grp";
435						sirf,function = "i2c0";
436					};
437				};
438				i2c1_pins_a: i2c1_0 {
439					i2c {
440						sirf,pins = "i2c1grp";
441						sirf,function = "i2c1";
442					};
443				};
444				pwm0_pins_a: pwm0_0 {
445				        pwm {
446				                sirf,pins = "pwm0grp";
447				                sirf,function = "pwm0";
448				        };
449				};
450				pwm1_pins_a: pwm1_0 {
451				        pwm {
452				                sirf,pins = "pwm1grp";
453				                sirf,function = "pwm1";
454				        };
455				};
456				pwm2_pins_a: pwm2_0 {
457				        pwm {
458				                sirf,pins = "pwm2grp";
459				                sirf,function = "pwm2";
460				        };
461				};
462				pwm3_pins_a: pwm3_0 {
463				        pwm {
464				                sirf,pins = "pwm3grp";
465				                sirf,function = "pwm3";
466				        };
467				};
468				gps_pins_a: gps_0 {
469				        gps {
470				                sirf,pins = "gpsgrp";
471				                sirf,function = "gps";
472				        };
473				};
474				vip_pins_a: vip_0 {
475				        vip {
476				                sirf,pins = "vipgrp";
477				                sirf,function = "vip";
478				        };
479				};
480				sdmmc0_pins_a: sdmmc0_0 {
481				        sdmmc0 {
482				                sirf,pins = "sdmmc0grp";
483				                sirf,function = "sdmmc0";
484				        };
485				};
486				sdmmc1_pins_a: sdmmc1_0 {
487				        sdmmc1 {
488				                sirf,pins = "sdmmc1grp";
489				                sirf,function = "sdmmc1";
490				        };
491				};
492				sdmmc2_pins_a: sdmmc2_0 {
493				        sdmmc2 {
494				                sirf,pins = "sdmmc2grp";
495				                sirf,function = "sdmmc2";
496				        };
497				};
498				sdmmc3_pins_a: sdmmc3_0 {
499				        sdmmc3 {
500				                sirf,pins = "sdmmc3grp";
501				                sirf,function = "sdmmc3";
502				        };
503				};
504				sdmmc4_pins_a: sdmmc4_0 {
505				        sdmmc4 {
506				                sirf,pins = "sdmmc4grp";
507				                sirf,function = "sdmmc4";
508				        };
509				};
510				sdmmc5_pins_a: sdmmc5_0 {
511				        sdmmc5 {
512				                sirf,pins = "sdmmc5grp";
513				                sirf,function = "sdmmc5";
514				        };
515				};
516				i2s_pins_a: i2s_0 {
517				        i2s {
518				                sirf,pins = "i2sgrp";
519				                sirf,function = "i2s";
520				        };
521				};
522				ac97_pins_a: ac97_0 {
523				        ac97 {
524				                sirf,pins = "ac97grp";
525				                sirf,function = "ac97";
526				        };
527				};
528				nand_pins_a: nand_0 {
529				        nand {
530				                sirf,pins = "nandgrp";
531				                sirf,function = "nand";
532				        };
533				};
534				usp0_pins_a: usp0_0 {
535				        usp0 {
536				                sirf,pins = "usp0grp";
537				                sirf,function = "usp0";
538				        };
539				};
540				usp1_pins_a: usp1_0 {
541				        usp1 {
542				                sirf,pins = "usp1grp";
543				                sirf,function = "usp1";
544				        };
545				};
546				usp2_pins_a: usp2_0 {
547				        usp2 {
548				                sirf,pins = "usp2grp";
549				                sirf,function = "usp2";
550				        };
551				};
552				usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
553				        usb0_utmi_drvbus {
554				                sirf,pins = "usb0_utmi_drvbusgrp";
555				                sirf,function = "usb0_utmi_drvbus";
556				        };
557				};
558				usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
559				        usb1_utmi_drvbus {
560				                sirf,pins = "usb1_utmi_drvbusgrp";
561				                sirf,function = "usb1_utmi_drvbus";
562				        };
563				};
564				warm_rst_pins_a: warm_rst_0 {
565				        warm_rst {
566				                sirf,pins = "warm_rstgrp";
567				                sirf,function = "warm_rst";
568				        };
569				};
570				pulse_count_pins_a: pulse_count_0 {
571				        pulse_count {
572				                sirf,pins = "pulse_countgrp";
573				                sirf,function = "pulse_count";
574				        };
575				};
576				cko0_rst_pins_a: cko0_rst_0 {
577				        cko0_rst {
578				                sirf,pins = "cko0_rstgrp";
579				                sirf,function = "cko0_rst";
580				        };
581				};
582				cko1_rst_pins_a: cko1_rst_0 {
583				        cko1_rst {
584				                sirf,pins = "cko1_rstgrp";
585				                sirf,function = "cko1_rst";
586				        };
587				};
588			};
589
590			pwm@cc130000 {
591				compatible = "sirf,marco-pwm";
592				reg = <0xcc130000 0x10000>;
593			};
594
595			efusesys@cc140000 {
596				compatible = "sirf,marco-efuse";
597				reg = <0xcc140000 0x10000>;
598			};
599
600			pulsec@cc150000 {
601				compatible = "sirf,marco-pulsec";
602				reg = <0xcc150000 0x10000>;
603				interrupts = <0 48 0>;
604			};
605
606			pci-iobg {
607				compatible = "sirf,marco-pciiobg", "simple-bus";
608				#address-cells = <1>;
609				#size-cells = <1>;
610				ranges = <0xcd000000 0xcd000000 0x1000000>;
611
612				sd0: sdhci@cd000000 {
613					cell-index = <0>;
614					compatible = "sirf,marco-sdhc";
615					reg = <0xcd000000 0x100000>;
616					interrupts = <0 38 0>;
617					status = "disabled";
618				};
619
620				sd1: sdhci@cd100000 {
621					cell-index = <1>;
622					compatible = "sirf,marco-sdhc";
623					reg = <0xcd100000 0x100000>;
624					interrupts = <0 38 0>;
625					status = "disabled";
626				};
627
628				sd2: sdhci@cd200000 {
629					cell-index = <2>;
630					compatible = "sirf,marco-sdhc";
631					reg = <0xcd200000 0x100000>;
632					interrupts = <0 23 0>;
633					status = "disabled";
634				};
635
636				sd3: sdhci@cd300000 {
637					cell-index = <3>;
638					compatible = "sirf,marco-sdhc";
639					reg = <0xcd300000 0x100000>;
640					interrupts = <0 23 0>;
641					status = "disabled";
642				};
643
644				sd4: sdhci@cd400000 {
645					cell-index = <4>;
646					compatible = "sirf,marco-sdhc";
647					reg = <0xcd400000 0x100000>;
648					interrupts = <0 39 0>;
649					status = "disabled";
650				};
651
652				sd5: sdhci@cd500000 {
653					cell-index = <5>;
654					compatible = "sirf,marco-sdhc";
655					reg = <0xcd500000 0x100000>;
656					interrupts = <0 39 0>;
657					status = "disabled";
658				};
659
660				pci-copy@cd900000 {
661					compatible = "sirf,marco-pcicp";
662					reg = <0xcd900000 0x100000>;
663					interrupts = <0 40 0>;
664				};
665
666				rom-interface@cda00000 {
667					compatible = "sirf,marco-romif";
668					reg = <0xcda00000 0x100000>;
669				};
670			};
671		};
672
673		rtc-iobg {
674			compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
675			#address-cells = <1>;
676			#size-cells = <1>;
677			reg = <0xc1000000 0x10000>;
678
679			gpsrtc@1000 {
680				compatible = "sirf,marco-gpsrtc";
681				reg = <0x1000 0x1000>;
682				interrupts = <0 55 0>,
683					   <0 56 0>,
684					   <0 57 0>;
685			};
686
687			sysrtc@2000 {
688				compatible = "sirf,marco-sysrtc";
689				reg = <0x2000 0x1000>;
690				interrupts = <0 52 0>,
691					   <0 53 0>,
692					   <0 54 0>;
693			};
694
695			pwrc@3000 {
696				compatible = "sirf,marco-pwrc";
697				reg = <0x3000 0x1000>;
698				interrupts = <0 32 0>;
699			};
700		};
701
702		uus-iobg {
703			compatible = "simple-bus";
704			#address-cells = <1>;
705			#size-cells = <1>;
706			ranges = <0xce000000 0xce000000 0x1000000>;
707
708			usb0: usb@ce000000 {
709				compatible = "chipidea,ci13611a-marco";
710				reg = <0xce000000 0x10000>;
711				interrupts = <0 10 0>;
712			};
713
714			usb1: usb@ce010000 {
715				compatible = "chipidea,ci13611a-marco";
716				reg = <0xce010000 0x10000>;
717				interrupts = <0 11 0>;
718			};
719
720			security@ce020000 {
721				compatible = "sirf,marco-security";
722				reg = <0xce020000 0x10000>;
723				interrupts = <0 42 0>;
724			};
725		};
726
727		can-iobg {
728			compatible = "simple-bus";
729			#address-cells = <1>;
730			#size-cells = <1>;
731			ranges = <0xd0000000 0xd0000000 0x1000000>;
732
733			can0: can@d0000000 {
734				compatible = "sirf,marco-can";
735				reg = <0xd0000000 0x10000>;
736			};
737
738			can1: can@d0010000 {
739				compatible = "sirf,marco-can";
740				reg = <0xd0010000 0x10000>;
741			};
742		};
743
744		lvds-iobg {
745			compatible = "simple-bus";
746			#address-cells = <1>;
747			#size-cells = <1>;
748			ranges = <0xd1000000 0xd1000000 0x1000000>;
749
750			lvds@d1000000 {
751				compatible = "sirf,marco-lvds";
752				reg = <0xd1000000 0x10000>;
753				interrupts = <0 64 0>;
754			};
755		};
756	};
757};
758