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1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10	model = "Qualcomm MSM8660";
11	compatible = "qcom,msm8660";
12	interrupt-parent = <&intc>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			compatible = "qcom,scorpion";
20			enable-method = "qcom,gcc-msm8660";
21			device_type = "cpu";
22			reg = <0>;
23			next-level-cache = <&L2>;
24		};
25
26		cpu@1 {
27			compatible = "qcom,scorpion";
28			enable-method = "qcom,gcc-msm8660";
29			device_type = "cpu";
30			reg = <1>;
31			next-level-cache = <&L2>;
32		};
33
34		L2: l2-cache {
35			compatible = "cache";
36			cache-level = <2>;
37		};
38	};
39
40	soc: soc {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		ranges;
44		compatible = "simple-bus";
45
46		intc: interrupt-controller@2080000 {
47			compatible = "qcom,msm-8660-qgic";
48			interrupt-controller;
49			#interrupt-cells = <3>;
50			reg = < 0x02080000 0x1000 >,
51			      < 0x02081000 0x1000 >;
52		};
53
54		timer@2000000 {
55			compatible = "qcom,scss-timer", "qcom,msm-timer";
56			interrupts = <1 0 0x301>,
57				     <1 1 0x301>,
58				     <1 2 0x301>;
59			reg = <0x02000000 0x100>;
60			clock-frequency = <27000000>,
61					  <32768>;
62			cpu-offset = <0x40000>;
63		};
64
65		msmgpio: gpio@800000 {
66			compatible = "qcom,msm-gpio";
67			reg = <0x00800000 0x4000>;
68			gpio-controller;
69			#gpio-cells = <2>;
70			ngpio = <173>;
71			interrupts = <0 16 0x4>;
72			interrupt-controller;
73			#interrupt-cells = <2>;
74		};
75
76		gcc: clock-controller@900000 {
77			compatible = "qcom,gcc-msm8660";
78			#clock-cells = <1>;
79			#reset-cells = <1>;
80			reg = <0x900000 0x4000>;
81		};
82
83		gsbi12: gsbi@19c00000 {
84			compatible = "qcom,gsbi-v1.0.0";
85			reg = <0x19c00000 0x100>;
86			clocks = <&gcc GSBI12_H_CLK>;
87			clock-names = "iface";
88			#address-cells = <1>;
89			#size-cells = <1>;
90			ranges;
91
92			serial@19c40000 {
93				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
94				reg = <0x19c40000 0x1000>,
95				      <0x19c00000 0x1000>;
96				interrupts = <0 195 0x0>;
97				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
98				clock-names = "core", "iface";
99				status = "disabled";
100			};
101		};
102
103		qcom,ssbi@500000 {
104			compatible = "qcom,ssbi";
105			reg = <0x500000 0x1000>;
106			qcom,controller-type = "pmic-arbiter";
107
108			pmicintc: pmic@0 {
109				compatible = "qcom,pm8058";
110				interrupt-parent = <&msmgpio>;
111				interrupts = <88 8>;
112				#interrupt-cells = <2>;
113				interrupt-controller;
114				#address-cells = <1>;
115				#size-cells = <0>;
116
117				pwrkey@1c {
118					compatible = "qcom,pm8058-pwrkey";
119					reg = <0x1c>;
120					interrupt-parent = <&pmicintc>;
121					interrupts = <50 1>, <51 1>;
122					debounce = <15625>;
123					pull-up;
124				};
125
126				keypad@148 {
127					compatible = "qcom,pm8058-keypad";
128					reg = <0x148>;
129					interrupt-parent = <&pmicintc>;
130					interrupts = <74 1>, <75 1>;
131					debounce = <15>;
132					scan-delay = <32>;
133					row-hold = <91500>;
134				};
135
136				rtc@11d {
137					compatible = "qcom,pm8058-rtc";
138					interrupt-parent = <&pmicintc>;
139					interrupts = <39 1>;
140					reg = <0x11d>;
141					allow-set-time;
142				};
143
144				vibrator@4a {
145					compatible = "qcom,pm8058-vib";
146					reg = <0x4a>;
147				};
148			};
149		};
150
151		/* Temporary fixed regulator */
152		vsdcc_fixed: vsdcc-regulator {
153			compatible = "regulator-fixed";
154			regulator-name = "SDCC Power";
155			regulator-min-microvolt = <2700000>;
156			regulator-max-microvolt = <2700000>;
157			regulator-always-on;
158		};
159
160		amba {
161			compatible = "arm,amba-bus";
162			#address-cells = <1>;
163			#size-cells = <1>;
164			ranges;
165			sdcc1: sdcc@12400000 {
166				status		= "disabled";
167				compatible	= "arm,pl18x", "arm,primecell";
168				arm,primecell-periphid = <0x00051180>;
169				reg		= <0x12400000 0x8000>;
170				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
171				interrupt-names	= "cmd_irq";
172				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
173				clock-names	= "mclk", "apb_pclk";
174				bus-width	= <8>;
175				max-frequency	= <48000000>;
176				non-removable;
177				cap-sd-highspeed;
178				cap-mmc-highspeed;
179				vmmc-supply = <&vsdcc_fixed>;
180			};
181
182			sdcc3: sdcc@12180000 {
183				compatible	= "arm,pl18x", "arm,primecell";
184				arm,primecell-periphid = <0x00051180>;
185				status		= "disabled";
186				reg		= <0x12180000 0x8000>;
187				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
188				interrupt-names	= "cmd_irq";
189				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
190				clock-names	= "mclk", "apb_pclk";
191				bus-width	= <4>;
192				cap-sd-highspeed;
193				cap-mmc-highspeed;
194				max-frequency	= <48000000>;
195				no-1-8-v;
196				vmmc-supply = <&vsdcc_fixed>;
197			};
198		};
199	};
200
201};
202