1/* 2 * Copyright 2012 Stefan Roese 3 * Stefan Roese <sr@denx.de> 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13/include/ "skeleton.dtsi" 14 15/ { 16 interrupt-parent = <&intc>; 17 18 aliases { 19 ethernet0 = &emac; 20 serial0 = &uart0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 serial4 = &uart4; 25 serial5 = &uart5; 26 serial6 = &uart6; 27 serial7 = &uart7; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a8"; 36 reg = <0x0>; 37 }; 38 }; 39 40 memory { 41 reg = <0x40000000 0x80000000>; 42 }; 43 44 clocks { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges; 48 49 /* 50 * This is a dummy clock, to be used as placeholder on 51 * other mux clocks when a specific parent clock is not 52 * yet implemented. It should be dropped when the driver 53 * is complete. 54 */ 55 dummy: dummy { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <0>; 59 }; 60 61 osc24M: clk@01c20050 { 62 #clock-cells = <0>; 63 compatible = "allwinner,sun4i-a10-osc-clk"; 64 reg = <0x01c20050 0x4>; 65 clock-frequency = <24000000>; 66 clock-output-names = "osc24M"; 67 }; 68 69 osc32k: clk@0 { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 clock-output-names = "osc32k"; 74 }; 75 76 pll1: clk@01c20000 { 77 #clock-cells = <0>; 78 compatible = "allwinner,sun4i-a10-pll1-clk"; 79 reg = <0x01c20000 0x4>; 80 clocks = <&osc24M>; 81 clock-output-names = "pll1"; 82 }; 83 84 pll4: clk@01c20018 { 85 #clock-cells = <0>; 86 compatible = "allwinner,sun4i-a10-pll1-clk"; 87 reg = <0x01c20018 0x4>; 88 clocks = <&osc24M>; 89 clock-output-names = "pll4"; 90 }; 91 92 pll5: clk@01c20020 { 93 #clock-cells = <1>; 94 compatible = "allwinner,sun4i-a10-pll5-clk"; 95 reg = <0x01c20020 0x4>; 96 clocks = <&osc24M>; 97 clock-output-names = "pll5_ddr", "pll5_other"; 98 }; 99 100 pll6: clk@01c20028 { 101 #clock-cells = <1>; 102 compatible = "allwinner,sun4i-a10-pll6-clk"; 103 reg = <0x01c20028 0x4>; 104 clocks = <&osc24M>; 105 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 106 }; 107 108 /* dummy is 200M */ 109 cpu: cpu@01c20054 { 110 #clock-cells = <0>; 111 compatible = "allwinner,sun4i-a10-cpu-clk"; 112 reg = <0x01c20054 0x4>; 113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 114 clock-output-names = "cpu"; 115 }; 116 117 axi: axi@01c20054 { 118 #clock-cells = <0>; 119 compatible = "allwinner,sun4i-a10-axi-clk"; 120 reg = <0x01c20054 0x4>; 121 clocks = <&cpu>; 122 clock-output-names = "axi"; 123 }; 124 125 axi_gates: clk@01c2005c { 126 #clock-cells = <1>; 127 compatible = "allwinner,sun4i-a10-axi-gates-clk"; 128 reg = <0x01c2005c 0x4>; 129 clocks = <&axi>; 130 clock-output-names = "axi_dram"; 131 }; 132 133 ahb: ahb@01c20054 { 134 #clock-cells = <0>; 135 compatible = "allwinner,sun4i-a10-ahb-clk"; 136 reg = <0x01c20054 0x4>; 137 clocks = <&axi>; 138 clock-output-names = "ahb"; 139 }; 140 141 ahb_gates: clk@01c20060 { 142 #clock-cells = <1>; 143 compatible = "allwinner,sun4i-a10-ahb-gates-clk"; 144 reg = <0x01c20060 0x8>; 145 clocks = <&ahb>; 146 clock-output-names = "ahb_usb0", "ahb_ehci0", 147 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", 148 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", 149 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", 150 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", 151 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", 152 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", 153 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", 154 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", 155 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", 156 "ahb_de_fe1", "ahb_mp", "ahb_mali400"; 157 }; 158 159 apb0: apb0@01c20054 { 160 #clock-cells = <0>; 161 compatible = "allwinner,sun4i-a10-apb0-clk"; 162 reg = <0x01c20054 0x4>; 163 clocks = <&ahb>; 164 clock-output-names = "apb0"; 165 }; 166 167 apb0_gates: clk@01c20068 { 168 #clock-cells = <1>; 169 compatible = "allwinner,sun4i-a10-apb0-gates-clk"; 170 reg = <0x01c20068 0x4>; 171 clocks = <&apb0>; 172 clock-output-names = "apb0_codec", "apb0_spdif", 173 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", 174 "apb0_ir1", "apb0_keypad"; 175 }; 176 177 apb1_mux: apb1_mux@01c20058 { 178 #clock-cells = <0>; 179 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 180 reg = <0x01c20058 0x4>; 181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 182 clock-output-names = "apb1_mux"; 183 }; 184 185 apb1: apb1@01c20058 { 186 #clock-cells = <0>; 187 compatible = "allwinner,sun4i-a10-apb1-clk"; 188 reg = <0x01c20058 0x4>; 189 clocks = <&apb1_mux>; 190 clock-output-names = "apb1"; 191 }; 192 193 apb1_gates: clk@01c2006c { 194 #clock-cells = <1>; 195 compatible = "allwinner,sun4i-a10-apb1-gates-clk"; 196 reg = <0x01c2006c 0x4>; 197 clocks = <&apb1>; 198 clock-output-names = "apb1_i2c0", "apb1_i2c1", 199 "apb1_i2c2", "apb1_can", "apb1_scr", 200 "apb1_ps20", "apb1_ps21", "apb1_uart0", 201 "apb1_uart1", "apb1_uart2", "apb1_uart3", 202 "apb1_uart4", "apb1_uart5", "apb1_uart6", 203 "apb1_uart7"; 204 }; 205 206 nand_clk: clk@01c20080 { 207 #clock-cells = <0>; 208 compatible = "allwinner,sun4i-a10-mod0-clk"; 209 reg = <0x01c20080 0x4>; 210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clock-output-names = "nand"; 212 }; 213 214 ms_clk: clk@01c20084 { 215 #clock-cells = <0>; 216 compatible = "allwinner,sun4i-a10-mod0-clk"; 217 reg = <0x01c20084 0x4>; 218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clock-output-names = "ms"; 220 }; 221 222 mmc0_clk: clk@01c20088 { 223 #clock-cells = <0>; 224 compatible = "allwinner,sun4i-a10-mod0-clk"; 225 reg = <0x01c20088 0x4>; 226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clock-output-names = "mmc0"; 228 }; 229 230 mmc1_clk: clk@01c2008c { 231 #clock-cells = <0>; 232 compatible = "allwinner,sun4i-a10-mod0-clk"; 233 reg = <0x01c2008c 0x4>; 234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clock-output-names = "mmc1"; 236 }; 237 238 mmc2_clk: clk@01c20090 { 239 #clock-cells = <0>; 240 compatible = "allwinner,sun4i-a10-mod0-clk"; 241 reg = <0x01c20090 0x4>; 242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clock-output-names = "mmc2"; 244 }; 245 246 mmc3_clk: clk@01c20094 { 247 #clock-cells = <0>; 248 compatible = "allwinner,sun4i-a10-mod0-clk"; 249 reg = <0x01c20094 0x4>; 250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clock-output-names = "mmc3"; 252 }; 253 254 ts_clk: clk@01c20098 { 255 #clock-cells = <0>; 256 compatible = "allwinner,sun4i-a10-mod0-clk"; 257 reg = <0x01c20098 0x4>; 258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clock-output-names = "ts"; 260 }; 261 262 ss_clk: clk@01c2009c { 263 #clock-cells = <0>; 264 compatible = "allwinner,sun4i-a10-mod0-clk"; 265 reg = <0x01c2009c 0x4>; 266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clock-output-names = "ss"; 268 }; 269 270 spi0_clk: clk@01c200a0 { 271 #clock-cells = <0>; 272 compatible = "allwinner,sun4i-a10-mod0-clk"; 273 reg = <0x01c200a0 0x4>; 274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clock-output-names = "spi0"; 276 }; 277 278 spi1_clk: clk@01c200a4 { 279 #clock-cells = <0>; 280 compatible = "allwinner,sun4i-a10-mod0-clk"; 281 reg = <0x01c200a4 0x4>; 282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 283 clock-output-names = "spi1"; 284 }; 285 286 spi2_clk: clk@01c200a8 { 287 #clock-cells = <0>; 288 compatible = "allwinner,sun4i-a10-mod0-clk"; 289 reg = <0x01c200a8 0x4>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 291 clock-output-names = "spi2"; 292 }; 293 294 pata_clk: clk@01c200ac { 295 #clock-cells = <0>; 296 compatible = "allwinner,sun4i-a10-mod0-clk"; 297 reg = <0x01c200ac 0x4>; 298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 299 clock-output-names = "pata"; 300 }; 301 302 ir0_clk: clk@01c200b0 { 303 #clock-cells = <0>; 304 compatible = "allwinner,sun4i-a10-mod0-clk"; 305 reg = <0x01c200b0 0x4>; 306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 307 clock-output-names = "ir0"; 308 }; 309 310 ir1_clk: clk@01c200b4 { 311 #clock-cells = <0>; 312 compatible = "allwinner,sun4i-a10-mod0-clk"; 313 reg = <0x01c200b4 0x4>; 314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 315 clock-output-names = "ir1"; 316 }; 317 318 usb_clk: clk@01c200cc { 319 #clock-cells = <1>; 320 #reset-cells = <1>; 321 compatible = "allwinner,sun4i-a10-usb-clk"; 322 reg = <0x01c200cc 0x4>; 323 clocks = <&pll6 1>; 324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; 325 }; 326 327 spi3_clk: clk@01c200d4 { 328 #clock-cells = <0>; 329 compatible = "allwinner,sun4i-a10-mod0-clk"; 330 reg = <0x01c200d4 0x4>; 331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 332 clock-output-names = "spi3"; 333 }; 334 }; 335 336 soc@01c00000 { 337 compatible = "simple-bus"; 338 #address-cells = <1>; 339 #size-cells = <1>; 340 ranges; 341 342 dma: dma-controller@01c02000 { 343 compatible = "allwinner,sun4i-a10-dma"; 344 reg = <0x01c02000 0x1000>; 345 interrupts = <27>; 346 clocks = <&ahb_gates 6>; 347 #dma-cells = <2>; 348 }; 349 350 spi0: spi@01c05000 { 351 compatible = "allwinner,sun4i-a10-spi"; 352 reg = <0x01c05000 0x1000>; 353 interrupts = <10>; 354 clocks = <&ahb_gates 20>, <&spi0_clk>; 355 clock-names = "ahb", "mod"; 356 dmas = <&dma 1 27>, <&dma 1 26>; 357 dma-names = "rx", "tx"; 358 status = "disabled"; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 }; 362 363 spi1: spi@01c06000 { 364 compatible = "allwinner,sun4i-a10-spi"; 365 reg = <0x01c06000 0x1000>; 366 interrupts = <11>; 367 clocks = <&ahb_gates 21>, <&spi1_clk>; 368 clock-names = "ahb", "mod"; 369 dmas = <&dma 1 9>, <&dma 1 8>; 370 dma-names = "rx", "tx"; 371 status = "disabled"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 }; 375 376 emac: ethernet@01c0b000 { 377 compatible = "allwinner,sun4i-a10-emac"; 378 reg = <0x01c0b000 0x1000>; 379 interrupts = <55>; 380 clocks = <&ahb_gates 17>; 381 status = "disabled"; 382 }; 383 384 mdio@01c0b080 { 385 compatible = "allwinner,sun4i-a10-mdio"; 386 reg = <0x01c0b080 0x14>; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 mmc0: mmc@01c0f000 { 393 compatible = "allwinner,sun4i-a10-mmc"; 394 reg = <0x01c0f000 0x1000>; 395 clocks = <&ahb_gates 8>, <&mmc0_clk>; 396 clock-names = "ahb", "mmc"; 397 interrupts = <32>; 398 status = "disabled"; 399 }; 400 401 mmc1: mmc@01c10000 { 402 compatible = "allwinner,sun4i-a10-mmc"; 403 reg = <0x01c10000 0x1000>; 404 clocks = <&ahb_gates 9>, <&mmc1_clk>; 405 clock-names = "ahb", "mmc"; 406 interrupts = <33>; 407 status = "disabled"; 408 }; 409 410 mmc2: mmc@01c11000 { 411 compatible = "allwinner,sun4i-a10-mmc"; 412 reg = <0x01c11000 0x1000>; 413 clocks = <&ahb_gates 10>, <&mmc2_clk>; 414 clock-names = "ahb", "mmc"; 415 interrupts = <34>; 416 status = "disabled"; 417 }; 418 419 mmc3: mmc@01c12000 { 420 compatible = "allwinner,sun4i-a10-mmc"; 421 reg = <0x01c12000 0x1000>; 422 clocks = <&ahb_gates 11>, <&mmc3_clk>; 423 clock-names = "ahb", "mmc"; 424 interrupts = <35>; 425 status = "disabled"; 426 }; 427 428 usbphy: phy@01c13400 { 429 #phy-cells = <1>; 430 compatible = "allwinner,sun4i-a10-usb-phy"; 431 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 432 reg-names = "phy_ctrl", "pmu1", "pmu2"; 433 clocks = <&usb_clk 8>; 434 clock-names = "usb_phy"; 435 resets = <&usb_clk 1>, <&usb_clk 2>; 436 reset-names = "usb1_reset", "usb2_reset"; 437 status = "disabled"; 438 }; 439 440 ehci0: usb@01c14000 { 441 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 442 reg = <0x01c14000 0x100>; 443 interrupts = <39>; 444 clocks = <&ahb_gates 1>; 445 phys = <&usbphy 1>; 446 phy-names = "usb"; 447 status = "disabled"; 448 }; 449 450 ohci0: usb@01c14400 { 451 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 452 reg = <0x01c14400 0x100>; 453 interrupts = <64>; 454 clocks = <&usb_clk 6>, <&ahb_gates 2>; 455 phys = <&usbphy 1>; 456 phy-names = "usb"; 457 status = "disabled"; 458 }; 459 460 spi2: spi@01c17000 { 461 compatible = "allwinner,sun4i-a10-spi"; 462 reg = <0x01c17000 0x1000>; 463 interrupts = <12>; 464 clocks = <&ahb_gates 22>, <&spi2_clk>; 465 clock-names = "ahb", "mod"; 466 dmas = <&dma 1 29>, <&dma 1 28>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 }; 472 473 ahci: sata@01c18000 { 474 compatible = "allwinner,sun4i-a10-ahci"; 475 reg = <0x01c18000 0x1000>; 476 interrupts = <56>; 477 clocks = <&pll6 0>, <&ahb_gates 25>; 478 status = "disabled"; 479 }; 480 481 ehci1: usb@01c1c000 { 482 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 483 reg = <0x01c1c000 0x100>; 484 interrupts = <40>; 485 clocks = <&ahb_gates 3>; 486 phys = <&usbphy 2>; 487 phy-names = "usb"; 488 status = "disabled"; 489 }; 490 491 ohci1: usb@01c1c400 { 492 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 493 reg = <0x01c1c400 0x100>; 494 interrupts = <65>; 495 clocks = <&usb_clk 7>, <&ahb_gates 4>; 496 phys = <&usbphy 2>; 497 phy-names = "usb"; 498 status = "disabled"; 499 }; 500 501 spi3: spi@01c1f000 { 502 compatible = "allwinner,sun4i-a10-spi"; 503 reg = <0x01c1f000 0x1000>; 504 interrupts = <50>; 505 clocks = <&ahb_gates 23>, <&spi3_clk>; 506 clock-names = "ahb", "mod"; 507 dmas = <&dma 1 31>, <&dma 1 30>; 508 dma-names = "rx", "tx"; 509 status = "disabled"; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 }; 513 514 intc: interrupt-controller@01c20400 { 515 compatible = "allwinner,sun4i-a10-ic"; 516 reg = <0x01c20400 0x400>; 517 interrupt-controller; 518 #interrupt-cells = <1>; 519 }; 520 521 pio: pinctrl@01c20800 { 522 compatible = "allwinner,sun4i-a10-pinctrl"; 523 reg = <0x01c20800 0x400>; 524 interrupts = <28>; 525 clocks = <&apb0_gates 5>; 526 gpio-controller; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 #size-cells = <0>; 530 #gpio-cells = <3>; 531 532 pwm0_pins_a: pwm0@0 { 533 allwinner,pins = "PB2"; 534 allwinner,function = "pwm"; 535 allwinner,drive = <0>; 536 allwinner,pull = <0>; 537 }; 538 539 pwm1_pins_a: pwm1@0 { 540 allwinner,pins = "PI3"; 541 allwinner,function = "pwm"; 542 allwinner,drive = <0>; 543 allwinner,pull = <0>; 544 }; 545 546 uart0_pins_a: uart0@0 { 547 allwinner,pins = "PB22", "PB23"; 548 allwinner,function = "uart0"; 549 allwinner,drive = <0>; 550 allwinner,pull = <0>; 551 }; 552 553 uart0_pins_b: uart0@1 { 554 allwinner,pins = "PF2", "PF4"; 555 allwinner,function = "uart0"; 556 allwinner,drive = <0>; 557 allwinner,pull = <0>; 558 }; 559 560 uart1_pins_a: uart1@0 { 561 allwinner,pins = "PA10", "PA11"; 562 allwinner,function = "uart1"; 563 allwinner,drive = <0>; 564 allwinner,pull = <0>; 565 }; 566 567 i2c0_pins_a: i2c0@0 { 568 allwinner,pins = "PB0", "PB1"; 569 allwinner,function = "i2c0"; 570 allwinner,drive = <0>; 571 allwinner,pull = <0>; 572 }; 573 574 i2c1_pins_a: i2c1@0 { 575 allwinner,pins = "PB18", "PB19"; 576 allwinner,function = "i2c1"; 577 allwinner,drive = <0>; 578 allwinner,pull = <0>; 579 }; 580 581 i2c2_pins_a: i2c2@0 { 582 allwinner,pins = "PB20", "PB21"; 583 allwinner,function = "i2c2"; 584 allwinner,drive = <0>; 585 allwinner,pull = <0>; 586 }; 587 588 emac_pins_a: emac0@0 { 589 allwinner,pins = "PA0", "PA1", "PA2", 590 "PA3", "PA4", "PA5", "PA6", 591 "PA7", "PA8", "PA9", "PA10", 592 "PA11", "PA12", "PA13", "PA14", 593 "PA15", "PA16"; 594 allwinner,function = "emac"; 595 allwinner,drive = <0>; 596 allwinner,pull = <0>; 597 }; 598 599 mmc0_pins_a: mmc0@0 { 600 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 601 allwinner,function = "mmc0"; 602 allwinner,drive = <2>; 603 allwinner,pull = <0>; 604 }; 605 606 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 607 allwinner,pins = "PH1"; 608 allwinner,function = "gpio_in"; 609 allwinner,drive = <0>; 610 allwinner,pull = <1>; 611 }; 612 613 ir0_pins_a: ir0@0 { 614 allwinner,pins = "PB3","PB4"; 615 allwinner,function = "ir0"; 616 allwinner,drive = <0>; 617 allwinner,pull = <0>; 618 }; 619 620 ir1_pins_a: ir1@0 { 621 allwinner,pins = "PB22","PB23"; 622 allwinner,function = "ir1"; 623 allwinner,drive = <0>; 624 allwinner,pull = <0>; 625 }; 626 }; 627 628 timer@01c20c00 { 629 compatible = "allwinner,sun4i-a10-timer"; 630 reg = <0x01c20c00 0x90>; 631 interrupts = <22>; 632 clocks = <&osc24M>; 633 }; 634 635 wdt: watchdog@01c20c90 { 636 compatible = "allwinner,sun4i-a10-wdt"; 637 reg = <0x01c20c90 0x10>; 638 }; 639 640 rtc: rtc@01c20d00 { 641 compatible = "allwinner,sun4i-a10-rtc"; 642 reg = <0x01c20d00 0x20>; 643 interrupts = <24>; 644 }; 645 646 pwm: pwm@01c20e00 { 647 compatible = "allwinner,sun4i-a10-pwm"; 648 reg = <0x01c20e00 0xc>; 649 clocks = <&osc24M>; 650 #pwm-cells = <3>; 651 status = "disabled"; 652 }; 653 654 ir0: ir@01c21800 { 655 compatible = "allwinner,sun4i-a10-ir"; 656 clocks = <&apb0_gates 6>, <&ir0_clk>; 657 clock-names = "apb", "ir"; 658 interrupts = <5>; 659 reg = <0x01c21800 0x40>; 660 status = "disabled"; 661 }; 662 663 ir1: ir@01c21c00 { 664 compatible = "allwinner,sun4i-a10-ir"; 665 clocks = <&apb0_gates 7>, <&ir1_clk>; 666 clock-names = "apb", "ir"; 667 interrupts = <6>; 668 reg = <0x01c21c00 0x40>; 669 status = "disabled"; 670 }; 671 672 sid: eeprom@01c23800 { 673 compatible = "allwinner,sun4i-a10-sid"; 674 reg = <0x01c23800 0x10>; 675 }; 676 677 rtp: rtp@01c25000 { 678 compatible = "allwinner,sun4i-a10-ts"; 679 reg = <0x01c25000 0x100>; 680 interrupts = <29>; 681 }; 682 683 uart0: serial@01c28000 { 684 compatible = "snps,dw-apb-uart"; 685 reg = <0x01c28000 0x400>; 686 interrupts = <1>; 687 reg-shift = <2>; 688 reg-io-width = <4>; 689 clocks = <&apb1_gates 16>; 690 status = "disabled"; 691 }; 692 693 uart1: serial@01c28400 { 694 compatible = "snps,dw-apb-uart"; 695 reg = <0x01c28400 0x400>; 696 interrupts = <2>; 697 reg-shift = <2>; 698 reg-io-width = <4>; 699 clocks = <&apb1_gates 17>; 700 status = "disabled"; 701 }; 702 703 uart2: serial@01c28800 { 704 compatible = "snps,dw-apb-uart"; 705 reg = <0x01c28800 0x400>; 706 interrupts = <3>; 707 reg-shift = <2>; 708 reg-io-width = <4>; 709 clocks = <&apb1_gates 18>; 710 status = "disabled"; 711 }; 712 713 uart3: serial@01c28c00 { 714 compatible = "snps,dw-apb-uart"; 715 reg = <0x01c28c00 0x400>; 716 interrupts = <4>; 717 reg-shift = <2>; 718 reg-io-width = <4>; 719 clocks = <&apb1_gates 19>; 720 status = "disabled"; 721 }; 722 723 uart4: serial@01c29000 { 724 compatible = "snps,dw-apb-uart"; 725 reg = <0x01c29000 0x400>; 726 interrupts = <17>; 727 reg-shift = <2>; 728 reg-io-width = <4>; 729 clocks = <&apb1_gates 20>; 730 status = "disabled"; 731 }; 732 733 uart5: serial@01c29400 { 734 compatible = "snps,dw-apb-uart"; 735 reg = <0x01c29400 0x400>; 736 interrupts = <18>; 737 reg-shift = <2>; 738 reg-io-width = <4>; 739 clocks = <&apb1_gates 21>; 740 status = "disabled"; 741 }; 742 743 uart6: serial@01c29800 { 744 compatible = "snps,dw-apb-uart"; 745 reg = <0x01c29800 0x400>; 746 interrupts = <19>; 747 reg-shift = <2>; 748 reg-io-width = <4>; 749 clocks = <&apb1_gates 22>; 750 status = "disabled"; 751 }; 752 753 uart7: serial@01c29c00 { 754 compatible = "snps,dw-apb-uart"; 755 reg = <0x01c29c00 0x400>; 756 interrupts = <20>; 757 reg-shift = <2>; 758 reg-io-width = <4>; 759 clocks = <&apb1_gates 23>; 760 status = "disabled"; 761 }; 762 763 i2c0: i2c@01c2ac00 { 764 compatible = "allwinner,sun4i-a10-i2c"; 765 reg = <0x01c2ac00 0x400>; 766 interrupts = <7>; 767 clocks = <&apb1_gates 0>; 768 status = "disabled"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 }; 772 773 i2c1: i2c@01c2b000 { 774 compatible = "allwinner,sun4i-a10-i2c"; 775 reg = <0x01c2b000 0x400>; 776 interrupts = <8>; 777 clocks = <&apb1_gates 1>; 778 status = "disabled"; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 }; 782 783 i2c2: i2c@01c2b400 { 784 compatible = "allwinner,sun4i-a10-i2c"; 785 reg = <0x01c2b400 0x400>; 786 interrupts = <9>; 787 clocks = <&apb1_gates 2>; 788 status = "disabled"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 }; 792 }; 793}; 794