1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public 22 * License along with this library; if not, write to the Free 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 * 26 * Or, alternatively, 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use, 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50/include/ "skeleton.dtsi" 51 52/ { 53 interrupt-parent = <&gic>; 54 55 aliases { 56 serial0 = &uart0; 57 serial1 = &uart1; 58 serial2 = &uart2; 59 serial3 = &uart3; 60 serial4 = &uart4; 61 serial5 = &uart5; 62 ethernet0 = &gmac; 63 }; 64 65 66 cpus { 67 enable-method = "allwinner,sun6i-a31"; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 }; 76 77 cpu@1 { 78 compatible = "arm,cortex-a7"; 79 device_type = "cpu"; 80 reg = <1>; 81 }; 82 83 cpu@2 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <2>; 87 }; 88 89 cpu@3 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <3>; 93 }; 94 }; 95 96 memory { 97 reg = <0x40000000 0x80000000>; 98 }; 99 100 pmu { 101 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 102 interrupts = <0 120 4>, 103 <0 121 4>, 104 <0 122 4>, 105 <0 123 4>; 106 }; 107 108 clocks { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges; 112 113 osc24M: osc24M { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <24000000>; 117 }; 118 119 osc32k: clk@0 { 120 #clock-cells = <0>; 121 compatible = "fixed-clock"; 122 clock-frequency = <32768>; 123 clock-output-names = "osc32k"; 124 }; 125 126 pll1: clk@01c20000 { 127 #clock-cells = <0>; 128 compatible = "allwinner,sun6i-a31-pll1-clk"; 129 reg = <0x01c20000 0x4>; 130 clocks = <&osc24M>; 131 clock-output-names = "pll1"; 132 }; 133 134 pll6: clk@01c20028 { 135 #clock-cells = <0>; 136 compatible = "allwinner,sun6i-a31-pll6-clk"; 137 reg = <0x01c20028 0x4>; 138 clocks = <&osc24M>; 139 clock-output-names = "pll6"; 140 }; 141 142 cpu: cpu@01c20050 { 143 #clock-cells = <0>; 144 compatible = "allwinner,sun4i-a10-cpu-clk"; 145 reg = <0x01c20050 0x4>; 146 147 /* 148 * PLL1 is listed twice here. 149 * While it looks suspicious, it's actually documented 150 * that way both in the datasheet and in the code from 151 * Allwinner. 152 */ 153 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 154 clock-output-names = "cpu"; 155 }; 156 157 axi: axi@01c20050 { 158 #clock-cells = <0>; 159 compatible = "allwinner,sun4i-a10-axi-clk"; 160 reg = <0x01c20050 0x4>; 161 clocks = <&cpu>; 162 clock-output-names = "axi"; 163 }; 164 165 ahb1_mux: ahb1_mux@01c20054 { 166 #clock-cells = <0>; 167 compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; 168 reg = <0x01c20054 0x4>; 169 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; 170 clock-output-names = "ahb1_mux"; 171 }; 172 173 ahb1: ahb1@01c20054 { 174 #clock-cells = <0>; 175 compatible = "allwinner,sun4i-a10-ahb-clk"; 176 reg = <0x01c20054 0x4>; 177 clocks = <&ahb1_mux>; 178 clock-output-names = "ahb1"; 179 }; 180 181 ahb1_gates: clk@01c20060 { 182 #clock-cells = <1>; 183 compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; 184 reg = <0x01c20060 0x8>; 185 clocks = <&ahb1>; 186 clock-output-names = "ahb1_mipidsi", "ahb1_ss", 187 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", 188 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", 189 "ahb1_nand0", "ahb1_sdram", 190 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", 191 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", 192 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", 193 "ahb1_ehci1", "ahb1_ohci0", 194 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", 195 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", 196 "ahb1_hdmi", "ahb1_de0", "ahb1_de1", 197 "ahb1_fe0", "ahb1_fe1", "ahb1_mp", 198 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", 199 "ahb1_drc0", "ahb1_drc1"; 200 }; 201 202 apb1: apb1@01c20054 { 203 #clock-cells = <0>; 204 compatible = "allwinner,sun4i-a10-apb0-clk"; 205 reg = <0x01c20054 0x4>; 206 clocks = <&ahb1>; 207 clock-output-names = "apb1"; 208 }; 209 210 apb1_gates: clk@01c20068 { 211 #clock-cells = <1>; 212 compatible = "allwinner,sun6i-a31-apb1-gates-clk"; 213 reg = <0x01c20068 0x4>; 214 clocks = <&apb1>; 215 clock-output-names = "apb1_codec", "apb1_digital_mic", 216 "apb1_pio", "apb1_daudio0", 217 "apb1_daudio1"; 218 }; 219 220 apb2_mux: apb2_mux@01c20058 { 221 #clock-cells = <0>; 222 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 223 reg = <0x01c20058 0x4>; 224 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 225 clock-output-names = "apb2_mux"; 226 }; 227 228 apb2: apb2@01c20058 { 229 #clock-cells = <0>; 230 compatible = "allwinner,sun6i-a31-apb2-div-clk"; 231 reg = <0x01c20058 0x4>; 232 clocks = <&apb2_mux>; 233 clock-output-names = "apb2"; 234 }; 235 236 apb2_gates: clk@01c2006c { 237 #clock-cells = <1>; 238 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 239 reg = <0x01c2006c 0x4>; 240 clocks = <&apb2>; 241 clock-output-names = "apb2_i2c0", "apb2_i2c1", 242 "apb2_i2c2", "apb2_i2c3", "apb2_uart0", 243 "apb2_uart1", "apb2_uart2", "apb2_uart3", 244 "apb2_uart4", "apb2_uart5"; 245 }; 246 247 mmc0_clk: clk@01c20088 { 248 #clock-cells = <0>; 249 compatible = "allwinner,sun4i-a10-mod0-clk"; 250 reg = <0x01c20088 0x4>; 251 clocks = <&osc24M>, <&pll6>; 252 clock-output-names = "mmc0"; 253 }; 254 255 mmc1_clk: clk@01c2008c { 256 #clock-cells = <0>; 257 compatible = "allwinner,sun4i-a10-mod0-clk"; 258 reg = <0x01c2008c 0x4>; 259 clocks = <&osc24M>, <&pll6>; 260 clock-output-names = "mmc1"; 261 }; 262 263 mmc2_clk: clk@01c20090 { 264 #clock-cells = <0>; 265 compatible = "allwinner,sun4i-a10-mod0-clk"; 266 reg = <0x01c20090 0x4>; 267 clocks = <&osc24M>, <&pll6>; 268 clock-output-names = "mmc2"; 269 }; 270 271 mmc3_clk: clk@01c20094 { 272 #clock-cells = <0>; 273 compatible = "allwinner,sun4i-a10-mod0-clk"; 274 reg = <0x01c20094 0x4>; 275 clocks = <&osc24M>, <&pll6>; 276 clock-output-names = "mmc3"; 277 }; 278 279 spi0_clk: clk@01c200a0 { 280 #clock-cells = <0>; 281 compatible = "allwinner,sun4i-a10-mod0-clk"; 282 reg = <0x01c200a0 0x4>; 283 clocks = <&osc24M>, <&pll6>; 284 clock-output-names = "spi0"; 285 }; 286 287 spi1_clk: clk@01c200a4 { 288 #clock-cells = <0>; 289 compatible = "allwinner,sun4i-a10-mod0-clk"; 290 reg = <0x01c200a4 0x4>; 291 clocks = <&osc24M>, <&pll6>; 292 clock-output-names = "spi1"; 293 }; 294 295 spi2_clk: clk@01c200a8 { 296 #clock-cells = <0>; 297 compatible = "allwinner,sun4i-a10-mod0-clk"; 298 reg = <0x01c200a8 0x4>; 299 clocks = <&osc24M>, <&pll6>; 300 clock-output-names = "spi2"; 301 }; 302 303 spi3_clk: clk@01c200ac { 304 #clock-cells = <0>; 305 compatible = "allwinner,sun4i-a10-mod0-clk"; 306 reg = <0x01c200ac 0x4>; 307 clocks = <&osc24M>, <&pll6>; 308 clock-output-names = "spi3"; 309 }; 310 311 usb_clk: clk@01c200cc { 312 #clock-cells = <1>; 313 #reset-cells = <1>; 314 compatible = "allwinner,sun6i-a31-usb-clk"; 315 reg = <0x01c200cc 0x4>; 316 clocks = <&osc24M>; 317 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", 318 "usb_ohci0", "usb_ohci1", 319 "usb_ohci2"; 320 }; 321 322 /* 323 * The following two are dummy clocks, placeholders used in the gmac_tx 324 * clock. The gmac driver will choose one parent depending on the PHY 325 * interface mode, using clk_set_rate auto-reparenting. 326 * The actual TX clock rate is not controlled by the gmac_tx clock. 327 */ 328 mii_phy_tx_clk: clk@1 { 329 #clock-cells = <0>; 330 compatible = "fixed-clock"; 331 clock-frequency = <25000000>; 332 clock-output-names = "mii_phy_tx"; 333 }; 334 335 gmac_int_tx_clk: clk@2 { 336 #clock-cells = <0>; 337 compatible = "fixed-clock"; 338 clock-frequency = <125000000>; 339 clock-output-names = "gmac_int_tx"; 340 }; 341 342 gmac_tx_clk: clk@01c200d0 { 343 #clock-cells = <0>; 344 compatible = "allwinner,sun7i-a20-gmac-clk"; 345 reg = <0x01c200d0 0x4>; 346 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 347 clock-output-names = "gmac_tx"; 348 }; 349 }; 350 351 soc@01c00000 { 352 compatible = "simple-bus"; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges; 356 357 dma: dma-controller@01c02000 { 358 compatible = "allwinner,sun6i-a31-dma"; 359 reg = <0x01c02000 0x1000>; 360 interrupts = <0 50 4>; 361 clocks = <&ahb1_gates 6>; 362 resets = <&ahb1_rst 6>; 363 #dma-cells = <1>; 364 365 /* DMA controller requires AHB1 clocked from PLL6 */ 366 assigned-clocks = <&ahb1_mux>; 367 assigned-clock-parents = <&pll6>; 368 }; 369 370 mmc0: mmc@01c0f000 { 371 compatible = "allwinner,sun5i-a13-mmc"; 372 reg = <0x01c0f000 0x1000>; 373 clocks = <&ahb1_gates 8>, <&mmc0_clk>; 374 clock-names = "ahb", "mmc"; 375 resets = <&ahb1_rst 8>; 376 reset-names = "ahb"; 377 interrupts = <0 60 4>; 378 status = "disabled"; 379 }; 380 381 mmc1: mmc@01c10000 { 382 compatible = "allwinner,sun5i-a13-mmc"; 383 reg = <0x01c10000 0x1000>; 384 clocks = <&ahb1_gates 9>, <&mmc1_clk>; 385 clock-names = "ahb", "mmc"; 386 resets = <&ahb1_rst 9>; 387 reset-names = "ahb"; 388 interrupts = <0 61 4>; 389 status = "disabled"; 390 }; 391 392 mmc2: mmc@01c11000 { 393 compatible = "allwinner,sun5i-a13-mmc"; 394 reg = <0x01c11000 0x1000>; 395 clocks = <&ahb1_gates 10>, <&mmc2_clk>; 396 clock-names = "ahb", "mmc"; 397 resets = <&ahb1_rst 10>; 398 reset-names = "ahb"; 399 interrupts = <0 62 4>; 400 status = "disabled"; 401 }; 402 403 mmc3: mmc@01c12000 { 404 compatible = "allwinner,sun5i-a13-mmc"; 405 reg = <0x01c12000 0x1000>; 406 clocks = <&ahb1_gates 11>, <&mmc3_clk>; 407 clock-names = "ahb", "mmc"; 408 resets = <&ahb1_rst 11>; 409 reset-names = "ahb"; 410 interrupts = <0 63 4>; 411 status = "disabled"; 412 }; 413 414 usbphy: phy@01c19400 { 415 compatible = "allwinner,sun6i-a31-usb-phy"; 416 reg = <0x01c19400 0x10>, 417 <0x01c1a800 0x4>, 418 <0x01c1b800 0x4>; 419 reg-names = "phy_ctrl", 420 "pmu1", 421 "pmu2"; 422 clocks = <&usb_clk 8>, 423 <&usb_clk 9>, 424 <&usb_clk 10>; 425 clock-names = "usb0_phy", 426 "usb1_phy", 427 "usb2_phy"; 428 resets = <&usb_clk 0>, 429 <&usb_clk 1>, 430 <&usb_clk 2>; 431 reset-names = "usb0_reset", 432 "usb1_reset", 433 "usb2_reset"; 434 status = "disabled"; 435 #phy-cells = <1>; 436 }; 437 438 ehci0: usb@01c1a000 { 439 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 440 reg = <0x01c1a000 0x100>; 441 interrupts = <0 72 4>; 442 clocks = <&ahb1_gates 26>; 443 resets = <&ahb1_rst 26>; 444 phys = <&usbphy 1>; 445 phy-names = "usb"; 446 status = "disabled"; 447 }; 448 449 ohci0: usb@01c1a400 { 450 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 451 reg = <0x01c1a400 0x100>; 452 interrupts = <0 73 4>; 453 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 454 resets = <&ahb1_rst 29>; 455 phys = <&usbphy 1>; 456 phy-names = "usb"; 457 status = "disabled"; 458 }; 459 460 ehci1: usb@01c1b000 { 461 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 462 reg = <0x01c1b000 0x100>; 463 interrupts = <0 74 4>; 464 clocks = <&ahb1_gates 27>; 465 resets = <&ahb1_rst 27>; 466 phys = <&usbphy 2>; 467 phy-names = "usb"; 468 status = "disabled"; 469 }; 470 471 ohci1: usb@01c1b400 { 472 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 473 reg = <0x01c1b400 0x100>; 474 interrupts = <0 75 4>; 475 clocks = <&ahb1_gates 30>, <&usb_clk 17>; 476 resets = <&ahb1_rst 30>; 477 phys = <&usbphy 2>; 478 phy-names = "usb"; 479 status = "disabled"; 480 }; 481 482 ohci2: usb@01c1c400 { 483 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 484 reg = <0x01c1c400 0x100>; 485 interrupts = <0 77 4>; 486 clocks = <&ahb1_gates 31>, <&usb_clk 18>; 487 resets = <&ahb1_rst 31>; 488 status = "disabled"; 489 }; 490 491 pio: pinctrl@01c20800 { 492 compatible = "allwinner,sun6i-a31-pinctrl"; 493 reg = <0x01c20800 0x400>; 494 interrupts = <0 11 4>, 495 <0 15 4>, 496 <0 16 4>, 497 <0 17 4>; 498 clocks = <&apb1_gates 5>; 499 gpio-controller; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 #size-cells = <0>; 503 #gpio-cells = <3>; 504 505 uart0_pins_a: uart0@0 { 506 allwinner,pins = "PH20", "PH21"; 507 allwinner,function = "uart0"; 508 allwinner,drive = <0>; 509 allwinner,pull = <0>; 510 }; 511 512 i2c0_pins_a: i2c0@0 { 513 allwinner,pins = "PH14", "PH15"; 514 allwinner,function = "i2c0"; 515 allwinner,drive = <0>; 516 allwinner,pull = <0>; 517 }; 518 519 i2c1_pins_a: i2c1@0 { 520 allwinner,pins = "PH16", "PH17"; 521 allwinner,function = "i2c1"; 522 allwinner,drive = <0>; 523 allwinner,pull = <0>; 524 }; 525 526 i2c2_pins_a: i2c2@0 { 527 allwinner,pins = "PH18", "PH19"; 528 allwinner,function = "i2c2"; 529 allwinner,drive = <0>; 530 allwinner,pull = <0>; 531 }; 532 533 mmc0_pins_a: mmc0@0 { 534 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 535 allwinner,function = "mmc0"; 536 allwinner,drive = <2>; 537 allwinner,pull = <0>; 538 }; 539 540 gmac_pins_mii_a: gmac_mii@0 { 541 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 542 "PA8", "PA9", "PA11", 543 "PA12", "PA13", "PA14", "PA19", 544 "PA20", "PA21", "PA22", "PA23", 545 "PA24", "PA26", "PA27"; 546 allwinner,function = "gmac"; 547 allwinner,drive = <0>; 548 allwinner,pull = <0>; 549 }; 550 551 gmac_pins_gmii_a: gmac_gmii@0 { 552 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 553 "PA4", "PA5", "PA6", "PA7", 554 "PA8", "PA9", "PA10", "PA11", 555 "PA12", "PA13", "PA14", "PA15", 556 "PA16", "PA17", "PA18", "PA19", 557 "PA20", "PA21", "PA22", "PA23", 558 "PA24", "PA25", "PA26", "PA27"; 559 allwinner,function = "gmac"; 560 /* 561 * data lines in GMII mode run at 125MHz and 562 * might need a higher signal drive strength 563 */ 564 allwinner,drive = <2>; 565 allwinner,pull = <0>; 566 }; 567 568 gmac_pins_rgmii_a: gmac_rgmii@0 { 569 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 570 "PA9", "PA10", "PA11", 571 "PA12", "PA13", "PA14", "PA19", 572 "PA20", "PA25", "PA26", "PA27"; 573 allwinner,function = "gmac"; 574 /* 575 * data lines in RGMII mode use DDR mode 576 * and need a higher signal drive strength 577 */ 578 allwinner,drive = <3>; 579 allwinner,pull = <0>; 580 }; 581 }; 582 583 ahb1_rst: reset@01c202c0 { 584 #reset-cells = <1>; 585 compatible = "allwinner,sun6i-a31-ahb1-reset"; 586 reg = <0x01c202c0 0xc>; 587 }; 588 589 apb1_rst: reset@01c202d0 { 590 #reset-cells = <1>; 591 compatible = "allwinner,sun6i-a31-clock-reset"; 592 reg = <0x01c202d0 0x4>; 593 }; 594 595 apb2_rst: reset@01c202d8 { 596 #reset-cells = <1>; 597 compatible = "allwinner,sun6i-a31-clock-reset"; 598 reg = <0x01c202d8 0x4>; 599 }; 600 601 timer@01c20c00 { 602 compatible = "allwinner,sun4i-a10-timer"; 603 reg = <0x01c20c00 0xa0>; 604 interrupts = <0 18 4>, 605 <0 19 4>, 606 <0 20 4>, 607 <0 21 4>, 608 <0 22 4>; 609 clocks = <&osc24M>; 610 }; 611 612 wdt1: watchdog@01c20ca0 { 613 compatible = "allwinner,sun6i-a31-wdt"; 614 reg = <0x01c20ca0 0x20>; 615 }; 616 617 uart0: serial@01c28000 { 618 compatible = "snps,dw-apb-uart"; 619 reg = <0x01c28000 0x400>; 620 interrupts = <0 0 4>; 621 reg-shift = <2>; 622 reg-io-width = <4>; 623 clocks = <&apb2_gates 16>; 624 resets = <&apb2_rst 16>; 625 dmas = <&dma 6>, <&dma 6>; 626 dma-names = "rx", "tx"; 627 status = "disabled"; 628 }; 629 630 uart1: serial@01c28400 { 631 compatible = "snps,dw-apb-uart"; 632 reg = <0x01c28400 0x400>; 633 interrupts = <0 1 4>; 634 reg-shift = <2>; 635 reg-io-width = <4>; 636 clocks = <&apb2_gates 17>; 637 resets = <&apb2_rst 17>; 638 dmas = <&dma 7>, <&dma 7>; 639 dma-names = "rx", "tx"; 640 status = "disabled"; 641 }; 642 643 uart2: serial@01c28800 { 644 compatible = "snps,dw-apb-uart"; 645 reg = <0x01c28800 0x400>; 646 interrupts = <0 2 4>; 647 reg-shift = <2>; 648 reg-io-width = <4>; 649 clocks = <&apb2_gates 18>; 650 resets = <&apb2_rst 18>; 651 dmas = <&dma 8>, <&dma 8>; 652 dma-names = "rx", "tx"; 653 status = "disabled"; 654 }; 655 656 uart3: serial@01c28c00 { 657 compatible = "snps,dw-apb-uart"; 658 reg = <0x01c28c00 0x400>; 659 interrupts = <0 3 4>; 660 reg-shift = <2>; 661 reg-io-width = <4>; 662 clocks = <&apb2_gates 19>; 663 resets = <&apb2_rst 19>; 664 dmas = <&dma 9>, <&dma 9>; 665 dma-names = "rx", "tx"; 666 status = "disabled"; 667 }; 668 669 uart4: serial@01c29000 { 670 compatible = "snps,dw-apb-uart"; 671 reg = <0x01c29000 0x400>; 672 interrupts = <0 4 4>; 673 reg-shift = <2>; 674 reg-io-width = <4>; 675 clocks = <&apb2_gates 20>; 676 resets = <&apb2_rst 20>; 677 dmas = <&dma 10>, <&dma 10>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 uart5: serial@01c29400 { 683 compatible = "snps,dw-apb-uart"; 684 reg = <0x01c29400 0x400>; 685 interrupts = <0 5 4>; 686 reg-shift = <2>; 687 reg-io-width = <4>; 688 clocks = <&apb2_gates 21>; 689 resets = <&apb2_rst 21>; 690 dmas = <&dma 22>, <&dma 22>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 i2c0: i2c@01c2ac00 { 696 compatible = "allwinner,sun6i-a31-i2c"; 697 reg = <0x01c2ac00 0x400>; 698 interrupts = <0 6 4>; 699 clocks = <&apb2_gates 0>; 700 resets = <&apb2_rst 0>; 701 status = "disabled"; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 }; 705 706 i2c1: i2c@01c2b000 { 707 compatible = "allwinner,sun6i-a31-i2c"; 708 reg = <0x01c2b000 0x400>; 709 interrupts = <0 7 4>; 710 clocks = <&apb2_gates 1>; 711 resets = <&apb2_rst 1>; 712 status = "disabled"; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 }; 716 717 i2c2: i2c@01c2b400 { 718 compatible = "allwinner,sun6i-a31-i2c"; 719 reg = <0x01c2b400 0x400>; 720 interrupts = <0 8 4>; 721 clocks = <&apb2_gates 2>; 722 resets = <&apb2_rst 2>; 723 status = "disabled"; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 }; 727 728 i2c3: i2c@01c2b800 { 729 compatible = "allwinner,sun6i-a31-i2c"; 730 reg = <0x01c2b800 0x400>; 731 interrupts = <0 9 4>; 732 clocks = <&apb2_gates 3>; 733 resets = <&apb2_rst 3>; 734 status = "disabled"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 }; 738 739 gmac: ethernet@01c30000 { 740 compatible = "allwinner,sun7i-a20-gmac"; 741 reg = <0x01c30000 0x1054>; 742 interrupts = <0 82 4>; 743 interrupt-names = "macirq"; 744 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; 745 clock-names = "stmmaceth", "allwinner_gmac_tx"; 746 resets = <&ahb1_rst 17>; 747 reset-names = "stmmaceth"; 748 snps,pbl = <2>; 749 snps,fixed-burst; 750 snps,force_sf_dma_mode; 751 status = "disabled"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 }; 755 756 timer@01c60000 { 757 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; 758 reg = <0x01c60000 0x1000>; 759 interrupts = <0 51 4>, 760 <0 52 4>, 761 <0 53 4>, 762 <0 54 4>; 763 clocks = <&ahb1_gates 19>; 764 resets = <&ahb1_rst 19>; 765 }; 766 767 spi0: spi@01c68000 { 768 compatible = "allwinner,sun6i-a31-spi"; 769 reg = <0x01c68000 0x1000>; 770 interrupts = <0 65 4>; 771 clocks = <&ahb1_gates 20>, <&spi0_clk>; 772 clock-names = "ahb", "mod"; 773 dmas = <&dma 23>, <&dma 23>; 774 dma-names = "rx", "tx"; 775 resets = <&ahb1_rst 20>; 776 status = "disabled"; 777 }; 778 779 spi1: spi@01c69000 { 780 compatible = "allwinner,sun6i-a31-spi"; 781 reg = <0x01c69000 0x1000>; 782 interrupts = <0 66 4>; 783 clocks = <&ahb1_gates 21>, <&spi1_clk>; 784 clock-names = "ahb", "mod"; 785 dmas = <&dma 24>, <&dma 24>; 786 dma-names = "rx", "tx"; 787 resets = <&ahb1_rst 21>; 788 status = "disabled"; 789 }; 790 791 spi2: spi@01c6a000 { 792 compatible = "allwinner,sun6i-a31-spi"; 793 reg = <0x01c6a000 0x1000>; 794 interrupts = <0 67 4>; 795 clocks = <&ahb1_gates 22>, <&spi2_clk>; 796 clock-names = "ahb", "mod"; 797 dmas = <&dma 25>, <&dma 25>; 798 dma-names = "rx", "tx"; 799 resets = <&ahb1_rst 22>; 800 status = "disabled"; 801 }; 802 803 spi3: spi@01c6b000 { 804 compatible = "allwinner,sun6i-a31-spi"; 805 reg = <0x01c6b000 0x1000>; 806 interrupts = <0 68 4>; 807 clocks = <&ahb1_gates 23>, <&spi3_clk>; 808 clock-names = "ahb", "mod"; 809 dmas = <&dma 26>, <&dma 26>; 810 dma-names = "rx", "tx"; 811 resets = <&ahb1_rst 23>; 812 status = "disabled"; 813 }; 814 815 gic: interrupt-controller@01c81000 { 816 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 817 reg = <0x01c81000 0x1000>, 818 <0x01c82000 0x1000>, 819 <0x01c84000 0x2000>, 820 <0x01c86000 0x2000>; 821 interrupt-controller; 822 #interrupt-cells = <3>; 823 interrupts = <1 9 0xf04>; 824 }; 825 826 rtc: rtc@01f00000 { 827 compatible = "allwinner,sun6i-a31-rtc"; 828 reg = <0x01f00000 0x54>; 829 interrupts = <0 40 4>, <0 41 4>; 830 }; 831 832 nmi_intc: interrupt-controller@01f00c0c { 833 compatible = "allwinner,sun6i-a31-sc-nmi"; 834 interrupt-controller; 835 #interrupt-cells = <2>; 836 reg = <0x01f00c0c 0x38>; 837 interrupts = <0 32 4>; 838 }; 839 840 prcm@01f01400 { 841 compatible = "allwinner,sun6i-a31-prcm"; 842 reg = <0x01f01400 0x200>; 843 844 ar100: ar100_clk { 845 compatible = "allwinner,sun6i-a31-ar100-clk"; 846 #clock-cells = <0>; 847 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 848 clock-output-names = "ar100"; 849 }; 850 851 ahb0: ahb0_clk { 852 compatible = "fixed-factor-clock"; 853 #clock-cells = <0>; 854 clock-div = <1>; 855 clock-mult = <1>; 856 clocks = <&ar100>; 857 clock-output-names = "ahb0"; 858 }; 859 860 apb0: apb0_clk { 861 compatible = "allwinner,sun6i-a31-apb0-clk"; 862 #clock-cells = <0>; 863 clocks = <&ahb0>; 864 clock-output-names = "apb0"; 865 }; 866 867 apb0_gates: apb0_gates_clk { 868 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 869 #clock-cells = <1>; 870 clocks = <&apb0>; 871 clock-output-names = "apb0_pio", "apb0_ir", 872 "apb0_timer", "apb0_p2wi", 873 "apb0_uart", "apb0_1wire", 874 "apb0_i2c"; 875 }; 876 877 apb0_rst: apb0_rst { 878 compatible = "allwinner,sun6i-a31-clock-reset"; 879 #reset-cells = <1>; 880 }; 881 }; 882 883 cpucfg@01f01c00 { 884 compatible = "allwinner,sun6i-a31-cpuconfig"; 885 reg = <0x01f01c00 0x300>; 886 }; 887 888 r_pio: pinctrl@01f02c00 { 889 compatible = "allwinner,sun6i-a31-r-pinctrl"; 890 reg = <0x01f02c00 0x400>; 891 interrupts = <0 45 4>, 892 <0 46 4>; 893 clocks = <&apb0_gates 0>; 894 resets = <&apb0_rst 0>; 895 gpio-controller; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 #size-cells = <0>; 899 #gpio-cells = <3>; 900 }; 901 }; 902}; 903