1#include <versatile-ab.dts> 2 3/ { 4 model = "ARM Versatile PB"; 5 compatible = "arm,versatile-pb"; 6 7 amba { 8 gpio2: gpio@101e6000 { 9 compatible = "arm,pl061", "arm,primecell"; 10 reg = <0x101e6000 0x1000>; 11 interrupts = <8>; 12 gpio-controller; 13 #gpio-cells = <2>; 14 interrupt-controller; 15 #interrupt-cells = <2>; 16 clocks = <&pclk>; 17 clock-names = "apb_pclk"; 18 }; 19 20 gpio3: gpio@101e7000 { 21 compatible = "arm,pl061", "arm,primecell"; 22 reg = <0x101e7000 0x1000>; 23 interrupts = <9>; 24 gpio-controller; 25 #gpio-cells = <2>; 26 interrupt-controller; 27 #interrupt-cells = <2>; 28 clocks = <&pclk>; 29 clock-names = "apb_pclk"; 30 }; 31 32 fpga { 33 uart@9000 { 34 compatible = "arm,pl011", "arm,primecell"; 35 reg = <0x9000 0x1000>; 36 interrupt-parent = <&sic>; 37 interrupts = <6>; 38 clocks = <&xtal24mhz>, <&pclk>; 39 clock-names = "uartclk", "apb_pclk"; 40 }; 41 sci@a000 { 42 compatible = "arm,primecell"; 43 reg = <0xa000 0x1000>; 44 interrupt-parent = <&sic>; 45 interrupts = <5>; 46 clocks = <&xtal24mhz>; 47 clock-names = "apb_pclk"; 48 }; 49 mmc@b000 { 50 compatible = "arm,pl180", "arm,primecell"; 51 reg = <0xb000 0x1000>; 52 interrupts-extended = <&vic 23 &sic 2>; 53 clocks = <&xtal24mhz>, <&pclk>; 54 clock-names = "mclk", "apb_pclk"; 55 }; 56 }; 57 }; 58}; 59