1/* 2 * linux/arch/arm/kernel/head-nommu.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (C) 2003-2006 Hyok S. Choi 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common kernel startup code (non-paged MM) 12 * 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/ptrace.h> 19#include <asm/asm-offsets.h> 20#include <asm/memory.h> 21#include <asm/cp15.h> 22#include <asm/thread_info.h> 23#include <asm/v7m.h> 24#include <asm/mpu.h> 25#include <asm/page.h> 26 27/* 28 * Kernel startup entry point. 29 * --------------------------- 30 * 31 * This is normally called from the decompressor code. The requirements 32 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 33 * r1 = machine nr. 34 * 35 * See linux/arch/arm/tools/mach-types for the complete list of machine 36 * numbers for r1. 37 * 38 */ 39 40 __HEAD 41 42#ifdef CONFIG_CPU_THUMBONLY 43 .thumb 44ENTRY(stext) 45#else 46 .arm 47ENTRY(stext) 48 49 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 50 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 51 THUMB( .thumb ) @ switch to Thumb now. 52 THUMB(1: ) 53#endif 54 55 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 56 @ and irqs disabled 57#if defined(CONFIG_CPU_CP15) 58 mrc p15, 0, r9, c0, c0 @ get processor id 59#elif defined(CONFIG_CPU_V7M) 60 ldr r9, =BASEADDR_V7M_SCB 61 ldr r9, [r9, V7M_SCB_CPUID] 62#else 63 ldr r9, =CONFIG_PROCESSOR_ID 64#endif 65 bl __lookup_processor_type @ r5=procinfo r9=cpuid 66 movs r10, r5 @ invalid processor (r5=0)? 67 beq __error_p @ yes, error 'p' 68 69#ifdef CONFIG_ARM_MPU 70 /* Calculate the size of a region covering just the kernel */ 71 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET 72 ldr r6, =(_end) @ Cover whole kernel 73 sub r6, r6, r5 @ Minimum size of region to map 74 clz r6, r6 @ Region size must be 2^N... 75 rsb r6, r6, #31 @ ...so round up region size 76 lsl r6, r6, #MPU_RSR_SZ @ Put size in right field 77 orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit 78 bl __setup_mpu 79#endif 80 adr lr, BSYM(1f) @ return (PIC) address 81 ARM( add pc, r10, #PROCINFO_INITFUNC ) 82 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 83 THUMB( ret r12 ) 841: bl __after_proc_init 85 b __mmap_switched 86ENDPROC(stext) 87 88#ifdef CONFIG_SMP 89 .text 90ENTRY(secondary_startup) 91 /* 92 * Common entry point for secondary CPUs. 93 * 94 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 95 * the processor type - there is no need to check the machine type 96 * as it has already been validated by the primary processor. 97 */ 98 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 99#ifndef CONFIG_CPU_CP15 100 ldr r9, =CONFIG_PROCESSOR_ID 101#else 102 mrc p15, 0, r9, c0, c0 @ get processor id 103#endif 104 bl __lookup_processor_type @ r5=procinfo r9=cpuid 105 movs r10, r5 @ invalid processor? 106 beq __error_p @ yes, error 'p' 107 108 ldr r7, __secondary_data 109 110#ifdef CONFIG_ARM_MPU 111 /* Use MPU region info supplied by __cpu_up */ 112 ldr r6, [r7] @ get secondary_data.mpu_szr 113 bl __setup_mpu @ Initialize the MPU 114#endif 115 116 adr lr, BSYM(1f) @ return (PIC) address 117 ARM( add pc, r10, #PROCINFO_INITFUNC ) 118 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 119 THUMB( ret r12 ) 1201: bl __after_proc_init 121 ldr sp, [r7, #12] @ set up the stack pointer 122 mov fp, #0 123 b secondary_start_kernel 124ENDPROC(secondary_startup) 125 126 .type __secondary_data, %object 127__secondary_data: 128 .long secondary_data 129#endif /* CONFIG_SMP */ 130 131/* 132 * Set the Control Register and Read the process ID. 133 */ 134__after_proc_init: 135#ifdef CONFIG_CPU_CP15 136 /* 137 * CP15 system control register value returned in r0 from 138 * the CPU init function. 139 */ 140#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 141 orr r0, r0, #CR_A 142#else 143 bic r0, r0, #CR_A 144#endif 145#ifdef CONFIG_CPU_DCACHE_DISABLE 146 bic r0, r0, #CR_C 147#endif 148#ifdef CONFIG_CPU_BPREDICT_DISABLE 149 bic r0, r0, #CR_Z 150#endif 151#ifdef CONFIG_CPU_ICACHE_DISABLE 152 bic r0, r0, #CR_I 153#endif 154#ifdef CONFIG_CPU_HIGH_VECTOR 155 orr r0, r0, #CR_V 156#else 157 bic r0, r0, #CR_V 158#endif 159 mcr p15, 0, r0, c1, c0, 0 @ write control reg 160#endif /* CONFIG_CPU_CP15 */ 161 ret lr 162ENDPROC(__after_proc_init) 163 .ltorg 164 165#ifdef CONFIG_ARM_MPU 166 167 168/* Set which MPU region should be programmed */ 169.macro set_region_nr tmp, rgnr 170 mov \tmp, \rgnr @ Use static region numbers 171 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 172.endm 173 174/* Setup a single MPU region, either D or I side (D-side for unified) */ 175.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE 176 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 177 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 178 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 179.endm 180 181/* 182 * Setup the MPU and initial MPU Regions. We create the following regions: 183 * Region 0: Use this for probing the MPU details, so leave disabled. 184 * Region 1: Background region - covers the whole of RAM as strongly ordered 185 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6 186 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page 187 * 188 * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION 189*/ 190 191ENTRY(__setup_mpu) 192 193 /* Probe for v7 PMSA compliance */ 194 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 195 and r0, r0, #(MMFR0_PMSA) @ PMSA field 196 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 197 bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA 198 199 /* Determine whether the D/I-side memory map is unified. We set the 200 * flags here and continue to use them for the rest of this function */ 201 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 202 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 203 beq __error_p @ Fail: ARM_MPU and no MPU 204 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 205 206 /* Setup second region first to free up r6 */ 207 set_region_nr r0, #MPU_RAM_REGION 208 isb 209 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 210 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 211 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL) 212 213 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled 214 beq 1f @ Memory-map not unified 215 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled 2161: isb 217 218 /* First/background region */ 219 set_region_nr r0, #MPU_BG_REGION 220 isb 221 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */ 222 mov r0, #0 @ BG region starts at 0x0 223 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA) 224 mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled 225 226 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled 227 beq 2f @ Memory-map not unified 228 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled 2292: isb 230 231 /* Vectors region */ 232 set_region_nr r0, #MPU_VECTORS_REGION 233 isb 234 /* Shared, inaccessible to PL0, rw PL1 */ 235 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE 236 ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL) 237 /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */ 238 mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN) 239 240 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled 241 beq 3f @ Memory-map not unified 242 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled 2433: isb 244 245 /* Enable the MPU */ 246 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR 247 bic r0, r0, #CR_BR @ Disable the 'default mem-map' 248 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) 249 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU 250 isb 251 ret lr 252ENDPROC(__setup_mpu) 253#endif 254#include "head-common.S" 255