1 /* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14 #include <linux/linkage.h> 15 #include <linux/init.h> 16 17 #include <asm/assembler.h> 18 #include <asm/cp15.h> 19 #include <asm/domain.h> 20 #include <asm/ptrace.h> 21 #include <asm/asm-offsets.h> 22 #include <asm/memory.h> 23 #include <asm/thread_info.h> 24 #include <asm/pgtable.h> 25 26 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) 27 #include CONFIG_DEBUG_LL_INCLUDE 28 #endif 29 30 /* 31 * swapper_pg_dir is the virtual address of the initial page table. 32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 34 * the least significant 16 bits to be 0x8000, but we could probably 35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 36 */ 37 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000 40 #endif 41 42 #ifdef CONFIG_ARM_LPAE 43 /* LPAE requires an additional page for the PGD */ 44 #define PG_DIR_SIZE 0x5000 45 #define PMD_ORDER 3 46 #else 47 #define PG_DIR_SIZE 0x4000 48 #define PMD_ORDER 2 49 #endif 50 51 .globl swapper_pg_dir 52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 53 54 .macro pgtbl, rd, phys 55 add \rd, \phys, #TEXT_OFFSET 56 sub \rd, \rd, #PG_DIR_SIZE 57 .endm 58 59 /* 60 * Kernel startup entry point. 61 * --------------------------- 62 * 63 * This is normally called from the decompressor code. The requirements 64 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 65 * r1 = machine nr, r2 = atags or dtb pointer. 66 * 67 * This code is mostly position independent, so if you link the kernel at 68 * 0xc0008000, you call this at __pa(0xc0008000). 69 * 70 * See linux/arch/arm/tools/mach-types for the complete list of machine 71 * numbers for r1. 72 * 73 * We're trying to keep crap to a minimum; DO NOT add any machine specific 74 * crap here - that's what the boot loader (or in extreme, well justified 75 * circumstances, zImage) is for. 76 */ 77 .arm 78 79 __HEAD 80 ENTRY(stext) 81 ARM_BE8(setend be ) @ ensure we are in BE8 mode 82 83 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 84 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 85 THUMB( .thumb ) @ switch to Thumb now. 86 THUMB(1: ) 87 88 #ifdef CONFIG_ARM_VIRT_EXT 89 bl __hyp_stub_install 90 #endif 91 @ ensure svc mode and all interrupts masked 92 safe_svcmode_maskall r9 93 94 mrc p15, 0, r9, c0, c0 @ get processor id 95 bl __lookup_processor_type @ r5=procinfo r9=cpuid 96 movs r10, r5 @ invalid processor (r5=0)? 97 THUMB( it eq ) @ force fixup-able long branch encoding 98 beq __error_p @ yes, error 'p' 99 100 #ifdef CONFIG_ARM_LPAE 101 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 102 and r3, r3, #0xf @ extract VMSA support 103 cmp r3, #5 @ long-descriptor translation table format? 104 THUMB( it lo ) @ force fixup-able long branch encoding 105 blo __error_lpae @ only classic page table format 106 #endif 107 108 #ifndef CONFIG_XIP_KERNEL 109 adr r3, 2f 110 ldmia r3, {r4, r8} 111 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 112 add r8, r8, r4 @ PHYS_OFFSET 113 #else 114 ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case 115 #endif 116 117 /* 118 * r1 = machine no, r2 = atags or dtb, 119 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 120 */ 121 bl __vet_atags 122 #ifdef CONFIG_SMP_ON_UP 123 bl __fixup_smp 124 #endif 125 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT 126 bl __fixup_pv_table 127 #endif 128 bl __create_page_tables 129 130 /* 131 * The following calls CPU specific code in a position independent 132 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 133 * xxx_proc_info structure selected by __lookup_processor_type 134 * above. 135 * 136 * The processor init function will be called with: 137 * r1 - machine type 138 * r2 - boot data (atags/dt) pointer 139 * r4 - translation table base (low word) 140 * r5 - translation table base (high word, if LPAE) 141 * r8 - translation table base 1 (pfn if LPAE) 142 * r9 - cpuid 143 * r13 - virtual address for __enable_mmu -> __turn_mmu_on 144 * 145 * On return, the CPU will be ready for the MMU to be turned on, 146 * r0 will hold the CPU control register value, r1, r2, r4, and 147 * r9 will be preserved. r5 will also be preserved if LPAE. 148 */ 149 ldr r13, =__mmap_switched @ address to jump to after 150 @ mmu has been enabled 151 adr lr, BSYM(1f) @ return (PIC) address 152 #ifdef CONFIG_ARM_LPAE 153 mov r5, #0 @ high TTBR0 154 mov r8, r4, lsr #12 @ TTBR1 is swapper_pg_dir pfn 155 #else 156 mov r8, r4 @ set TTBR1 to swapper_pg_dir 157 #endif 158 ldr r12, [r10, #PROCINFO_INITFUNC] 159 add r12, r12, r10 160 ret r12 161 1: b __enable_mmu 162 ENDPROC(stext) 163 .ltorg 164 #ifndef CONFIG_XIP_KERNEL 165 2: .long . 166 .long PAGE_OFFSET 167 #endif 168 169 /* 170 * Setup the initial page tables. We only setup the barest 171 * amount which are required to get the kernel running, which 172 * generally means mapping in the kernel code. 173 * 174 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 175 * 176 * Returns: 177 * r0, r3, r5-r7 corrupted 178 * r4 = physical page table address 179 */ 180 __create_page_tables: 181 pgtbl r4, r8 @ page table address 182 183 /* 184 * Clear the swapper page table 185 */ 186 mov r0, r4 187 mov r3, #0 188 add r6, r0, #PG_DIR_SIZE 189 1: str r3, [r0], #4 190 str r3, [r0], #4 191 str r3, [r0], #4 192 str r3, [r0], #4 193 teq r0, r6 194 bne 1b 195 196 #ifdef CONFIG_ARM_LPAE 197 /* 198 * Build the PGD table (first level) to point to the PMD table. A PGD 199 * entry is 64-bit wide. 200 */ 201 mov r0, r4 202 add r3, r4, #0x1000 @ first PMD table address 203 orr r3, r3, #3 @ PGD block type 204 mov r6, #4 @ PTRS_PER_PGD 205 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 206 1: 207 #ifdef CONFIG_CPU_ENDIAN_BE8 208 str r7, [r0], #4 @ set top PGD entry bits 209 str r3, [r0], #4 @ set bottom PGD entry bits 210 #else 211 str r3, [r0], #4 @ set bottom PGD entry bits 212 str r7, [r0], #4 @ set top PGD entry bits 213 #endif 214 add r3, r3, #0x1000 @ next PMD table 215 subs r6, r6, #1 216 bne 1b 217 218 add r4, r4, #0x1000 @ point to the PMD tables 219 #ifdef CONFIG_CPU_ENDIAN_BE8 220 add r4, r4, #4 @ we only write the bottom word 221 #endif 222 #endif 223 224 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 225 226 /* 227 * Create identity mapping to cater for __enable_mmu. 228 * This identity mapping will be removed by paging_init(). 229 */ 230 adr r0, __turn_mmu_on_loc 231 ldmia r0, {r3, r5, r6} 232 sub r0, r0, r3 @ virt->phys offset 233 add r5, r5, r0 @ phys __turn_mmu_on 234 add r6, r6, r0 @ phys __turn_mmu_on_end 235 mov r5, r5, lsr #SECTION_SHIFT 236 mov r6, r6, lsr #SECTION_SHIFT 237 238 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 239 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 240 cmp r5, r6 241 addlo r5, r5, #1 @ next section 242 blo 1b 243 244 /* 245 * Map our RAM from the start to the end of the kernel .bss section. 246 */ 247 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 248 ldr r6, =(_end - 1) 249 orr r3, r8, r7 250 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 251 1: str r3, [r0], #1 << PMD_ORDER 252 add r3, r3, #1 << SECTION_SHIFT 253 cmp r0, r6 254 bls 1b 255 256 #ifdef CONFIG_XIP_KERNEL 257 /* 258 * Map the kernel image separately as it is not located in RAM. 259 */ 260 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 261 mov r3, pc 262 mov r3, r3, lsr #SECTION_SHIFT 263 orr r3, r7, r3, lsl #SECTION_SHIFT 264 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 265 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 266 ldr r6, =(_edata_loc - 1) 267 add r0, r0, #1 << PMD_ORDER 268 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 269 1: cmp r0, r6 270 add r3, r3, #1 << SECTION_SHIFT 271 strls r3, [r0], #1 << PMD_ORDER 272 bls 1b 273 #endif 274 275 /* 276 * Then map boot params address in r2 if specified. 277 * We map 2 sections in case the ATAGs/DTB crosses a section boundary. 278 */ 279 mov r0, r2, lsr #SECTION_SHIFT 280 movs r0, r0, lsl #SECTION_SHIFT 281 subne r3, r0, r8 282 addne r3, r3, #PAGE_OFFSET 283 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 284 orrne r6, r7, r0 285 strne r6, [r3], #1 << PMD_ORDER 286 addne r6, r6, #1 << SECTION_SHIFT 287 strne r6, [r3] 288 289 #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 290 sub r4, r4, #4 @ Fixup page table pointer 291 @ for 64-bit descriptors 292 #endif 293 294 #ifdef CONFIG_DEBUG_LL 295 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 296 /* 297 * Map in IO space for serial debugging. 298 * This allows debug messages to be output 299 * via a serial console before paging_init. 300 */ 301 addruart r7, r3, r0 302 303 mov r3, r3, lsr #SECTION_SHIFT 304 mov r3, r3, lsl #PMD_ORDER 305 306 add r0, r4, r3 307 mov r3, r7, lsr #SECTION_SHIFT 308 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 309 orr r3, r7, r3, lsl #SECTION_SHIFT 310 #ifdef CONFIG_ARM_LPAE 311 mov r7, #1 << (54 - 32) @ XN 312 #ifdef CONFIG_CPU_ENDIAN_BE8 313 str r7, [r0], #4 314 str r3, [r0], #4 315 #else 316 str r3, [r0], #4 317 str r7, [r0], #4 318 #endif 319 #else 320 orr r3, r3, #PMD_SECT_XN 321 str r3, [r0], #4 322 #endif 323 324 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 325 /* we don't need any serial debugging mappings */ 326 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 327 #endif 328 329 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 330 /* 331 * If we're using the NetWinder or CATS, we also need to map 332 * in the 16550-type serial port for the debug messages 333 */ 334 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 335 orr r3, r7, #0x7c000000 336 str r3, [r0] 337 #endif 338 #ifdef CONFIG_ARCH_RPC 339 /* 340 * Map in screen at 0x02000000 & SCREEN2_BASE 341 * Similar reasons here - for debug. This is 342 * only for Acorn RiscPC architectures. 343 */ 344 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 345 orr r3, r7, #0x02000000 346 str r3, [r0] 347 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 348 str r3, [r0] 349 #endif 350 #endif 351 #ifdef CONFIG_ARM_LPAE 352 sub r4, r4, #0x1000 @ point to the PGD table 353 #endif 354 ret lr 355 ENDPROC(__create_page_tables) 356 .ltorg 357 .align 358 __turn_mmu_on_loc: 359 .long . 360 .long __turn_mmu_on 361 .long __turn_mmu_on_end 362 363 #if defined(CONFIG_SMP) 364 .text 365 ENTRY(secondary_startup) 366 /* 367 * Common entry point for secondary CPUs. 368 * 369 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 370 * the processor type - there is no need to check the machine type 371 * as it has already been validated by the primary processor. 372 */ 373 374 ARM_BE8(setend be) @ ensure we are in BE8 mode 375 376 #ifdef CONFIG_ARM_VIRT_EXT 377 bl __hyp_stub_install_secondary 378 #endif 379 safe_svcmode_maskall r9 380 381 mrc p15, 0, r9, c0, c0 @ get processor id 382 bl __lookup_processor_type 383 movs r10, r5 @ invalid processor? 384 moveq r0, #'p' @ yes, error 'p' 385 THUMB( it eq ) @ force fixup-able long branch encoding 386 beq __error_p 387 388 /* 389 * Use the page tables supplied from __cpu_up. 390 */ 391 adr r4, __secondary_data 392 ldmia r4, {r5, r7, r12} @ address to jump to after 393 sub lr, r4, r5 @ mmu has been enabled 394 add r3, r7, lr 395 ldrd r4, [r3, #0] @ get secondary_data.pgdir 396 ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE: 397 ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps 398 ARM_BE8(eor r4, r4, r5) @ without using a temp reg. 399 ldr r8, [r3, #8] @ get secondary_data.swapper_pg_dir 400 adr lr, BSYM(__enable_mmu) @ return address 401 mov r13, r12 @ __secondary_switched address 402 ldr r12, [r10, #PROCINFO_INITFUNC] 403 add r12, r12, r10 @ initialise processor 404 @ (return control reg) 405 ret r12 406 ENDPROC(secondary_startup) 407 408 /* 409 * r6 = &secondary_data 410 */ 411 ENTRY(__secondary_switched) 412 ldr sp, [r7, #12] @ get secondary_data.stack 413 mov fp, #0 414 b secondary_start_kernel 415 ENDPROC(__secondary_switched) 416 417 .align 418 419 .type __secondary_data, %object 420 __secondary_data: 421 .long . 422 .long secondary_data 423 .long __secondary_switched 424 #endif /* defined(CONFIG_SMP) */ 425 426 427 428 /* 429 * Setup common bits before finally enabling the MMU. Essentially 430 * this is just loading the page table pointer and domain access 431 * registers. All these registers need to be preserved by the 432 * processor setup function (or set in the case of r0) 433 * 434 * r0 = cp#15 control register 435 * r1 = machine ID 436 * r2 = atags or dtb pointer 437 * r4 = TTBR pointer (low word) 438 * r5 = TTBR pointer (high word if LPAE) 439 * r9 = processor ID 440 * r13 = *virtual* address to jump to upon completion 441 */ 442 __enable_mmu: 443 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 444 orr r0, r0, #CR_A 445 #else 446 bic r0, r0, #CR_A 447 #endif 448 #ifdef CONFIG_CPU_DCACHE_DISABLE 449 bic r0, r0, #CR_C 450 #endif 451 #ifdef CONFIG_CPU_BPREDICT_DISABLE 452 bic r0, r0, #CR_Z 453 #endif 454 #ifdef CONFIG_CPU_ICACHE_DISABLE 455 bic r0, r0, #CR_I 456 #endif 457 #ifdef CONFIG_ARM_LPAE 458 mcrr p15, 0, r4, r5, c2 @ load TTBR0 459 #else 460 mov r5, #DACR_INIT 461 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 462 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 463 #endif 464 b __turn_mmu_on 465 ENDPROC(__enable_mmu) 466 467 /* 468 * Enable the MMU. This completely changes the structure of the visible 469 * memory space. You will not be able to trace execution through this. 470 * If you have an enquiry about this, *please* check the linux-arm-kernel 471 * mailing list archives BEFORE sending another post to the list. 472 * 473 * r0 = cp#15 control register 474 * r1 = machine ID 475 * r2 = atags or dtb pointer 476 * r9 = processor ID 477 * r13 = *virtual* address to jump to upon completion 478 * 479 * other registers depend on the function called upon completion 480 */ 481 .align 5 482 .pushsection .idmap.text, "ax" 483 ENTRY(__turn_mmu_on) 484 mov r0, r0 485 instr_sync 486 mcr p15, 0, r0, c1, c0, 0 @ write control reg 487 mrc p15, 0, r3, c0, c0, 0 @ read id reg 488 instr_sync 489 mov r3, r3 490 mov r3, r13 491 ret r3 492 __turn_mmu_on_end: 493 ENDPROC(__turn_mmu_on) 494 .popsection 495 496 497 #ifdef CONFIG_SMP_ON_UP 498 __HEAD 499 __fixup_smp: 500 and r3, r9, #0x000f0000 @ architecture version 501 teq r3, #0x000f0000 @ CPU ID supported? 502 bne __fixup_smp_on_up @ no, assume UP 503 504 bic r3, r9, #0x00ff0000 505 bic r3, r3, #0x0000000f @ mask 0xff00fff0 506 mov r4, #0x41000000 507 orr r4, r4, #0x0000b000 508 orr r4, r4, #0x00000020 @ val 0x4100b020 509 teq r3, r4 @ ARM 11MPCore? 510 reteq lr @ yes, assume SMP 511 512 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 513 and r0, r0, #0xc0000000 @ multiprocessing extensions and 514 teq r0, #0x80000000 @ not part of a uniprocessor system? 515 bne __fixup_smp_on_up @ no, assume UP 516 517 @ Core indicates it is SMP. Check for Aegis SOC where a single 518 @ Cortex-A9 CPU is present but SMP operations fault. 519 mov r4, #0x41000000 520 orr r4, r4, #0x0000c000 521 orr r4, r4, #0x00000090 522 teq r3, r4 @ Check for ARM Cortex-A9 523 retne lr @ Not ARM Cortex-A9, 524 525 @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the 526 @ below address check will need to be #ifdef'd or equivalent 527 @ for the Aegis platform. 528 mrc p15, 4, r0, c15, c0 @ get SCU base address 529 teq r0, #0x0 @ '0' on actual UP A9 hardware 530 beq __fixup_smp_on_up @ So its an A9 UP 531 ldr r0, [r0, #4] @ read SCU Config 532 ARM_BE8(rev r0, r0) @ byteswap if big endian 533 and r0, r0, #0x3 @ number of CPUs 534 teq r0, #0x0 @ is 1? 535 retne lr 536 537 __fixup_smp_on_up: 538 adr r0, 1f 539 ldmia r0, {r3 - r5} 540 sub r3, r0, r3 541 add r4, r4, r3 542 add r5, r5, r3 543 b __do_fixup_smp_on_up 544 ENDPROC(__fixup_smp) 545 546 .align 547 1: .word . 548 .word __smpalt_begin 549 .word __smpalt_end 550 551 .pushsection .data 552 .globl smp_on_up 553 smp_on_up: 554 ALT_SMP(.long 1) 555 ALT_UP(.long 0) 556 .popsection 557 #endif 558 559 .text 560 __do_fixup_smp_on_up: 561 cmp r4, r5 562 reths lr 563 ldmia r4!, {r0, r6} 564 ARM( str r6, [r0, r3] ) 565 THUMB( add r0, r0, r3 ) 566 #ifdef __ARMEB__ 567 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 568 #endif 569 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 570 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 571 THUMB( strh r6, [r0] ) 572 b __do_fixup_smp_on_up 573 ENDPROC(__do_fixup_smp_on_up) 574 575 ENTRY(fixup_smp) 576 stmfd sp!, {r4 - r6, lr} 577 mov r4, r0 578 add r5, r0, r1 579 mov r3, #0 580 bl __do_fixup_smp_on_up 581 ldmfd sp!, {r4 - r6, pc} 582 ENDPROC(fixup_smp) 583 584 #ifdef __ARMEB__ 585 #define LOW_OFFSET 0x4 586 #define HIGH_OFFSET 0x0 587 #else 588 #define LOW_OFFSET 0x0 589 #define HIGH_OFFSET 0x4 590 #endif 591 592 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT 593 594 /* __fixup_pv_table - patch the stub instructions with the delta between 595 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 596 * can be expressed by an immediate shifter operand. The stub instruction 597 * has a form of '(add|sub) rd, rn, #imm'. 598 */ 599 __HEAD 600 __fixup_pv_table: 601 adr r0, 1f 602 ldmia r0, {r3-r7} 603 mvn ip, #0 604 subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 605 add r4, r4, r3 @ adjust table start address 606 add r5, r5, r3 @ adjust table end address 607 add r6, r6, r3 @ adjust __pv_phys_pfn_offset address 608 add r7, r7, r3 @ adjust __pv_offset address 609 mov r0, r8, lsr #12 @ convert to PFN 610 str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset 611 strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits 612 mov r6, r3, lsr #24 @ constant for add/sub instructions 613 teq r3, r6, lsl #24 @ must be 16MiB aligned 614 THUMB( it ne @ cross section branch ) 615 bne __error 616 str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits 617 b __fixup_a_pv_table 618 ENDPROC(__fixup_pv_table) 619 620 .align 621 1: .long . 622 .long __pv_table_begin 623 .long __pv_table_end 624 2: .long __pv_phys_pfn_offset 625 .long __pv_offset 626 627 .text 628 __fixup_a_pv_table: 629 adr r0, 3f 630 ldr r6, [r0] 631 add r6, r6, r3 632 ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word 633 ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word 634 mov r6, r6, lsr #24 635 cmn r0, #1 636 #ifdef CONFIG_THUMB2_KERNEL 637 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction 638 lsls r6, #24 639 beq 2f 640 clz r7, r6 641 lsr r6, #24 642 lsl r6, r7 643 bic r6, #0x0080 644 lsrs r7, #1 645 orrcs r6, #0x0080 646 orr r6, r6, r7, lsl #12 647 orr r6, #0x4000 648 b 2f 649 1: add r7, r3 650 ldrh ip, [r7, #2] 651 ARM_BE8(rev16 ip, ip) 652 tst ip, #0x4000 653 and ip, #0x8f00 654 orrne ip, r6 @ mask in offset bits 31-24 655 orreq ip, r0 @ mask in offset bits 7-0 656 ARM_BE8(rev16 ip, ip) 657 strh ip, [r7, #2] 658 bne 2f 659 ldrh ip, [r7] 660 ARM_BE8(rev16 ip, ip) 661 bic ip, #0x20 662 orr ip, ip, r0, lsr #16 663 ARM_BE8(rev16 ip, ip) 664 strh ip, [r7] 665 2: cmp r4, r5 666 ldrcc r7, [r4], #4 @ use branch for delay slot 667 bcc 1b 668 bx lr 669 #else 670 #ifdef CONFIG_CPU_ENDIAN_BE8 671 moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction 672 #else 673 moveq r0, #0x400000 @ set bit 22, mov to mvn instruction 674 #endif 675 b 2f 676 1: ldr ip, [r7, r3] 677 #ifdef CONFIG_CPU_ENDIAN_BE8 678 @ in BE8, we load data in BE, but instructions still in LE 679 bic ip, ip, #0xff000000 680 tst ip, #0x000f0000 @ check the rotation field 681 orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 682 biceq ip, ip, #0x00004000 @ clear bit 22 683 orreq ip, ip, r0 @ mask in offset bits 7-0 684 #else 685 bic ip, ip, #0x000000ff 686 tst ip, #0xf00 @ check the rotation field 687 orrne ip, ip, r6 @ mask in offset bits 31-24 688 biceq ip, ip, #0x400000 @ clear bit 22 689 orreq ip, ip, r0 @ mask in offset bits 7-0 690 #endif 691 str ip, [r7, r3] 692 2: cmp r4, r5 693 ldrcc r7, [r4], #4 @ use branch for delay slot 694 bcc 1b 695 ret lr 696 #endif 697 ENDPROC(__fixup_a_pv_table) 698 699 .align 700 3: .long __pv_offset 701 702 ENTRY(fixup_pv_table) 703 stmfd sp!, {r4 - r7, lr} 704 mov r3, #0 @ no offset 705 mov r4, r0 @ r0 = table start 706 add r5, r0, r1 @ r1 = table size 707 bl __fixup_a_pv_table 708 ldmfd sp!, {r4 - r7, pc} 709 ENDPROC(fixup_pv_table) 710 711 .data 712 .globl __pv_phys_pfn_offset 713 .type __pv_phys_pfn_offset, %object 714 __pv_phys_pfn_offset: 715 .word 0 716 .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset 717 718 .globl __pv_offset 719 .type __pv_offset, %object 720 __pv_offset: 721 .quad 0 722 .size __pv_offset, . -__pv_offset 723 #endif 724 725 #include "head-common.S" 726