1 /* 2 * SoC specific header file for the AT91SAM9N12 3 * 4 * Copyright (C) 2012 Atmel Corporation 5 * 6 * Common definitions, based on AT91SAM9N12 SoC datasheet 7 * 8 * Licensed under GPLv2 or later 9 */ 10 11 #ifndef _AT91SAM9N12_H_ 12 #define _AT91SAM9N12_H_ 13 14 /* 15 * Peripheral identifiers/interrupts. 16 */ 17 #define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ 18 #define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ 19 #define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */ 20 #define AT91SAM9N12_ID_USART0 5 /* USART 0 */ 21 #define AT91SAM9N12_ID_USART1 6 /* USART 1 */ 22 #define AT91SAM9N12_ID_USART2 7 /* USART 2 */ 23 #define AT91SAM9N12_ID_USART3 8 /* USART 3 */ 24 #define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ 25 #define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ 26 #define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */ 27 #define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ 28 #define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ 29 #define AT91SAM9N12_ID_UART0 15 /* UART 0 */ 30 #define AT91SAM9N12_ID_UART1 16 /* UART 1 */ 31 #define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 32 #define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ 33 #define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ 34 #define AT91SAM9N12_ID_DMA 20 /* DMA Controller */ 35 #define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */ 36 #define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */ 37 #define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ 38 #define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */ 39 #define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ 40 #define AT91SAM9N12_ID_TRNG 30 /* TRNG */ 41 #define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ 42 43 /* 44 * User Peripheral physical base addresses. 45 */ 46 #define AT91SAM9N12_BASE_USART0 0xf801c000 47 #define AT91SAM9N12_BASE_USART1 0xf8020000 48 #define AT91SAM9N12_BASE_USART2 0xf8024000 49 #define AT91SAM9N12_BASE_USART3 0xf8028000 50 51 /* 52 * System Peripherals 53 */ 54 #define AT91SAM9N12_BASE_RTC 0xfffffeb0 55 56 /* 57 * Internal Memory. 58 */ 59 #define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 60 #define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ 61 62 #define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ 63 #define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ 64 65 #endif 66