1 /*
2 * arch/arm/mach-at91/include/mach/uncompress.h
3 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #ifndef __ASM_ARCH_UNCOMPRESS_H
23 #define __ASM_ARCH_UNCOMPRESS_H
24
25 #include <linux/io.h>
26 #include <linux/atmel_serial.h>
27 #include <mach/hardware.h>
28
29 #include <mach/at91_dbgu.h>
30 #include <mach/cpu.h>
31
32 void __iomem *at91_uart;
33
34 #if !defined(CONFIG_ARCH_AT91X40)
35 static const u32 uarts_rm9200[] = {
36 AT91_BASE_DBGU0,
37 AT91RM9200_BASE_US0,
38 AT91RM9200_BASE_US1,
39 AT91RM9200_BASE_US2,
40 AT91RM9200_BASE_US3,
41 0,
42 };
43
44 static const u32 uarts_sam9260[] = {
45 AT91_BASE_DBGU0,
46 AT91SAM9260_BASE_US0,
47 AT91SAM9260_BASE_US1,
48 AT91SAM9260_BASE_US2,
49 AT91SAM9260_BASE_US3,
50 AT91SAM9260_BASE_US4,
51 AT91SAM9260_BASE_US5,
52 0,
53 };
54
55 static const u32 uarts_sam9261[] = {
56 AT91_BASE_DBGU0,
57 AT91SAM9261_BASE_US0,
58 AT91SAM9261_BASE_US1,
59 AT91SAM9261_BASE_US2,
60 0,
61 };
62
63 static const u32 uarts_sam9263[] = {
64 AT91_BASE_DBGU1,
65 AT91SAM9263_BASE_US0,
66 AT91SAM9263_BASE_US1,
67 AT91SAM9263_BASE_US2,
68 0,
69 };
70
71 static const u32 uarts_sam9g45[] = {
72 AT91_BASE_DBGU1,
73 AT91SAM9G45_BASE_US0,
74 AT91SAM9G45_BASE_US1,
75 AT91SAM9G45_BASE_US2,
76 AT91SAM9G45_BASE_US3,
77 0,
78 };
79
80 static const u32 uarts_sam9rl[] = {
81 AT91_BASE_DBGU0,
82 AT91SAM9RL_BASE_US0,
83 AT91SAM9RL_BASE_US1,
84 AT91SAM9RL_BASE_US2,
85 AT91SAM9RL_BASE_US3,
86 0,
87 };
88
89 static const u32 uarts_sam9x5[] = {
90 AT91_BASE_DBGU0,
91 AT91SAM9X5_BASE_USART0,
92 AT91SAM9X5_BASE_USART1,
93 AT91SAM9X5_BASE_USART2,
94 0,
95 };
96
97 static const u32 uarts_sama5d3[] = {
98 AT91_BASE_DBGU1,
99 SAMA5D3_BASE_USART0,
100 SAMA5D3_BASE_USART1,
101 SAMA5D3_BASE_USART2,
102 SAMA5D3_BASE_USART3,
103 0,
104 };
105
106 static const u32 uarts_sama5d4[] = {
107 AT91_BASE_DBGU2,
108 SAMA5D4_BASE_USART3,
109 0,
110 };
111
decomp_soc_detect(void __iomem * dbgu_base)112 static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
113 {
114 u32 cidr, socid;
115
116 cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
117 socid = cidr & ~AT91_CIDR_VERSION;
118
119 switch (socid) {
120 case ARCH_ID_AT91RM9200:
121 return uarts_rm9200;
122
123 case ARCH_ID_AT91SAM9G20:
124 case ARCH_ID_AT91SAM9260:
125 return uarts_sam9260;
126
127 case ARCH_ID_AT91SAM9261:
128 return uarts_sam9261;
129
130 case ARCH_ID_AT91SAM9263:
131 return uarts_sam9263;
132
133 case ARCH_ID_AT91SAM9G45:
134 return uarts_sam9g45;
135
136 case ARCH_ID_AT91SAM9RL64:
137 return uarts_sam9rl;
138
139 case ARCH_ID_AT91SAM9N12:
140 case ARCH_ID_AT91SAM9X5:
141 return uarts_sam9x5;
142
143 case ARCH_ID_SAMA5:
144 cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
145 if (cidr & ARCH_EXID_SAMA5D3)
146 return uarts_sama5d3;
147 else if (cidr & ARCH_EXID_SAMA5D4)
148 return uarts_sama5d4;
149
150 break;
151 }
152
153 /* at91sam9g10 */
154 if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
155 return uarts_sam9261;
156 }
157 /* at91sam9xe */
158 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
159 return uarts_sam9260;
160 }
161
162 return NULL;
163 }
164
arch_decomp_setup(void)165 static inline void arch_decomp_setup(void)
166 {
167 int i = 0;
168 const u32* usarts;
169
170 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
171 if (!usarts)
172 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
173 if (!usarts)
174 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
175 if (!usarts) {
176 at91_uart = NULL;
177 return;
178 }
179
180 do {
181 /* physical address */
182 at91_uart = (void __iomem *)usarts[i];
183
184 if (__raw_readl(at91_uart + ATMEL_US_BRGR))
185 return;
186 i++;
187 } while (usarts[i]);
188
189 at91_uart = NULL;
190 }
191 #else
arch_decomp_setup(void)192 static inline void arch_decomp_setup(void)
193 {
194 at91_uart = NULL;
195 }
196 #endif
197
198 /*
199 * The following code assumes the serial port has already been
200 * initialized by the bootloader. If you didn't setup a port in
201 * your bootloader then nothing will appear (which might be desired).
202 *
203 * This does not append a newline
204 */
putc(int c)205 static void putc(int c)
206 {
207 if (!at91_uart)
208 return;
209
210 while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
211 barrier();
212 __raw_writel(c, at91_uart + ATMEL_US_THR);
213 }
214
flush(void)215 static inline void flush(void)
216 {
217 if (!at91_uart)
218 return;
219
220 /* wait for transmission to complete */
221 while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
222 barrier();
223 }
224
225 #endif
226