1 /*
2 * PCI-E support for CNS3xxx
3 *
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/bug.h>
17 #include <linux/pci.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/ptrace.h>
22 #include <asm/mach/map.h>
23 #include "cns3xxx.h"
24 #include "core.h"
25
26 struct cns3xxx_pcie {
27 void __iomem *host_regs; /* PCI config registers for host bridge */
28 void __iomem *cfg0_regs; /* PCI Type 0 config registers */
29 void __iomem *cfg1_regs; /* PCI Type 1 config registers */
30 unsigned int irqs[2];
31 struct resource res_io;
32 struct resource res_mem;
33 struct hw_pci hw_pci;
34
35 bool linked;
36 };
37
38 static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
39
sysdata_to_cnspci(void * sysdata)40 static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
41 {
42 struct pci_sys_data *root = sysdata;
43
44 return &cns3xxx_pcie[root->domain];
45 }
46
pdev_to_cnspci(const struct pci_dev * dev)47 static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
48 {
49 return sysdata_to_cnspci(dev->sysdata);
50 }
51
pbus_to_cnspci(struct pci_bus * bus)52 static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
53 {
54 return sysdata_to_cnspci(bus->sysdata);
55 }
56
cns3xxx_pci_cfg_base(struct pci_bus * bus,unsigned int devfn,int where)57 static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
58 unsigned int devfn, int where)
59 {
60 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
61 int busno = bus->number;
62 int slot = PCI_SLOT(devfn);
63 void __iomem *base;
64
65 /* If there is no link, just show the CNS PCI bridge. */
66 if (!cnspci->linked && busno > 0)
67 return NULL;
68
69 /*
70 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
71 * we still want to access it. For this to work, we must place
72 * the first device on the same bus as the CNS PCI bridge.
73 */
74 if (busno == 0) { /* internal PCIe bus, host bridge device */
75 if (devfn == 0) /* device# and function# are ignored by hw */
76 base = cnspci->host_regs;
77 else
78 return NULL; /* no such device */
79
80 } else if (busno == 1) { /* directly connected PCIe device */
81 if (slot == 0) /* device# is ignored by hw */
82 base = cnspci->cfg0_regs;
83 else
84 return NULL; /* no such device */
85 } else /* remote PCI bus */
86 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
87
88 return base + (where & 0xffc) + (devfn << 12);
89 }
90
cns3xxx_pci_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)91 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
92 int where, int size, u32 *val)
93 {
94 u32 v;
95 void __iomem *base;
96 u32 mask = (0x1ull << (size * 8)) - 1;
97 int shift = (where % 4) * 8;
98
99 base = cns3xxx_pci_cfg_base(bus, devfn, where);
100 if (!base) {
101 *val = 0xffffffff;
102 return PCIBIOS_SUCCESSFUL;
103 }
104
105 v = __raw_readl(base);
106
107 if (bus->number == 0 && devfn == 0 &&
108 (where & 0xffc) == PCI_CLASS_REVISION) {
109 /*
110 * RC's class is 0xb, but Linux PCI driver needs 0x604
111 * for a PCIe bridge. So we must fixup the class code
112 * to 0x604 here.
113 */
114 v &= 0xff;
115 v |= 0x604 << 16;
116 }
117
118 *val = (v >> shift) & mask;
119
120 return PCIBIOS_SUCCESSFUL;
121 }
122
cns3xxx_pci_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)123 static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 val)
125 {
126 u32 v;
127 void __iomem *base;
128 u32 mask = (0x1ull << (size * 8)) - 1;
129 int shift = (where % 4) * 8;
130
131 base = cns3xxx_pci_cfg_base(bus, devfn, where);
132 if (!base)
133 return PCIBIOS_SUCCESSFUL;
134
135 v = __raw_readl(base);
136
137 v &= ~(mask << shift);
138 v |= (val & mask) << shift;
139
140 __raw_writel(v, base);
141
142 return PCIBIOS_SUCCESSFUL;
143 }
144
cns3xxx_pci_setup(int nr,struct pci_sys_data * sys)145 static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
146 {
147 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
148 struct resource *res_io = &cnspci->res_io;
149 struct resource *res_mem = &cnspci->res_mem;
150
151 BUG_ON(request_resource(&iomem_resource, res_io) ||
152 request_resource(&iomem_resource, res_mem));
153
154 pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
155 pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
156
157 return 1;
158 }
159
160 static struct pci_ops cns3xxx_pcie_ops = {
161 .read = cns3xxx_pci_read_config,
162 .write = cns3xxx_pci_write_config,
163 };
164
cns3xxx_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)165 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
166 {
167 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
168 int irq = cnspci->irqs[!!dev->bus->number];
169
170 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
171 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
172 PCI_FUNC(dev->devfn), slot, pin, irq);
173
174 return irq;
175 }
176
177 static struct cns3xxx_pcie cns3xxx_pcie[] = {
178 [0] = {
179 .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
180 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
181 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
182 .res_io = {
183 .name = "PCIe0 I/O space",
184 .start = CNS3XXX_PCIE0_IO_BASE,
185 .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
186 .flags = IORESOURCE_IO,
187 },
188 .res_mem = {
189 .name = "PCIe0 non-prefetchable",
190 .start = CNS3XXX_PCIE0_MEM_BASE,
191 .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
192 .flags = IORESOURCE_MEM,
193 },
194 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
195 .hw_pci = {
196 .domain = 0,
197 .nr_controllers = 1,
198 .ops = &cns3xxx_pcie_ops,
199 .setup = cns3xxx_pci_setup,
200 .map_irq = cns3xxx_pcie_map_irq,
201 },
202 },
203 [1] = {
204 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
205 .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
206 .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
207 .res_io = {
208 .name = "PCIe1 I/O space",
209 .start = CNS3XXX_PCIE1_IO_BASE,
210 .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
211 .flags = IORESOURCE_IO,
212 },
213 .res_mem = {
214 .name = "PCIe1 non-prefetchable",
215 .start = CNS3XXX_PCIE1_MEM_BASE,
216 .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
217 .flags = IORESOURCE_MEM,
218 },
219 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
220 .hw_pci = {
221 .domain = 1,
222 .nr_controllers = 1,
223 .ops = &cns3xxx_pcie_ops,
224 .setup = cns3xxx_pci_setup,
225 .map_irq = cns3xxx_pcie_map_irq,
226 },
227 },
228 };
229
cns3xxx_pcie_check_link(struct cns3xxx_pcie * cnspci)230 static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
231 {
232 int port = cnspci->hw_pci.domain;
233 u32 reg;
234 unsigned long time;
235
236 reg = __raw_readl(MISC_PCIE_CTRL(port));
237 /*
238 * Enable Application Request to 1, it will exit L1 automatically,
239 * but when chip back, it will use another clock, still can use 0x1.
240 */
241 reg |= 0x3;
242 __raw_writel(reg, MISC_PCIE_CTRL(port));
243
244 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
245 pr_info("PCIe: Port[%d] Check data link layer...", port);
246
247 time = jiffies;
248 while (1) {
249 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
250 if (reg & 0x1) {
251 pr_info("Link up.\n");
252 cnspci->linked = 1;
253 break;
254 } else if (time_after(jiffies, time + 50)) {
255 pr_info("Device not found.\n");
256 break;
257 }
258 }
259 }
260
cns3xxx_pcie_hw_init(struct cns3xxx_pcie * cnspci)261 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
262 {
263 int port = cnspci->hw_pci.domain;
264 struct pci_sys_data sd = {
265 .domain = port,
266 };
267 struct pci_bus bus = {
268 .number = 0,
269 .ops = &cns3xxx_pcie_ops,
270 .sysdata = &sd,
271 };
272 u16 mem_base = cnspci->res_mem.start >> 16;
273 u16 mem_limit = cnspci->res_mem.end >> 16;
274 u16 io_base = cnspci->res_io.start >> 16;
275 u16 io_limit = cnspci->res_io.end >> 16;
276 u32 devfn = 0;
277 u8 tmp8;
278 u16 pos;
279 u16 dc;
280
281 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
282 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
283 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
284
285 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
286 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
287 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
288
289 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
290 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
291 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
292 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
293
294 if (!cnspci->linked)
295 return;
296
297 /* Set Device Max_Read_Request_Size to 128 byte */
298 bus.number = 1; /* directly connected PCIe device */
299 devfn = PCI_DEVFN(0, 0);
300 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
301 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
302 if (dc & PCI_EXP_DEVCTL_READRQ) {
303 dc &= ~PCI_EXP_DEVCTL_READRQ;
304 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
305 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
306 if (dc & PCI_EXP_DEVCTL_READRQ)
307 pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
308 else
309 pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
310 }
311 /* Disable PCIe0 Interrupt Mask INTA to INTD */
312 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
313 }
314
cns3xxx_pcie_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)315 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
316 struct pt_regs *regs)
317 {
318 if (fsr & (1 << 10))
319 regs->ARM_pc += 4;
320 return 0;
321 }
322
cns3xxx_pcie_init_late(void)323 void __init cns3xxx_pcie_init_late(void)
324 {
325 int i;
326
327 pcibios_min_io = 0;
328 pcibios_min_mem = 0;
329
330 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
331 "imprecise external abort");
332
333 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
334 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
335 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
336 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
337 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
338 pci_common_init(&cns3xxx_pcie[i].hw_pci);
339 }
340
341 pci_assign_unassigned_resources();
342 }
343