1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include "common.h"
19 #include "hardware.h"
20
21 #define REG_SET 0x4
22 #define REG_CLR 0x8
23
24 #define ANADIG_REG_2P5 0x130
25 #define ANADIG_REG_CORE 0x140
26 #define ANADIG_ANA_MISC0 0x150
27 #define ANADIG_USB1_CHRG_DETECT 0x1b0
28 #define ANADIG_USB2_CHRG_DETECT 0x210
29 #define ANADIG_DIGPROG 0x260
30 #define ANADIG_DIGPROG_IMX6SL 0x280
31
32 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
33 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
34 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
35 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
36 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
37
38 static struct regmap *anatop;
39
imx_anatop_enable_weak2p5(bool enable)40 static void imx_anatop_enable_weak2p5(bool enable)
41 {
42 u32 reg, val;
43
44 regmap_read(anatop, ANADIG_ANA_MISC0, &val);
45
46 /* can only be enabled when stop_mode_config is clear. */
47 reg = ANADIG_REG_2P5;
48 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
49 REG_SET : REG_CLR;
50 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
51 }
52
imx_anatop_enable_fet_odrive(bool enable)53 static void imx_anatop_enable_fet_odrive(bool enable)
54 {
55 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
56 BM_ANADIG_REG_CORE_FET_ODRIVE);
57 }
58
imx_anatop_pre_suspend(void)59 void imx_anatop_pre_suspend(void)
60 {
61 imx_anatop_enable_weak2p5(true);
62 imx_anatop_enable_fet_odrive(true);
63 }
64
imx_anatop_post_resume(void)65 void imx_anatop_post_resume(void)
66 {
67 imx_anatop_enable_fet_odrive(false);
68 imx_anatop_enable_weak2p5(false);
69 }
70
imx_anatop_usb_chrg_detect_disable(void)71 static void imx_anatop_usb_chrg_detect_disable(void)
72 {
73 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
74 BM_ANADIG_USB_CHRG_DETECT_EN_B
75 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
76 regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
77 BM_ANADIG_USB_CHRG_DETECT_EN_B |
78 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
79 }
80
imx_init_revision_from_anatop(void)81 void __init imx_init_revision_from_anatop(void)
82 {
83 struct device_node *np;
84 void __iomem *anatop_base;
85 unsigned int revision;
86 u32 digprog;
87 u16 offset = ANADIG_DIGPROG;
88
89 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
90 anatop_base = of_iomap(np, 0);
91 WARN_ON(!anatop_base);
92 if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
93 offset = ANADIG_DIGPROG_IMX6SL;
94 digprog = readl_relaxed(anatop_base + offset);
95 iounmap(anatop_base);
96
97 switch (digprog & 0xff) {
98 case 0:
99 revision = IMX_CHIP_REVISION_1_0;
100 break;
101 case 1:
102 revision = IMX_CHIP_REVISION_1_1;
103 break;
104 case 2:
105 revision = IMX_CHIP_REVISION_1_2;
106 break;
107 case 3:
108 revision = IMX_CHIP_REVISION_1_3;
109 break;
110 case 4:
111 revision = IMX_CHIP_REVISION_1_4;
112 break;
113 case 5:
114 /*
115 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
116 * as 'D' in Part Number last character.
117 */
118 revision = IMX_CHIP_REVISION_1_5;
119 break;
120 default:
121 revision = IMX_CHIP_REVISION_UNKNOWN;
122 }
123
124 mxc_set_cpu_type(digprog >> 16 & 0xff);
125 imx_set_soc_revision(revision);
126 }
127
imx_anatop_init(void)128 void __init imx_anatop_init(void)
129 {
130 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
131 if (IS_ERR(anatop)) {
132 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
133 return;
134 }
135
136 imx_anatop_usb_chrg_detect_disable();
137 }
138