1 /*
2 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation.
16 */
17
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
21 #include <linux/io.h>
22 #include <linux/err.h>
23 #include <linux/of.h>
24
25 #include "clk.h"
26 #include "common.h"
27 #include "crmregs-imx3.h"
28 #include "hardware.h"
29 #include "mx31.h"
30
31 static const char *mcu_main_sel[] = { "spll", "mpll", };
32 static const char *per_sel[] = { "per_div", "ipg", };
33 static const char *csi_sel[] = { "upll", "spll", };
34 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
35
36 enum mx31_clks {
37 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
38 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
39 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
40 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
41 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
42 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
43 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
44 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
45 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
46 };
47
48 static struct clk *clk[clk_max];
49 static struct clk_onecell_data clk_data;
50
mx31_clocks_init(unsigned long fref)51 int __init mx31_clocks_init(unsigned long fref)
52 {
53 void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
54 struct device_node *np;
55
56 clk[dummy] = imx_clk_fixed("dummy", 0);
57 clk[ckih] = imx_clk_fixed("ckih", fref);
58 clk[ckil] = imx_clk_fixed("ckil", 32768);
59 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
60 clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
61 clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
62 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
65 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
66 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
67 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
68 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
69 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
70 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
71 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
72 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
73 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
74 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
75 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
76 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
77 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
78 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
79 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
80 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
81 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
82 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
83 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
84 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
85 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
86 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
87 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
88 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
89 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
90 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
91 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
92 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
93 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
94 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
95 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
96 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
97 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
98 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
99 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
100 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
101 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
102 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
103 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
104 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
105 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
106 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
107 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
108 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
109 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
110 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
111 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
112 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
113 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
114 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
115
116 imx_check_clocks(clk, ARRAY_SIZE(clk));
117
118 np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
119
120 if (np) {
121 clk_data.clks = clk;
122 clk_data.clk_num = ARRAY_SIZE(clk);
123 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
124 }
125
126 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
127 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
128 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
129 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
130 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
131 clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
132 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
133 clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc");
134 clk_register_clkdev(clk[epit1_gate], "epit", NULL);
135 clk_register_clkdev(clk[epit2_gate], "epit", NULL);
136 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
137 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
138 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
139 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
140 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
141 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
142 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
143 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
144 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
145 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
146 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
147 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
148 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
149 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
150 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
151 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
152 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
153 /* i.mx31 has the i.mx21 type uart */
154 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
155 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
156 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
157 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
158 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
159 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
160 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
161 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
162 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
163 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
164 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
165 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
166 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
167 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
168 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
169 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
170 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
171 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
172 clk_register_clkdev(clk[firi_gate], "firi", NULL);
173 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
174 clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
175 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
176 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
177 clk_register_clkdev(clk[iim_gate], "iim", NULL);
178
179 clk_set_parent(clk[csi], clk[upll]);
180 clk_prepare_enable(clk[emi_gate]);
181 clk_prepare_enable(clk[iim_gate]);
182 mx31_revision();
183 clk_disable_unprepare(clk[iim_gate]);
184
185 mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
186
187 return 0;
188 }
189
mx31_clocks_init_dt(void)190 int __init mx31_clocks_init_dt(void)
191 {
192 struct device_node *np;
193 u32 fref = 26000000; /* default */
194
195 for_each_compatible_node(np, NULL, "fixed-clock") {
196 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
197 continue;
198
199 if (!of_property_read_u32(np, "clock-frequency", &fref))
200 break;
201 }
202
203 return mx31_clocks_init(fref);
204 }
205