1 /*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/ioport.h>
26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h>
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/platform_device.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_pci.h>
35 #include <video/vga.h>
36
37 #include <asm/mach/map.h>
38 #include <asm/signal.h>
39 #include <asm/mach/pci.h>
40 #include <asm/irq_regs.h>
41
42 #include "pci_v3.h"
43 #include "hardware.h"
44
45 /*
46 * Where in the memory map does PCI live?
47 *
48 * This represents a fairly liberal usage of address space. Even though
49 * the V3 only has two windows (therefore we need to map stuff on the fly),
50 * we maintain the same addresses, even if they're not mapped.
51 */
52 #define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */
53 #define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */
54 #define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
55 #define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
56 #define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
57
58 #define PCI_MEMORY_VADDR IOMEM(0xe8000000)
59 #define PCI_CONFIG_VADDR IOMEM(0xec000000)
60
61 /*
62 * V3 Local Bus to PCI Bridge definitions
63 *
64 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
65 * All V3 register names are prefaced by V3_ to avoid clashing with any other
66 * PCI definitions. Their names match the user's manual.
67 *
68 * I'm assuming that I20 is disabled.
69 *
70 */
71 #define V3_PCI_VENDOR 0x00000000
72 #define V3_PCI_DEVICE 0x00000002
73 #define V3_PCI_CMD 0x00000004
74 #define V3_PCI_STAT 0x00000006
75 #define V3_PCI_CC_REV 0x00000008
76 #define V3_PCI_HDR_CFG 0x0000000C
77 #define V3_PCI_IO_BASE 0x00000010
78 #define V3_PCI_BASE0 0x00000014
79 #define V3_PCI_BASE1 0x00000018
80 #define V3_PCI_SUB_VENDOR 0x0000002C
81 #define V3_PCI_SUB_ID 0x0000002E
82 #define V3_PCI_ROM 0x00000030
83 #define V3_PCI_BPARAM 0x0000003C
84 #define V3_PCI_MAP0 0x00000040
85 #define V3_PCI_MAP1 0x00000044
86 #define V3_PCI_INT_STAT 0x00000048
87 #define V3_PCI_INT_CFG 0x0000004C
88 #define V3_LB_BASE0 0x00000054
89 #define V3_LB_BASE1 0x00000058
90 #define V3_LB_MAP0 0x0000005E
91 #define V3_LB_MAP1 0x00000062
92 #define V3_LB_BASE2 0x00000064
93 #define V3_LB_MAP2 0x00000066
94 #define V3_LB_SIZE 0x00000068
95 #define V3_LB_IO_BASE 0x0000006E
96 #define V3_FIFO_CFG 0x00000070
97 #define V3_FIFO_PRIORITY 0x00000072
98 #define V3_FIFO_STAT 0x00000074
99 #define V3_LB_ISTAT 0x00000076
100 #define V3_LB_IMASK 0x00000077
101 #define V3_SYSTEM 0x00000078
102 #define V3_LB_CFG 0x0000007A
103 #define V3_PCI_CFG 0x0000007C
104 #define V3_DMA_PCI_ADR0 0x00000080
105 #define V3_DMA_PCI_ADR1 0x00000090
106 #define V3_DMA_LOCAL_ADR0 0x00000084
107 #define V3_DMA_LOCAL_ADR1 0x00000094
108 #define V3_DMA_LENGTH0 0x00000088
109 #define V3_DMA_LENGTH1 0x00000098
110 #define V3_DMA_CSR0 0x0000008B
111 #define V3_DMA_CSR1 0x0000009B
112 #define V3_DMA_CTLB_ADR0 0x0000008C
113 #define V3_DMA_CTLB_ADR1 0x0000009C
114 #define V3_DMA_DELAY 0x000000E0
115 #define V3_MAIL_DATA 0x000000C0
116 #define V3_PCI_MAIL_IEWR 0x000000D0
117 #define V3_PCI_MAIL_IERD 0x000000D2
118 #define V3_LB_MAIL_IEWR 0x000000D4
119 #define V3_LB_MAIL_IERD 0x000000D6
120 #define V3_MAIL_WR_STAT 0x000000D8
121 #define V3_MAIL_RD_STAT 0x000000DA
122 #define V3_QBA_MAP 0x000000DC
123
124 /* PCI COMMAND REGISTER bits
125 */
126 #define V3_COMMAND_M_FBB_EN (1 << 9)
127 #define V3_COMMAND_M_SERR_EN (1 << 8)
128 #define V3_COMMAND_M_PAR_EN (1 << 6)
129 #define V3_COMMAND_M_MASTER_EN (1 << 2)
130 #define V3_COMMAND_M_MEM_EN (1 << 1)
131 #define V3_COMMAND_M_IO_EN (1 << 0)
132
133 /* SYSTEM REGISTER bits
134 */
135 #define V3_SYSTEM_M_RST_OUT (1 << 15)
136 #define V3_SYSTEM_M_LOCK (1 << 14)
137
138 /* PCI_CFG bits
139 */
140 #define V3_PCI_CFG_M_I2O_EN (1 << 15)
141 #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
142 #define V3_PCI_CFG_M_IO_DIS (1 << 13)
143 #define V3_PCI_CFG_M_EN3V (1 << 12)
144 #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
145 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
146 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
147
148 /* PCI_BASE register bits (PCI -> Local Bus)
149 */
150 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
151 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
152 #define V3_PCI_BASE_M_PREFETCH (1 << 3)
153 #define V3_PCI_BASE_M_TYPE (3 << 1)
154 #define V3_PCI_BASE_M_IO (1 << 0)
155
156 /* PCI MAP register bits (PCI -> Local bus)
157 */
158 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
159 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
160 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
161 #define V3_PCI_MAP_M_SWAP (3 << 8)
162 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
163 #define V3_PCI_MAP_M_REG_EN (1 << 1)
164 #define V3_PCI_MAP_M_ENABLE (1 << 0)
165
166 /*
167 * LB_BASE0,1 register bits (Local bus -> PCI)
168 */
169 #define V3_LB_BASE_ADR_BASE 0xfff00000
170 #define V3_LB_BASE_SWAP (3 << 8)
171 #define V3_LB_BASE_ADR_SIZE (15 << 4)
172 #define V3_LB_BASE_PREFETCH (1 << 3)
173 #define V3_LB_BASE_ENABLE (1 << 0)
174
175 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
176 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
177 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
178 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
179 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
180 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
181 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
182 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
183 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
184 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
185 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
186 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
187
188 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
189
190 /*
191 * LB_MAP0,1 register bits (Local bus -> PCI)
192 */
193 #define V3_LB_MAP_MAP_ADR 0xfff0
194 #define V3_LB_MAP_TYPE (7 << 1)
195 #define V3_LB_MAP_AD_LOW_EN (1 << 0)
196
197 #define V3_LB_MAP_TYPE_IACK (0 << 1)
198 #define V3_LB_MAP_TYPE_IO (1 << 1)
199 #define V3_LB_MAP_TYPE_MEM (3 << 1)
200 #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
201 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
202
203 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
204
205 /*
206 * LB_BASE2 register bits (Local bus -> PCI IO)
207 */
208 #define V3_LB_BASE2_ADR_BASE 0xff00
209 #define V3_LB_BASE2_SWAP (3 << 6)
210 #define V3_LB_BASE2_ENABLE (1 << 0)
211
212 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
213
214 /*
215 * LB_MAP2 register bits (Local bus -> PCI IO)
216 */
217 #define V3_LB_MAP2_MAP_ADR 0xff00
218
219 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
220
221 /*
222 * The V3 PCI interface chip in Integrator provides several windows from
223 * local bus memory into the PCI memory areas. Unfortunately, there
224 * are not really enough windows for our usage, therefore we reuse
225 * one of the windows for access to PCI configuration space. The
226 * memory map is as follows:
227 *
228 * Local Bus Memory Usage
229 *
230 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
231 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
232 * 60000000 - 60FFFFFF PCI IO. 16M
233 * 61000000 - 61FFFFFF PCI Configuration. 16M
234 *
235 * There are three V3 windows, each described by a pair of V3 registers.
236 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
237 * Base0 and Base1 can be used for any type of PCI memory access. Base2
238 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
239 * uses this only for PCI IO space.
240 *
241 * Normally these spaces are mapped using the following base registers:
242 *
243 * Usage Local Bus Memory Base/Map registers used
244 *
245 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
246 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
247 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
248 * Cfg 61000000 - 61FFFFFF
249 *
250 * This means that I20 and PCI configuration space accesses will fail.
251 * When PCI configuration accesses are needed (via the uHAL PCI
252 * configuration space primitives) we must remap the spaces as follows:
253 *
254 * Usage Local Bus Memory Base/Map registers used
255 *
256 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
257 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
258 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
259 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
260 *
261 * To make this work, the code depends on overlapping windows working.
262 * The V3 chip translates an address by checking its range within
263 * each of the BASE/MAP pairs in turn (in ascending register number
264 * order). It will use the first matching pair. So, for example,
265 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
266 * LB_BASE1/LB_MAP1, the V3 will use the translation from
267 * LB_BASE0/LB_MAP0.
268 *
269 * To allow PCI Configuration space access, the code enlarges the
270 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
271 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
272 * be remapped for use by configuration cycles.
273 *
274 * At the end of the PCI Configuration space accesses,
275 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
276 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
277 * reveal the now restored LB_BASE1/LB_MAP1 window.
278 *
279 * NOTE: We do not set up I2O mapping. I suspect that this is only
280 * for an intelligent (target) device. Using I2O disables most of
281 * the mappings into PCI memory.
282 */
283
284 /* Filled in by probe */
285 static void __iomem *pci_v3_base;
286 /* CPU side memory ranges */
287 static struct resource conf_mem; /* FIXME: remap this instead of static map */
288 static struct resource io_mem;
289 static struct resource non_mem;
290 static struct resource pre_mem;
291 /* PCI side memory ranges */
292 static u64 non_mem_pci;
293 static u64 non_mem_pci_sz;
294 static u64 pre_mem_pci;
295 static u64 pre_mem_pci_sz;
296
297 // V3 access routines
298 #define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
299 #define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
300
301 #define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
302 #define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
303
304 #define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
305 #define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
306
307 /*============================================================================
308 *
309 * routine: uHALir_PCIMakeConfigAddress()
310 *
311 * parameters: bus = which bus
312 * device = which device
313 * function = which function
314 * offset = configuration space register we are interested in
315 *
316 * description: this routine will generate a platform dependent config
317 * address.
318 *
319 * calls: none
320 *
321 * returns: configuration address to play on the PCI bus
322 *
323 * To generate the appropriate PCI configuration cycles in the PCI
324 * configuration address space, you present the V3 with the following pattern
325 * (which is very nearly a type 1 (except that the lower two bits are 00 and
326 * not 01). In order for this mapping to work you need to set up one of
327 * the local to PCI aperatures to 16Mbytes in length translating to
328 * PCI configuration space starting at 0x0000.0000.
329 *
330 * PCI configuration cycles look like this:
331 *
332 * Type 0:
333 *
334 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
335 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
336 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
337 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
338 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
339 *
340 * 31:11 Device select bit.
341 * 10:8 Function number
342 * 7:2 Register number
343 *
344 * Type 1:
345 *
346 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
347 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
348 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
349 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
350 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
351 *
352 * 31:24 reserved
353 * 23:16 bus number (8 bits = 128 possible buses)
354 * 15:11 Device number (5 bits)
355 * 10:8 function number
356 * 7:2 register number
357 *
358 */
359 static DEFINE_RAW_SPINLOCK(v3_lock);
360
361 #undef V3_LB_BASE_PREFETCH
362 #define V3_LB_BASE_PREFETCH 0
363
v3_open_config_window(struct pci_bus * bus,unsigned int devfn,int offset)364 static void __iomem *v3_open_config_window(struct pci_bus *bus,
365 unsigned int devfn, int offset)
366 {
367 unsigned int address, mapaddress, busnr;
368
369 busnr = bus->number;
370
371 /*
372 * Trap out illegal values
373 */
374 BUG_ON(offset > 255);
375 BUG_ON(busnr > 255);
376 BUG_ON(devfn > 255);
377
378 if (busnr == 0) {
379 int slot = PCI_SLOT(devfn);
380
381 /*
382 * local bus segment so need a type 0 config cycle
383 *
384 * build the PCI configuration "address" with one-hot in
385 * A31-A11
386 *
387 * mapaddress:
388 * 3:1 = config cycle (101)
389 * 0 = PCI A1 & A0 are 0 (0)
390 */
391 address = PCI_FUNC(devfn) << 8;
392 mapaddress = V3_LB_MAP_TYPE_CONFIG;
393
394 if (slot > 12)
395 /*
396 * high order bits are handled by the MAP register
397 */
398 mapaddress |= 1 << (slot - 5);
399 else
400 /*
401 * low order bits handled directly in the address
402 */
403 address |= 1 << (slot + 11);
404 } else {
405 /*
406 * not the local bus segment so need a type 1 config cycle
407 *
408 * address:
409 * 23:16 = bus number
410 * 15:11 = slot number (7:3 of devfn)
411 * 10:8 = func number (2:0 of devfn)
412 *
413 * mapaddress:
414 * 3:1 = config cycle (101)
415 * 0 = PCI A1 & A0 from host bus (1)
416 */
417 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
418 address = (busnr << 16) | (devfn << 8);
419 }
420
421 /*
422 * Set up base0 to see all 512Mbytes of memory space (not
423 * prefetchable), this frees up base1 for re-use by
424 * configuration memory
425 */
426 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
427 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
428
429 /*
430 * Set up base1/map1 to point into configuration space.
431 */
432 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
433 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
434 v3_writew(V3_LB_MAP1, mapaddress);
435
436 return PCI_CONFIG_VADDR + address + offset;
437 }
438
v3_close_config_window(void)439 static void v3_close_config_window(void)
440 {
441 /*
442 * Reassign base1 for use by prefetchable PCI memory
443 */
444 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
445 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
446 V3_LB_BASE_ENABLE);
447 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
448 V3_LB_MAP_TYPE_MEM_MULTIPLE);
449
450 /*
451 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
452 */
453 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
454 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
455 }
456
v3_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)457 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
458 int size, u32 *val)
459 {
460 void __iomem *addr;
461 unsigned long flags;
462 u32 v;
463
464 raw_spin_lock_irqsave(&v3_lock, flags);
465 addr = v3_open_config_window(bus, devfn, where);
466
467 switch (size) {
468 case 1:
469 v = __raw_readb(addr);
470 break;
471
472 case 2:
473 v = __raw_readw(addr);
474 break;
475
476 default:
477 v = __raw_readl(addr);
478 break;
479 }
480
481 v3_close_config_window();
482 raw_spin_unlock_irqrestore(&v3_lock, flags);
483
484 *val = v;
485 return PCIBIOS_SUCCESSFUL;
486 }
487
v3_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)488 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
489 int size, u32 val)
490 {
491 void __iomem *addr;
492 unsigned long flags;
493
494 raw_spin_lock_irqsave(&v3_lock, flags);
495 addr = v3_open_config_window(bus, devfn, where);
496
497 switch (size) {
498 case 1:
499 __raw_writeb((u8)val, addr);
500 __raw_readb(addr);
501 break;
502
503 case 2:
504 __raw_writew((u16)val, addr);
505 __raw_readw(addr);
506 break;
507
508 case 4:
509 __raw_writel(val, addr);
510 __raw_readl(addr);
511 break;
512 }
513
514 v3_close_config_window();
515 raw_spin_unlock_irqrestore(&v3_lock, flags);
516
517 return PCIBIOS_SUCCESSFUL;
518 }
519
520 static struct pci_ops pci_v3_ops = {
521 .read = v3_read_config,
522 .write = v3_write_config,
523 };
524
pci_v3_setup_resources(struct pci_sys_data * sys)525 static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
526 {
527 if (request_resource(&iomem_resource, &non_mem)) {
528 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
529 "memory region\n");
530 return -EBUSY;
531 }
532 if (request_resource(&iomem_resource, &pre_mem)) {
533 release_resource(&non_mem);
534 printk(KERN_ERR "PCI: unable to allocate prefetchable "
535 "memory region\n");
536 return -EBUSY;
537 }
538
539 /*
540 * the mem resource for this bus
541 * the prefetch mem resource for this bus
542 */
543 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
544 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
545
546 return 1;
547 }
548
549 /*
550 * These don't seem to be implemented on the Integrator I have, which
551 * means I can't get additional information on the reason for the pm2fb
552 * problems. I suppose I'll just have to mind-meld with the machine. ;)
553 */
554 static void __iomem *ap_syscon_base;
555 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
556 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
557 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
558
559 static int
v3_pci_fault(unsigned long addr,unsigned int fsr,struct pt_regs * regs)560 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
561 {
562 unsigned long pc = instruction_pointer(regs);
563 unsigned long instr = *(unsigned long *)pc;
564 #if 0
565 char buf[128];
566
567 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
568 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
569 v3_readb(V3_LB_ISTAT));
570 printk(KERN_DEBUG "%s", buf);
571 #endif
572
573 v3_writeb(V3_LB_ISTAT, 0);
574 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
575
576 /*
577 * If the instruction being executed was a read,
578 * make it look like it read all-ones.
579 */
580 if ((instr & 0x0c100000) == 0x04100000) {
581 int reg = (instr >> 12) & 15;
582 unsigned long val;
583
584 if (instr & 0x00400000)
585 val = 255;
586 else
587 val = -1;
588
589 regs->uregs[reg] = val;
590 regs->ARM_pc += 4;
591 return 0;
592 }
593
594 if ((instr & 0x0e100090) == 0x00100090) {
595 int reg = (instr >> 12) & 15;
596
597 regs->uregs[reg] = -1;
598 regs->ARM_pc += 4;
599 return 0;
600 }
601
602 return 1;
603 }
604
v3_irq(int irq,void * devid)605 static irqreturn_t v3_irq(int irq, void *devid)
606 {
607 #ifdef CONFIG_DEBUG_LL
608 struct pt_regs *regs = get_irq_regs();
609 unsigned long pc = instruction_pointer(regs);
610 unsigned long instr = *(unsigned long *)pc;
611 char buf[128];
612 extern void printascii(const char *);
613
614 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
615 "ISTAT=%02x\n", irq, pc, instr,
616 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
617 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
618 v3_readb(V3_LB_ISTAT));
619 printascii(buf);
620 #endif
621
622 v3_writew(V3_PCI_STAT, 0xf000);
623 v3_writeb(V3_LB_ISTAT, 0);
624 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
625
626 #ifdef CONFIG_DEBUG_LL
627 /*
628 * If the instruction being executed was a read,
629 * make it look like it read all-ones.
630 */
631 if ((instr & 0x0c100000) == 0x04100000) {
632 int reg = (instr >> 16) & 15;
633 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
634 printascii(buf);
635 }
636 #endif
637 return IRQ_HANDLED;
638 }
639
pci_v3_setup(int nr,struct pci_sys_data * sys)640 static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
641 {
642 int ret = 0;
643
644 if (!ap_syscon_base)
645 return -EINVAL;
646
647 if (nr == 0) {
648 sys->mem_offset = non_mem.start;
649 ret = pci_v3_setup_resources(sys);
650 }
651
652 return ret;
653 }
654
655 /*
656 * V3_LB_BASE? - local bus address
657 * V3_LB_MAP? - pci bus address
658 */
pci_v3_preinit(void)659 static void __init pci_v3_preinit(void)
660 {
661 unsigned long flags;
662 unsigned int temp;
663 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
664
665 pcibios_min_mem = 0x00100000;
666
667 /*
668 * Hook in our fault handler for PCI errors
669 */
670 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
671 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
672 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
673 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
674
675 raw_spin_lock_irqsave(&v3_lock, flags);
676
677 /*
678 * Unlock V3 registers, but only if they were previously locked.
679 */
680 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
681 v3_writew(V3_SYSTEM, 0xa05f);
682
683 /*
684 * Setup window 0 - PCI non-prefetchable memory
685 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
686 */
687 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
688 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
689 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
690 V3_LB_MAP_TYPE_MEM);
691
692 /*
693 * Setup window 1 - PCI prefetchable memory
694 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
695 */
696 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
697 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
698 V3_LB_BASE_ENABLE);
699 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
700 V3_LB_MAP_TYPE_MEM_MULTIPLE);
701
702 /*
703 * Setup window 2 - PCI IO
704 */
705 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
706 V3_LB_BASE_ENABLE);
707 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
708
709 /*
710 * Disable PCI to host IO cycles
711 */
712 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
713 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
714 v3_writew(V3_PCI_CFG, temp);
715
716 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
717 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
718
719 /*
720 * Set the V3 FIFO such that writes have higher priority than
721 * reads, and local bus write causes local bus read fifo flush.
722 * Same for PCI.
723 */
724 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
725
726 /*
727 * Re-lock the system register.
728 */
729 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
730 v3_writew(V3_SYSTEM, temp);
731
732 /*
733 * Clear any error conditions, and enable write errors.
734 */
735 v3_writeb(V3_LB_ISTAT, 0);
736 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
737 v3_writeb(V3_LB_IMASK, 0x28);
738 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
739
740 raw_spin_unlock_irqrestore(&v3_lock, flags);
741 }
742
pci_v3_postinit(void)743 static void __init pci_v3_postinit(void)
744 {
745 unsigned int pci_cmd;
746 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
747
748 pci_cmd = PCI_COMMAND_MEMORY |
749 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
750
751 v3_writew(V3_PCI_CMD, pci_cmd);
752
753 v3_writeb(V3_LB_ISTAT, ~0x40);
754 v3_writeb(V3_LB_IMASK, 0x68);
755
756 #if 0
757 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
758 if (ret)
759 printk(KERN_ERR "PCI: unable to grab local bus timeout "
760 "interrupt: %d\n", ret);
761 #endif
762
763 register_isa_ports(non_mem.start, io_address, 0);
764 }
765
766 /*
767 * A small note about bridges and interrupts. The DECchip 21050 (and
768 * later) adheres to the PCI-PCI bridge specification. This says that
769 * the interrupts on the other side of a bridge are swizzled in the
770 * following manner:
771 *
772 * Dev Interrupt Interrupt
773 * Pin on Pin on
774 * Device Connector
775 *
776 * 4 A A
777 * B B
778 * C C
779 * D D
780 *
781 * 5 A B
782 * B C
783 * C D
784 * D A
785 *
786 * 6 A C
787 * B D
788 * C A
789 * D B
790 *
791 * 7 A D
792 * B A
793 * C B
794 * D C
795 *
796 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
797 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
798 */
799
800 /*
801 * This routine handles multiple bridges.
802 */
pci_v3_swizzle(struct pci_dev * dev,u8 * pinp)803 static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
804 {
805 if (*pinp == 0)
806 *pinp = 1;
807
808 return pci_common_swizzle(dev, pinp);
809 }
810
811 static struct hw_pci pci_v3 __initdata = {
812 .swizzle = pci_v3_swizzle,
813 .setup = pci_v3_setup,
814 .nr_controllers = 1,
815 .ops = &pci_v3_ops,
816 .preinit = pci_v3_preinit,
817 .postinit = pci_v3_postinit,
818 };
819
pci_v3_probe(struct platform_device * pdev)820 static int __init pci_v3_probe(struct platform_device *pdev)
821 {
822 struct device_node *np = pdev->dev.of_node;
823 struct of_pci_range_parser parser;
824 struct of_pci_range range;
825 struct resource *res;
826 int irq, ret;
827
828 /* Remap the Integrator system controller */
829 ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100);
830 if (!ap_syscon_base) {
831 dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
832 return -ENODEV;
833 }
834
835 /* Device tree probe path */
836 if (!np) {
837 dev_err(&pdev->dev, "no device tree node for PCIv3\n");
838 return -ENODEV;
839 }
840
841 if (of_pci_range_parser_init(&parser, np))
842 return -EINVAL;
843
844 /* Get base for bridge registers */
845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 if (!res) {
847 dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
848 return -ENODEV;
849 }
850 pci_v3_base = devm_ioremap(&pdev->dev, res->start,
851 resource_size(res));
852 if (!pci_v3_base) {
853 dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
854 return -ENODEV;
855 }
856
857 /* Get and request error IRQ resource */
858 irq = platform_get_irq(pdev, 0);
859 if (irq <= 0) {
860 dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
861 return -ENODEV;
862 }
863 ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
864 "PCIv3 error", NULL);
865 if (ret < 0) {
866 dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
867 return ret;
868 }
869
870 for_each_of_pci_range(&parser, &range) {
871 if (!range.flags) {
872 ret = of_pci_range_to_resource(&range, np, &conf_mem);
873 conf_mem.name = "PCIv3 config";
874 }
875 if (range.flags & IORESOURCE_IO) {
876 ret = of_pci_range_to_resource(&range, np, &io_mem);
877 io_mem.name = "PCIv3 I/O";
878 }
879 if ((range.flags & IORESOURCE_MEM) &&
880 !(range.flags & IORESOURCE_PREFETCH)) {
881 non_mem_pci = range.pci_addr;
882 non_mem_pci_sz = range.size;
883 ret = of_pci_range_to_resource(&range, np, &non_mem);
884 non_mem.name = "PCIv3 non-prefetched mem";
885 }
886 if ((range.flags & IORESOURCE_MEM) &&
887 (range.flags & IORESOURCE_PREFETCH)) {
888 pre_mem_pci = range.pci_addr;
889 pre_mem_pci_sz = range.size;
890 ret = of_pci_range_to_resource(&range, np, &pre_mem);
891 pre_mem.name = "PCIv3 prefetched mem";
892 }
893
894 if (ret < 0) {
895 dev_err(&pdev->dev, "missing ranges in device node\n");
896 return ret;
897 }
898 }
899
900 pci_v3.map_irq = of_irq_parse_and_map_pci;
901 pci_common_init_dev(&pdev->dev, &pci_v3);
902
903 return 0;
904 }
905
906 static const struct of_device_id pci_ids[] = {
907 { .compatible = "v3,v360epc-pci", },
908 {},
909 };
910
911 static struct platform_driver pci_v3_driver = {
912 .driver = {
913 .name = "pci-v3",
914 .of_match_table = pci_ids,
915 },
916 };
917
pci_v3_init(void)918 static int __init pci_v3_init(void)
919 {
920 return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
921 }
922
923 subsys_initcall(pci_v3_init);
924
925 /*
926 * Static mappings for the PCIv3 bridge
927 *
928 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
929 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
930 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
931 */
932 static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
933 {
934 .virtual = (unsigned long)PCI_MEMORY_VADDR,
935 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
936 .length = SZ_16M,
937 .type = MT_DEVICE
938 }, {
939 .virtual = (unsigned long)PCI_CONFIG_VADDR,
940 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
941 .length = SZ_16M,
942 .type = MT_DEVICE
943 }
944 };
945
pci_v3_early_init(void)946 int __init pci_v3_early_init(void)
947 {
948 iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
949 vga_base = (unsigned long)PCI_MEMORY_VADDR;
950 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
951 return 0;
952 }
953