1 #ifndef _IOP13XX_HW_H_
2 #define _IOP13XX_HW_H_
3
4 #ifndef __ASSEMBLY__
5
6 enum reboot_mode;
7
8 /* The ATU offsets can change based on the strapping */
9 extern u32 iop13xx_atux_pmmr_offset;
10 extern u32 iop13xx_atue_pmmr_offset;
11 void iop13xx_init_early(void);
12 void iop13xx_init_irq(void);
13 void iop13xx_map_io(void);
14 void iop13xx_platform_init(void);
15 void iop13xx_add_tpmi_devices(void);
16 void iop13xx_init_irq(void);
17 void iop13xx_restart(enum reboot_mode, const char *);
18
19 /* CPUID CP6 R0 Page 0 */
iop13xx_cpu_id(void)20 static inline int iop13xx_cpu_id(void)
21 {
22 int id;
23 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
24 return id;
25 }
26
27 /* WDTCR CP6 R7 Page 9 */
read_wdtcr(void)28 static inline u32 read_wdtcr(void)
29 {
30 u32 val;
31 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
32 return val;
33 }
write_wdtcr(u32 val)34 static inline void write_wdtcr(u32 val)
35 {
36 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
37 }
38
39 /* WDTSR CP6 R8 Page 9 */
read_wdtsr(void)40 static inline u32 read_wdtsr(void)
41 {
42 u32 val;
43 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
44 return val;
45 }
write_wdtsr(u32 val)46 static inline void write_wdtsr(u32 val)
47 {
48 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
49 }
50
51 /* RCSR - Reset Cause Status Register */
read_rcsr(void)52 static inline u32 read_rcsr(void)
53 {
54 u32 val;
55 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
56 return val;
57 }
58
59 extern unsigned long get_iop_tick_rate(void);
60 #endif
61
62 /*
63 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
64 */
65 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
66 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
67
68 /* PCI MAP
69 * bus range cpu phys cpu virt note
70 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
71 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
72 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
73 *
74 * IO MAP
75 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
76 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
77 */
78 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
79 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
80
81 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
82 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
83 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
84 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
85 IOP13XX_PCIX_LOWER_MEM_BA)
86 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
87 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
88 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
89 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
90
91 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
92 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
93 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
94 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
95 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
96 IOP13XX_PCIX_LOWER_MEM_BA)
97
98 /* PCI-E ranges */
99 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
100 #define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
101
102 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
103 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
104 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
105 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
106 IOP13XX_PCIE_LOWER_MEM_BA)
107 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
108 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
109 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
110 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
111
112 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
113 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
114 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
115 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
116 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
117 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
118 IOP13XX_PCIE_LOWER_MEM_BA)
119
120 /* PBI Ranges */
121 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
122 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
123 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
124 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
125 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
126 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
127
128 /*
129 * IOP13XX chipset registers
130 */
131 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
132 #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
133 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
134 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
135 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
136 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
137 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
138 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
139 + IOP13XX_PMMR_PHYS_MEM_BASE)
140 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
141 + IOP13XX_PMMR_VIRT_MEM_BASE)
142 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
143 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
144 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
145 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
146 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
147 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
148 #define IOP13XX_PMMR_SIZE 0x00080000
149
150 /*=================== Defines for Platform Devices =====================*/
151 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
152 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
153 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
154 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
155
156 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
157 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
158 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
159 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
160 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
161 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
162
163 /* ATU selection flags */
164 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
165 #define IOP13XX_INIT_ATU_DEFAULT (0)
166 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
167 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
168 #define IOP13XX_INIT_ATU_NONE (1 << 2)
169
170 /* UART selection flags */
171 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
172 #define IOP13XX_INIT_UART_DEFAULT (0)
173 #define IOP13XX_INIT_UART_0 (1 << 0)
174 #define IOP13XX_INIT_UART_1 (1 << 1)
175
176 /* I2C selection flags */
177 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
178 #define IOP13XX_INIT_I2C_DEFAULT (0)
179 #define IOP13XX_INIT_I2C_0 (1 << 0)
180 #define IOP13XX_INIT_I2C_1 (1 << 1)
181 #define IOP13XX_INIT_I2C_2 (1 << 2)
182
183 /* ADMA selection flags */
184 /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
185 #define IOP13XX_INIT_ADMA_DEFAULT (0)
186 #define IOP13XX_INIT_ADMA_0 (1 << 0)
187 #define IOP13XX_INIT_ADMA_1 (1 << 1)
188 #define IOP13XX_INIT_ADMA_2 (1 << 2)
189
190 /* Platform devices */
191 #define IQ81340_NUM_UART 2
192 #define IQ81340_NUM_I2C 3
193 #define IQ81340_NUM_PHYS_MAP_FLASH 1
194 #define IQ81340_NUM_ADMA 3
195 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
196 IQ81340_NUM_I2C + \
197 IQ81340_NUM_PHYS_MAP_FLASH + \
198 IQ81340_NUM_ADMA)
199
200 /*========================== PMMR offsets for key registers ============*/
201 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
202 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
203 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
204 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
205 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
206 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
207 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
208 #define IOP13XX_MU_PMMR_OFFSET 0x00004000
209 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
210 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
211
212 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
213 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
214 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
215
216 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
217 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
218 IOP13XX_PMON_PMMR_OFFSET)
219 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
220 IOP13XX_PMON_PMMR_OFFSET)
221
222 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
223 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
224 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
225 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
226
227 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
228 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
229 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
230 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
231
232 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
233 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
234 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
235 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
236
237 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
238 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
239
240 /*================================ATU===================================*/
241 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
242 iop13xx_atux_pmmr_offset + (ofs))
243
244 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
245 iop13xx_atux_pmmr_offset + 0x2)
246
247 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
248 iop13xx_atux_pmmr_offset + 0x4)
249 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
250 iop13xx_atux_pmmr_offset + 0x6)
251
252 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
253 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
254 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
255 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
256 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
257 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
258 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
259 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
260 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
261 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
262 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
263 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
264 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
265 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
266 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
267 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
268 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
269 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
270 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
271 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
272 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
273 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
274 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
275 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
276
277 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
278 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
279 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
280 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
281 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
282 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
283 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
284 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
285 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
286 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
287 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
288 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
289 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
290 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
291
292 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
293 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
294 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
295 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
296 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
297 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
298
299 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
300 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
301 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
302 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
303 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
304 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
305 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
306 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
307 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
308 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
309 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
310 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
311 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
312 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
313 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
314 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
315 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
316
317 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
318 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
319 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
320
321 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
322 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
323
324 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
325 iop13xx_atue_pmmr_offset + (ofs))
326
327 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
328 iop13xx_atue_pmmr_offset + 0x2)
329 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
330 iop13xx_atue_pmmr_offset + 0x4)
331 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
332 iop13xx_atue_pmmr_offset + 0x6)
333
334 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
335 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
336 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
337 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
338 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
339 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
340 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
341 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
342 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
343 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
344 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
345 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
346 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
347 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
348 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
349 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
350 iop13xx_atue_pmmr_offset + 0xe2)
351 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
352 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
353 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
354 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
355 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
356 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
357 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
358 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
359 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
360
361 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
362 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
363 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
364 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
365 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
366 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
367
368 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
369 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
370
371 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
372 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
373 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
374 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
375 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
376 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
377 #define IOP13XX_ATUE_OCCAR_REG (2)
378
379 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
380 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
381 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
382 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
383 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
384 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
385 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
386
387 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
388 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
389 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
390
391 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
392 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
393
394 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
395 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
396 #define IOP13XX_ATUE_STAT_PME (1 << 27)
397 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
398 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
399 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
400 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
401 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
402 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
403 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
404 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
405 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
406 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
407 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
408 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
409 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
410 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
411 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
412 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
413 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
414 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
415 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
416 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
417
418 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
419 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
420 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
421 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
422 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
423 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
424 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
425 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
426 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
427 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
428 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
429 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
430 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
431 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
432 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
433
434 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
435 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
436 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
437 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
438 /*=======================================================================*/
439
440 /*============================MESSAGING UNIT=============================*/
441 #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
442 (ofs))
443
444 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
445 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
446 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
447 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
448 #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
449 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
450 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
451 #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
452 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
453 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
454 #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
455 #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
456 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
457 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
458 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
459 #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
460
461 #define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
462 #define IOP13XX_MU_BASE_PHYS (0xff000000)
463 #define IOP13XX_MU_BASE_PCI (0xff000000)
464 #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
465 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
466 /*=======================================================================*/
467
468 /*==============================ADMA UNITS===============================*/
469 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
470 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
471
472 /*==============================XSI BRIDGE===============================*/
473 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
474 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
475 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
476 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
477 IOP13XX_PMMR_VIRT_TO_PHYS(\
478 IOP13XX_ATUE_OCCDR))\
479 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
480 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
481 IOP13XX_PMMR_VIRT_TO_PHYS(\
482 IOP13XX_ATUX_OCCDR))\
483 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
484 /*=======================================================================*/
485
486 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
487 (ofs))
488
489 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
490 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
491 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
492 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
493 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
494 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
495
496 #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
497
498 /* Watchdog timer definitions */
499 #define IOP_WDTCR_EN_ARM 0x1e1e1e1e
500 #define IOP_WDTCR_EN 0xe1e1e1e1
501 #define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
502 #define IOP_WDTCR_DIS 0xf1f1f1f1
503 #define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
504 #define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
505 #define IOP13XX_WDTCR_IB_RESET (1 << 0)
506
507 #endif /* _IOP13XX_HW_H_ */
508