1 #ifndef _IOP13XX_TIME_H_
2 #define _IOP13XX_TIME_H_
3
4 #include <mach/irqs.h>
5
6 #define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
7
8 #define IOP_TMR_EN 0x02
9 #define IOP_TMR_RELOAD 0x04
10 #define IOP_TMR_PRIVILEGED 0x08
11 #define IOP_TMR_RATIO_1_1 0x00
12
13 #define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
14 #define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
15 #define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
16 #define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
17 #define IOP13XX_CORE_FREQ_MASK (7 << 16)
18 #define IOP13XX_CORE_FREQ_600 (0 << 16)
19 #define IOP13XX_CORE_FREQ_667 (1 << 16)
20 #define IOP13XX_CORE_FREQ_800 (2 << 16)
21 #define IOP13XX_CORE_FREQ_933 (3 << 16)
22 #define IOP13XX_CORE_FREQ_1000 (4 << 16)
23 #define IOP13XX_CORE_FREQ_1200 (5 << 16)
24
25 void iop_init_time(unsigned long tickrate);
26
iop13xx_core_freq(void)27 static inline unsigned long iop13xx_core_freq(void)
28 {
29 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
30 freq &= IOP13XX_CORE_FREQ_MASK;
31 switch (freq) {
32 case IOP13XX_CORE_FREQ_600:
33 return 600000000;
34 case IOP13XX_CORE_FREQ_667:
35 return 667000000;
36 case IOP13XX_CORE_FREQ_800:
37 return 800000000;
38 case IOP13XX_CORE_FREQ_933:
39 return 933000000;
40 case IOP13XX_CORE_FREQ_1000:
41 return 1000000000;
42 case IOP13XX_CORE_FREQ_1200:
43 return 1200000000;
44 default:
45 printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
46 __func__);
47 }
48
49 return 800000000;
50 }
51
iop13xx_xsi_bus_ratio(void)52 static inline unsigned long iop13xx_xsi_bus_ratio(void)
53 {
54 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
55 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
56 switch (ratio) {
57 case IOP13XX_XSI_FREQ_RATIO_2:
58 return 2;
59 case IOP13XX_XSI_FREQ_RATIO_3:
60 return 3;
61 case IOP13XX_XSI_FREQ_RATIO_4:
62 return 4;
63 default:
64 printk("%s: warning unknown ratio, defaulting to 2\n",
65 __func__);
66 }
67
68 return 2;
69 }
70
read_tmr0(void)71 static inline u32 read_tmr0(void)
72 {
73 u32 val;
74 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
75 return val;
76 }
77
write_tmr0(u32 val)78 static inline void write_tmr0(u32 val)
79 {
80 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
81 }
82
write_tmr1(u32 val)83 static inline void write_tmr1(u32 val)
84 {
85 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
86 }
87
read_tcr0(void)88 static inline u32 read_tcr0(void)
89 {
90 u32 val;
91 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
92 return val;
93 }
94
write_tcr0(u32 val)95 static inline void write_tcr0(u32 val)
96 {
97 asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
98 }
99
read_tcr1(void)100 static inline u32 read_tcr1(void)
101 {
102 u32 val;
103 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
104 return val;
105 }
106
write_tcr1(u32 val)107 static inline void write_tcr1(u32 val)
108 {
109 asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
110 }
111
write_trr0(u32 val)112 static inline void write_trr0(u32 val)
113 {
114 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
115 }
116
write_trr1(u32 val)117 static inline void write_trr1(u32 val)
118 {
119 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
120 }
121
write_tisr(u32 val)122 static inline void write_tisr(u32 val)
123 {
124 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
125 }
126 #endif
127