1 /* 2 * MMP2 Power Management Routines 3 * 4 * This software program is licensed subject to the GNU General Public License 5 * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html 6 * 7 * (C) Copyright 2010 Marvell International Ltd. 8 * All Rights Reserved 9 */ 10 11 #ifndef __MMP2_PM_H__ 12 #define __MMP2_PM_H__ 13 14 #include <mach/addr-map.h> 15 16 #define APMU_PJ_IDLE_CFG APMU_REG(0x018) 17 #define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) 18 #define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) 19 #define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) 20 #define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) 21 #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) 22 23 #define APMU_SRAM_PWR_DWN APMU_REG(0x08c) 24 25 #define MPMU_SCCR MPMU_REG(0x038) 26 #define MPMU_PCR_PJ MPMU_REG(0x1000) 27 #define MPMU_PCR_PJ_AXISD (1 << 31) 28 #define MPMU_PCR_PJ_SLPEN (1 << 29) 29 #define MPMU_PCR_PJ_SPSD (1 << 28) 30 #define MPMU_PCR_PJ_DDRCORSD (1 << 27) 31 #define MPMU_PCR_PJ_APBSD (1 << 26) 32 #define MPMU_PCR_PJ_INTCLR (1 << 24) 33 #define MPMU_PCR_PJ_SLPWP0 (1 << 23) 34 #define MPMU_PCR_PJ_SLPWP1 (1 << 22) 35 #define MPMU_PCR_PJ_SLPWP2 (1 << 21) 36 #define MPMU_PCR_PJ_SLPWP3 (1 << 20) 37 #define MPMU_PCR_PJ_VCTCXOSD (1 << 19) 38 #define MPMU_PCR_PJ_SLPWP4 (1 << 18) 39 #define MPMU_PCR_PJ_SLPWP5 (1 << 17) 40 #define MPMU_PCR_PJ_SLPWP6 (1 << 16) 41 #define MPMU_PCR_PJ_SLPWP7 (1 << 15) 42 43 #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) 44 #define MPMU_CGR_PJ MPMU_REG(0x1024) 45 #define MPMU_WUCRM_PJ MPMU_REG(0x104c) 46 #define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) 47 #define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) 48 49 enum { 50 POWER_MODE_ACTIVE = 0, 51 POWER_MODE_CORE_INTIDLE, 52 POWER_MODE_CORE_EXTIDLE, 53 POWER_MODE_APPS_IDLE, 54 POWER_MODE_APPS_SLEEP, 55 POWER_MODE_CHIP_SLEEP, 56 POWER_MODE_SYS_SLEEP, 57 }; 58 59 extern void mmp2_pm_enter_lowpower_mode(int state); 60 extern int mmp2_set_wake(struct irq_data *d, unsigned int on); 61 #endif 62