1 /*
2 * linux/arch/arm/mach-omap1/time.c
3 *
4 * OMAP Timers
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 *
11 * MPU timer code based on the older MPU timer code for OMAP
12 * Copyright (C) 2000 RidgeRun, Inc.
13 * Author: Greg Lonnon <glonnon@ridgerun.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/spinlock.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/clocksource.h>
44 #include <linux/clockchips.h>
45 #include <linux/io.h>
46 #include <linux/sched_clock.h>
47
48 #include <asm/irq.h>
49
50 #include <mach/hardware.h>
51 #include <asm/mach/irq.h>
52 #include <asm/mach/time.h>
53
54 #include "iomap.h"
55 #include "common.h"
56
57 #ifdef CONFIG_OMAP_MPU_TIMER
58
59 #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
60 #define OMAP_MPU_TIMER_OFFSET 0x100
61
62 typedef struct {
63 u32 cntl; /* CNTL_TIMER, R/W */
64 u32 load_tim; /* LOAD_TIM, W */
65 u32 read_tim; /* READ_TIM, R */
66 } omap_mpu_timer_regs_t;
67
68 #define omap_mpu_timer_base(n) \
69 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
70 (n)*OMAP_MPU_TIMER_OFFSET))
71
omap_mpu_timer_read(int nr)72 static inline unsigned long notrace omap_mpu_timer_read(int nr)
73 {
74 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
75 return readl(&timer->read_tim);
76 }
77
omap_mpu_set_autoreset(int nr)78 static inline void omap_mpu_set_autoreset(int nr)
79 {
80 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
81
82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
83 }
84
omap_mpu_remove_autoreset(int nr)85 static inline void omap_mpu_remove_autoreset(int nr)
86 {
87 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
88
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
90 }
91
omap_mpu_timer_start(int nr,unsigned long load_val,int autoreset)92 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
93 int autoreset)
94 {
95 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
96 unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
97
98 if (autoreset)
99 timerflags |= MPU_TIMER_AR;
100
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
102 udelay(1);
103 writel(load_val, &timer->load_tim);
104 udelay(1);
105 writel(timerflags, &timer->cntl);
106 }
107
omap_mpu_timer_stop(int nr)108 static inline void omap_mpu_timer_stop(int nr)
109 {
110 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
111
112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
113 }
114
115 /*
116 * ---------------------------------------------------------------------------
117 * MPU timer 1 ... count down to zero, interrupt, reload
118 * ---------------------------------------------------------------------------
119 */
omap_mpu_set_next_event(unsigned long cycles,struct clock_event_device * evt)120 static int omap_mpu_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122 {
123 omap_mpu_timer_start(0, cycles, 0);
124 return 0;
125 }
126
omap_mpu_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)127 static void omap_mpu_set_mode(enum clock_event_mode mode,
128 struct clock_event_device *evt)
129 {
130 switch (mode) {
131 case CLOCK_EVT_MODE_PERIODIC:
132 omap_mpu_set_autoreset(0);
133 break;
134 case CLOCK_EVT_MODE_ONESHOT:
135 omap_mpu_timer_stop(0);
136 omap_mpu_remove_autoreset(0);
137 break;
138 case CLOCK_EVT_MODE_UNUSED:
139 case CLOCK_EVT_MODE_SHUTDOWN:
140 case CLOCK_EVT_MODE_RESUME:
141 break;
142 }
143 }
144
145 static struct clock_event_device clockevent_mpu_timer1 = {
146 .name = "mpu_timer1",
147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
148 .set_next_event = omap_mpu_set_next_event,
149 .set_mode = omap_mpu_set_mode,
150 };
151
omap_mpu_timer1_interrupt(int irq,void * dev_id)152 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
153 {
154 struct clock_event_device *evt = &clockevent_mpu_timer1;
155
156 evt->event_handler(evt);
157
158 return IRQ_HANDLED;
159 }
160
161 static struct irqaction omap_mpu_timer1_irq = {
162 .name = "mpu_timer1",
163 .flags = IRQF_TIMER | IRQF_IRQPOLL,
164 .handler = omap_mpu_timer1_interrupt,
165 };
166
omap_init_mpu_timer(unsigned long rate)167 static __init void omap_init_mpu_timer(unsigned long rate)
168 {
169 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
170 omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
171
172 clockevent_mpu_timer1.cpumask = cpumask_of(0);
173 clockevents_config_and_register(&clockevent_mpu_timer1, rate,
174 1, -1);
175 }
176
177
178 /*
179 * ---------------------------------------------------------------------------
180 * MPU timer 2 ... free running 32-bit clock source and scheduler clock
181 * ---------------------------------------------------------------------------
182 */
183
omap_mpu_read_sched_clock(void)184 static u64 notrace omap_mpu_read_sched_clock(void)
185 {
186 return ~omap_mpu_timer_read(1);
187 }
188
omap_init_clocksource(unsigned long rate)189 static void __init omap_init_clocksource(unsigned long rate)
190 {
191 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
192 static char err[] __initdata = KERN_ERR
193 "%s: can't register clocksource!\n";
194
195 omap_mpu_timer_start(1, ~0, 1);
196 sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
197
198 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
199 300, 32, clocksource_mmio_readl_down))
200 printk(err, "mpu_timer2");
201 }
202
omap_mpu_timer_init(void)203 static void __init omap_mpu_timer_init(void)
204 {
205 struct clk *ck_ref = clk_get(NULL, "ck_ref");
206 unsigned long rate;
207
208 BUG_ON(IS_ERR(ck_ref));
209
210 rate = clk_get_rate(ck_ref);
211 clk_put(ck_ref);
212
213 /* PTV = 0 */
214 rate /= 2;
215
216 omap_init_mpu_timer(rate);
217 omap_init_clocksource(rate);
218 }
219
220 #else
omap_mpu_timer_init(void)221 static inline void omap_mpu_timer_init(void)
222 {
223 pr_err("Bogus timer, should not happen\n");
224 }
225 #endif /* CONFIG_OMAP_MPU_TIMER */
226
227 /*
228 * ---------------------------------------------------------------------------
229 * Timer initialization
230 * ---------------------------------------------------------------------------
231 */
omap1_timer_init(void)232 void __init omap1_timer_init(void)
233 {
234 if (omap_32k_timer_init() != 0)
235 omap_mpu_timer_init();
236 }
237