1 /*
2 * OMAP2/3/4 DPLL clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/clk-provider.h>
20 #include <linux/io.h>
21
22 #include <asm/div64.h>
23
24 #include "clock.h"
25
26 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
27 #define DPLL_MIN_MULTIPLIER 2
28 #define DPLL_MIN_DIVIDER 1
29
30 /* Possible error results from _dpll_test_mult */
31 #define DPLL_MULT_UNDERFLOW -1
32
33 /*
34 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
35 * The higher the scale factor, the greater the risk of arithmetic overflow,
36 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
37 * must be a power of DPLL_SCALE_BASE.
38 */
39 #define DPLL_SCALE_FACTOR 64
40 #define DPLL_SCALE_BASE 2
41 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
42 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
43
44 /*
45 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
46 * From device data manual section 4.3 "DPLL and DLL Specifications".
47 */
48 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
49 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
50
51 /* _dpll_test_fint() return codes */
52 #define DPLL_FINT_UNDERFLOW -1
53 #define DPLL_FINT_INVALID -2
54
55 /* Private functions */
56
57 /*
58 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
59 * @clk: DPLL struct clk to test
60 * @n: divider value (N) to test
61 *
62 * Tests whether a particular divider @n will result in a valid DPLL
63 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
64 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
65 * (assuming that it is counting N upwards), or -2 if the enclosing loop
66 * should skip to the next iteration (again assuming N is increasing).
67 */
_dpll_test_fint(struct clk_hw_omap * clk,unsigned int n)68 static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
69 {
70 struct dpll_data *dd;
71 long fint, fint_min, fint_max;
72 int ret = 0;
73
74 dd = clk->dpll_data;
75
76 /* DPLL divider must result in a valid jitter correction val */
77 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
78
79 if (dd->flags & DPLL_J_TYPE) {
80 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
81 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
82 } else {
83 fint_min = ti_clk_features.fint_min;
84 fint_max = ti_clk_features.fint_max;
85 }
86
87 if (!fint_min || !fint_max) {
88 WARN(1, "No fint limits available!\n");
89 return DPLL_FINT_INVALID;
90 }
91
92 if (fint < ti_clk_features.fint_min) {
93 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
94 n);
95 dd->max_divider = n;
96 ret = DPLL_FINT_UNDERFLOW;
97 } else if (fint > ti_clk_features.fint_max) {
98 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
99 n);
100 dd->min_divider = n;
101 ret = DPLL_FINT_INVALID;
102 } else if (fint > ti_clk_features.fint_band1_max &&
103 fint < ti_clk_features.fint_band2_min) {
104 pr_debug("rejecting n=%d due to Fint failure\n", n);
105 ret = DPLL_FINT_INVALID;
106 }
107
108 return ret;
109 }
110
_dpll_compute_new_rate(unsigned long parent_rate,unsigned int m,unsigned int n)111 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
112 unsigned int m, unsigned int n)
113 {
114 unsigned long long num;
115
116 num = (unsigned long long)parent_rate * m;
117 do_div(num, n);
118 return num;
119 }
120
121 /*
122 * _dpll_test_mult - test a DPLL multiplier value
123 * @m: pointer to the DPLL m (multiplier) value under test
124 * @n: current DPLL n (divider) value under test
125 * @new_rate: pointer to storage for the resulting rounded rate
126 * @target_rate: the desired DPLL rate
127 * @parent_rate: the DPLL's parent clock rate
128 *
129 * This code tests a DPLL multiplier value, ensuring that the
130 * resulting rate will not be higher than the target_rate, and that
131 * the multiplier value itself is valid for the DPLL. Initially, the
132 * integer pointed to by the m argument should be prescaled by
133 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
134 * a non-scaled m upon return. This non-scaled m will result in a
135 * new_rate as close as possible to target_rate (but not greater than
136 * target_rate) given the current (parent_rate, n, prescaled m)
137 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
138 * non-scaled m attempted to underflow, which can allow the calling
139 * function to bail out early; or 0 upon success.
140 */
_dpll_test_mult(int * m,int n,unsigned long * new_rate,unsigned long target_rate,unsigned long parent_rate)141 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
142 unsigned long target_rate,
143 unsigned long parent_rate)
144 {
145 int r = 0, carry = 0;
146
147 /* Unscale m and round if necessary */
148 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
149 carry = 1;
150 *m = (*m / DPLL_SCALE_FACTOR) + carry;
151
152 /*
153 * The new rate must be <= the target rate to avoid programming
154 * a rate that is impossible for the hardware to handle
155 */
156 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
157 if (*new_rate > target_rate) {
158 (*m)--;
159 *new_rate = 0;
160 }
161
162 /* Guard against m underflow */
163 if (*m < DPLL_MIN_MULTIPLIER) {
164 *m = DPLL_MIN_MULTIPLIER;
165 *new_rate = 0;
166 r = DPLL_MULT_UNDERFLOW;
167 }
168
169 if (*new_rate == 0)
170 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
171
172 return r;
173 }
174
175 /**
176 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
177 * @v: bitfield value of the DPLL enable
178 *
179 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
180 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
181 */
_omap2_dpll_is_in_bypass(u32 v)182 static int _omap2_dpll_is_in_bypass(u32 v)
183 {
184 u8 mask, val;
185
186 mask = ti_clk_features.dpll_bypass_vals;
187
188 /*
189 * Each set bit in the mask corresponds to a bypass value equal
190 * to the bitshift. Go through each set-bit in the mask and
191 * compare against the given register value.
192 */
193 while (mask) {
194 val = __ffs(mask);
195 mask ^= (1 << val);
196 if (v == val)
197 return 1;
198 }
199
200 return 0;
201 }
202
203 /* Public functions */
omap2_init_dpll_parent(struct clk_hw * hw)204 u8 omap2_init_dpll_parent(struct clk_hw *hw)
205 {
206 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
207 u32 v;
208 struct dpll_data *dd;
209
210 dd = clk->dpll_data;
211 if (!dd)
212 return -EINVAL;
213
214 v = omap2_clk_readl(clk, dd->control_reg);
215 v &= dd->enable_mask;
216 v >>= __ffs(dd->enable_mask);
217
218 /* Reparent the struct clk in case the dpll is in bypass */
219 if (_omap2_dpll_is_in_bypass(v))
220 return 1;
221
222 return 0;
223 }
224
225 /**
226 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
227 * @clk: struct clk * of a DPLL
228 *
229 * DPLLs can be locked or bypassed - basically, enabled or disabled.
230 * When locked, the DPLL output depends on the M and N values. When
231 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
232 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
233 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
234 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
235 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
236 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
237 * if the clock @clk is not a DPLL.
238 */
omap2_get_dpll_rate(struct clk_hw_omap * clk)239 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
240 {
241 long long dpll_clk;
242 u32 dpll_mult, dpll_div, v;
243 struct dpll_data *dd;
244
245 dd = clk->dpll_data;
246 if (!dd)
247 return 0;
248
249 /* Return bypass rate if DPLL is bypassed */
250 v = omap2_clk_readl(clk, dd->control_reg);
251 v &= dd->enable_mask;
252 v >>= __ffs(dd->enable_mask);
253
254 if (_omap2_dpll_is_in_bypass(v))
255 return __clk_get_rate(dd->clk_bypass);
256
257 v = omap2_clk_readl(clk, dd->mult_div1_reg);
258 dpll_mult = v & dd->mult_mask;
259 dpll_mult >>= __ffs(dd->mult_mask);
260 dpll_div = v & dd->div1_mask;
261 dpll_div >>= __ffs(dd->div1_mask);
262
263 dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
264 do_div(dpll_clk, dpll_div + 1);
265
266 return dpll_clk;
267 }
268
269 /* DPLL rate rounding code */
270
271 /**
272 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
273 * @clk: struct clk * for a DPLL
274 * @target_rate: desired DPLL clock rate
275 *
276 * Given a DPLL and a desired target rate, round the target rate to a
277 * possible, programmable rate for this DPLL. Attempts to select the
278 * minimum possible n. Stores the computed (m, n) in the DPLL's
279 * dpll_data structure so set_rate() will not need to call this
280 * (expensive) function again. Returns ~0 if the target rate cannot
281 * be rounded, or the rounded rate upon success.
282 */
omap2_dpll_round_rate(struct clk_hw * hw,unsigned long target_rate,unsigned long * parent_rate)283 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
284 unsigned long *parent_rate)
285 {
286 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
287 int m, n, r, scaled_max_m;
288 int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
289 unsigned long scaled_rt_rp;
290 unsigned long new_rate = 0;
291 struct dpll_data *dd;
292 unsigned long ref_rate;
293 long delta;
294 long prev_min_delta = LONG_MAX;
295 const char *clk_name;
296
297 if (!clk || !clk->dpll_data)
298 return ~0;
299
300 dd = clk->dpll_data;
301
302 ref_rate = __clk_get_rate(dd->clk_ref);
303 clk_name = __clk_get_name(hw->clk);
304 pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
305 clk_name, target_rate);
306
307 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
308 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
309
310 dd->last_rounded_rate = 0;
311
312 for (n = dd->min_divider; n <= dd->max_divider; n++) {
313
314 /* Is the (input clk, divider) pair valid for the DPLL? */
315 r = _dpll_test_fint(clk, n);
316 if (r == DPLL_FINT_UNDERFLOW)
317 break;
318 else if (r == DPLL_FINT_INVALID)
319 continue;
320
321 /* Compute the scaled DPLL multiplier, based on the divider */
322 m = scaled_rt_rp * n;
323
324 /*
325 * Since we're counting n up, a m overflow means we
326 * can bail out completely (since as n increases in
327 * the next iteration, there's no way that m can
328 * increase beyond the current m)
329 */
330 if (m > scaled_max_m)
331 break;
332
333 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
334 ref_rate);
335
336 /* m can't be set low enough for this n - try with a larger n */
337 if (r == DPLL_MULT_UNDERFLOW)
338 continue;
339
340 /* skip rates above our target rate */
341 delta = target_rate - new_rate;
342 if (delta < 0)
343 continue;
344
345 if (delta < prev_min_delta) {
346 prev_min_delta = delta;
347 min_delta_m = m;
348 min_delta_n = n;
349 }
350
351 pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
352 clk_name, m, n, new_rate);
353
354 if (delta == 0)
355 break;
356 }
357
358 if (prev_min_delta == LONG_MAX) {
359 pr_debug("clock: %s: cannot round to rate %lu\n",
360 clk_name, target_rate);
361 return ~0;
362 }
363
364 dd->last_rounded_m = min_delta_m;
365 dd->last_rounded_n = min_delta_n;
366 dd->last_rounded_rate = target_rate - prev_min_delta;
367
368 return dd->last_rounded_rate;
369 }
370
371