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1 /*
2  * Copyright (C) ST-Ericsson SA 2011
3  *
4  * License terms: GNU General Public License (GPL) version 2
5  */
6 
7 #include <linux/io.h>
8 #include <linux/of.h>
9 
10 #include <asm/hardware/cache-l2x0.h>
11 
12 #include "db8500-regs.h"
13 #include "id.h"
14 
ux500_l2x0_unlock(void)15 static int __init ux500_l2x0_unlock(void)
16 {
17 	int i;
18 	void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE);
19 
20 	/*
21 	 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
22 	 * apparently locks both caches before jumping to the kernel. The
23 	 * l2x0 core will not touch the unlock registers if the l2x0 is
24 	 * already enabled, so we do it right here instead. The PL310 has
25 	 * 8 sets of registers, one per possible CPU.
26 	 */
27 	for (i = 0; i < 8; i++) {
28 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
29 			       i * L2X0_LOCKDOWN_STRIDE);
30 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
31 			       i * L2X0_LOCKDOWN_STRIDE);
32 	}
33 	return 0;
34 }
35 
ux500_l2c310_write_sec(unsigned long val,unsigned reg)36 static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
37 {
38 	/*
39 	 * We can't write to secure registers as we are in non-secure
40 	 * mode, until we have some SMI service available.
41 	 */
42 }
43 
ux500_l2x0_init(void)44 static int __init ux500_l2x0_init(void)
45 {
46 	/* Multiplatform guard */
47 	if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
48 		return -ENODEV;
49 
50 	/* Unlock before init */
51 	ux500_l2x0_unlock();
52 	outer_cache.write_sec = ux500_l2c310_write_sec;
53 	l2x0_of_init(0, ~0);
54 
55 	return 0;
56 }
57 early_initcall(ux500_l2x0_init);
58