1 /*
2 * Versatile Express Core Tile Cortex A9x4 Support
3 */
4 #include <linux/init.h>
5 #include <linux/gfp.h>
6 #include <linux/device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/platform_device.h>
9 #include <linux/amba/bus.h>
10 #include <linux/amba/clcd.h>
11 #include <linux/platform_data/video-clcd-versatile.h>
12 #include <linux/clkdev.h>
13 #include <linux/vexpress.h>
14 #include <linux/irqchip/arm-gic.h>
15
16 #include <asm/hardware/arm_timer.h>
17 #include <asm/hardware/cache-l2x0.h>
18 #include <asm/smp_scu.h>
19 #include <asm/smp_twd.h>
20
21 #include <mach/ct-ca9x4.h>
22
23 #include <asm/hardware/timer-sp.h>
24
25 #include <asm/mach/map.h>
26 #include <asm/mach/time.h>
27
28 #include "core.h"
29
30 #include <mach/motherboard.h>
31 #include <mach/irqs.h>
32
33 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
34 {
35 .virtual = V2T_PERIPH,
36 .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
37 .length = SZ_8K,
38 .type = MT_DEVICE,
39 },
40 };
41
ct_ca9x4_map_io(void)42 static void __init ct_ca9x4_map_io(void)
43 {
44 iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
45 }
46
ca9x4_l2_init(void)47 static void __init ca9x4_l2_init(void)
48 {
49 #ifdef CONFIG_CACHE_L2X0
50 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
51
52 if (l2x0_base) {
53 /* set RAM latencies to 1 cycle for this core tile. */
54 writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
55 writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
56
57 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
58 } else {
59 pr_err("L2C: unable to map L2 cache controller\n");
60 }
61 #endif
62 }
63
64 #ifdef CONFIG_HAVE_ARM_TWD
65 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
66
ca9x4_twd_init(void)67 static void __init ca9x4_twd_init(void)
68 {
69 int err = twd_local_timer_register(&twd_local_timer);
70 if (err)
71 pr_err("twd_local_timer_register failed %d\n", err);
72 }
73 #else
74 #define ca9x4_twd_init() do {} while(0)
75 #endif
76
ct_ca9x4_init_irq(void)77 static void __init ct_ca9x4_init_irq(void)
78 {
79 gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
80 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
81 ca9x4_twd_init();
82 ca9x4_l2_init();
83 }
84
ct_ca9x4_clcd_setup(struct clcd_fb * fb)85 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
86 {
87 unsigned long framesize = 1024 * 768 * 2;
88
89 fb->panel = versatile_clcd_get_panel("XVGA");
90 if (!fb->panel)
91 return -EINVAL;
92
93 return versatile_clcd_setup_dma(fb, framesize);
94 }
95
96 static struct clcd_board ct_ca9x4_clcd_data = {
97 .name = "CT-CA9X4",
98 .caps = CLCD_CAP_5551 | CLCD_CAP_565,
99 .check = clcdfb_check,
100 .decode = clcdfb_decode,
101 .setup = ct_ca9x4_clcd_setup,
102 .mmap = versatile_clcd_mmap_dma,
103 .remove = versatile_clcd_remove_dma,
104 };
105
106 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
107 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
108 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
109 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
110
111 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
112 &clcd_device,
113 &dmc_device,
114 &smc_device,
115 &gpio_device,
116 };
117
118 static struct resource pmu_resources[] = {
119 [0] = {
120 .start = IRQ_CT_CA9X4_PMU_CPU0,
121 .end = IRQ_CT_CA9X4_PMU_CPU0,
122 .flags = IORESOURCE_IRQ,
123 },
124 [1] = {
125 .start = IRQ_CT_CA9X4_PMU_CPU1,
126 .end = IRQ_CT_CA9X4_PMU_CPU1,
127 .flags = IORESOURCE_IRQ,
128 },
129 [2] = {
130 .start = IRQ_CT_CA9X4_PMU_CPU2,
131 .end = IRQ_CT_CA9X4_PMU_CPU2,
132 .flags = IORESOURCE_IRQ,
133 },
134 [3] = {
135 .start = IRQ_CT_CA9X4_PMU_CPU3,
136 .end = IRQ_CT_CA9X4_PMU_CPU3,
137 .flags = IORESOURCE_IRQ,
138 },
139 };
140
141 static struct platform_device pmu_device = {
142 .name = "arm-pmu",
143 .id = -1,
144 .num_resources = ARRAY_SIZE(pmu_resources),
145 .resource = pmu_resources,
146 };
147
148 static struct clk_lookup osc1_lookup = {
149 .dev_id = "ct:clcd",
150 };
151
152 static struct platform_device osc1_device = {
153 .name = "vexpress-osc",
154 .id = 1,
155 .num_resources = 1,
156 .resource = (struct resource []) {
157 VEXPRESS_RES_FUNC(0xf, 1),
158 },
159 .dev.platform_data = &osc1_lookup,
160 };
161
ct_ca9x4_init(void)162 static void __init ct_ca9x4_init(void)
163 {
164 int i;
165
166 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
167 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
168
169 platform_device_register(&pmu_device);
170 vexpress_syscfg_device_register(&osc1_device);
171 }
172
173 #ifdef CONFIG_SMP
174 static void *ct_ca9x4_scu_base __initdata;
175
ct_ca9x4_init_cpu_map(void)176 static void __init ct_ca9x4_init_cpu_map(void)
177 {
178 int i, ncores;
179
180 ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
181 if (WARN_ON(!ct_ca9x4_scu_base))
182 return;
183
184 ncores = scu_get_core_count(ct_ca9x4_scu_base);
185
186 if (ncores > nr_cpu_ids) {
187 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
188 ncores, nr_cpu_ids);
189 ncores = nr_cpu_ids;
190 }
191
192 for (i = 0; i < ncores; ++i)
193 set_cpu_possible(i, true);
194 }
195
ct_ca9x4_smp_enable(unsigned int max_cpus)196 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
197 {
198 scu_enable(ct_ca9x4_scu_base);
199 }
200 #endif
201
202 struct ct_desc ct_ca9x4_desc __initdata = {
203 .id = V2M_CT_ID_CA9,
204 .name = "CA9x4",
205 .map_io = ct_ca9x4_map_io,
206 .init_irq = ct_ca9x4_init_irq,
207 .init_tile = ct_ca9x4_init,
208 #ifdef CONFIG_SMP
209 .init_cpu_map = ct_ca9x4_init_cpu_map,
210 .smp_enable = ct_ca9x4_smp_enable,
211 #endif
212 };
213